Code review comment for lp:~xnox/landscape-client/s390x

We are targeting these two microprocessors:
https://en.wikipedia.org/wiki/IBM_z13_(microprocessor)
https://en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)

L1,L2 caches are per core, L3 is shared. The L3 shared cache is not reported, but for the below z chip it would have been 64MB.

There is also storage controller per compute drawer with like extra 960MiB of L4 cache, per two chips, thus 480 MiB per core.

The cache-size reported up to landscape for x86_64 for my cpu is the shared L3 cache, for z that kind of matches the shared L3 cache as reported:
cache4 : level=3 type=Unified scope=Shared size=65536K line_size=256 associativity=16

Or do you want the largest one? Cause then it would be L4 cache (non-existant on x86_64) from the co-processing unit:
cache5 : level=4 type=Unified scope=Shared size=491520K line_size=256 associativity=30

I guess i should go for the largest one? Cause i guess ultimately cpuinfo simply reports the largest cache. Then for z13 that would be 480 MiB. I'll add that in, just to show off really how big these things are. =)