There have been reports of approximately a 0.9%-1.7% failure rate in SMU
communication timeouts with s0i3 entry on some OEM designs. Currently
the design in amd-pmc is to try every 100us for up to 20ms.
However the GPU driver which also communicates with the SMU using a
mailbox register which the driver polls every 1us for up to 2000ms.
In the GPU driver this was increased by commit 055162645a40 ("drm/amd/pm:
increase time out value when sending msg to SMU")
Increase the maximum timeout used by amd-pmc to 2000ms to match this
behavior. This has been shown to improve the stability for machines
that randomly have failures.
Cc: <email address hidden>
Reported-by: Julian Sikorski <email address hidden>
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1629
Signed-off-by: Mario Limonciello <email address hidden>
Acked-by: Shyam Sundar S K <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Hans de Goede <email address hidden>
(cherry picked from commit 3c3c8e88c8712bfe06cd10d7ca77a94a33610cd6)
Signed-off-by: You-Sheng Yang <email address hidden>
io_uring: ensure symmetry in handling iter types in loop_rw_iter()
When setting up the next segment, we check what type the iter is and
handle it accordingly. However, when incrementing and processed amount
we do not, and both iter advance and addr/len are adjusted, regardless
of type. Split the increment side just like we do on the setup side.
Fixes: 4017eb91a9e7 ("io_uring: make loop_rw_iter() use original user supplied pointers")
Cc: <email address hidden>
Reported-by: Valentina Palmiotti <email address hidden>
Reviewed-by: Pavel Begunkov <email address hidden>
Signed-off-by: Jens Axboe <email address hidden>
(cherry picked from commit 16c8d2df7ec0eed31b7d3b61cb13206a7fb930cc)
CVE-2021-41073
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Timo Aaltonen <email address hidden>
