Linaro GCC

Merge lp:~ramana/gcc-linaro/backport-neon-shiftimm-take2-4.6 into lp:gcc-linaro/4.6

  1. backport-neon-shiftimm-take2-4.6
  2. Merge into 4.6
Proposed by Ramana Radhakrishnan
Status: Merged
Approved by: Richard Sandiford
Approved revision: no longer in the source branch.
Merged at revision: 106772
Proposed branch: lp:~ramana/gcc-linaro/backport-neon-shiftimm-take2-4.6
Merge into: lp:gcc-linaro/4.6
Diff against target: 365 lines (+241/-19)
9 files modified
ChangeLog.linaro (+32/-0)
gcc/config/arm/arm-protos.h (+4/-0)
gcc/config/arm/arm.c (+82/-0)
gcc/config/arm/neon.md (+67/-19)
gcc/config/arm/predicates.md (+20/-0)
gcc/optabs.c (+3/-0)
gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c (+11/-0)
gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c (+11/-0)
gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c (+11/-0)
To merge this branch: bzr merge lp:~ramana/gcc-linaro/backport-neon-shiftimm-take2-4.6
Reviewer Review Type Date Requested Status
Richard Sandiford Approve
Review via email: mp+66796@code.launchpad.net

Description of the change

Proposed for merge to get testing coverage based on comments in review from previous iteration.

Ramana

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cbuild-snapshot: gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6
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Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on x86_64-natty-cbuild148-oort1-x86_64r1.

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The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106767.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/x86_64-natty-cbuild148-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild148-oort1-x86_64r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on armv7l-natty-cbuild149-ursa4-cortexa9r1.

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The test suite results changed compared to the branch point lp:gcc-linaro/4.6+bzr106767:
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c scan-assembler vshr.u32.*#3
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshl-imm-1.c scan-assembler vshl.i32.*#3
 +PASS: gcc.target/arm/neon-vshl-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshr-imm-1.c scan-assembler vshr.s32.*#3
 +PASS: gcc.target/arm/neon-vshr-imm-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/armv7l-natty-cbuild149-ursa4-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild149-ursa4-cortexa9r1

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Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on i686-natty-cbuild151-oort6-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/i686-natty-cbuild151-oort6-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106767.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/i686-natty-cbuild151-oort6-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild151-oort6-i686r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on armv7l-natty-cbuild151-ursa1-armv5r2.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/armv7l-natty-cbuild151-ursa1-armv5r2

The test suite results changed compared to the branch point lp:gcc-linaro/4.6+bzr106767:
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c scan-assembler vshr.u32.*#3
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshl-imm-1.c scan-assembler vshl.i32.*#3
 +PASS: gcc.target/arm/neon-vshl-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshr-imm-1.c scan-assembler vshr.s32.*#3
 +PASS: gcc.target/arm/neon-vshr-imm-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/armv7l-natty-cbuild151-ursa1-armv5r2/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild151-ursa1-armv5r2

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on armv7l-natty-cbuild151-ursa4-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/armv7l-natty-cbuild151-ursa4-cortexa9r1

The test suite results changed compared to the branch point lp:gcc-linaro/4.6+bzr106767:
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c scan-assembler vshr.u32.*#3
 +PASS: gcc.target/arm/neon-vlshr-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshl-imm-1.c scan-assembler vshl.i32.*#3
 +PASS: gcc.target/arm/neon-vshl-imm-1.c (test for excess errors)
 +PASS: gcc.target/arm/neon-vshr-imm-1.c scan-assembler vshr.s32.*#3
 +PASS: gcc.target/arm/neon-vshr-imm-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106768~ramana~backport-neon-shiftimm-take2-4.6/logs/armv7l-natty-cbuild151-ursa4-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild151-ursa4-cortexa9r1

Revision history for this message
Richard Sandiford (rsandifo) wrote :

OK.

review: Approve

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=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro 2011-07-04 11:13:51 +0000
+++ ChangeLog.linaro 2011-07-04 14:15:56 +0000
@@ -1,3 +1,35 @@
12011-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru>
5 Dmitry Melnik <dm@ispras.ru>
6
7 * config/arm/arm.c (neon_immediate_valid_for_shift): New function.
8 (neon_output_shift_immediate): Ditto.
9 * config/arm/arm-protos.h (neon_immediate_valid_for_shift): New
10 prototype.
11 (neon_output_shift_immediate): Ditto.
12 * config/arm/neon.md (vashl<mode>3): Modified constraint.
13 (vashr<mode>3_imm): New insn pattern.
14 (vlshr<mode>3_imm): Ditto.
15 (vashr<mode>3): Modified constraint.
16 (vlshr<mode>3): Ditto.
17 * config/arm/predicates.md (imm_for_neon_lshift_operand): New
18 predicate.
19 (imm_for_neon_rshift_operand): Ditto.
20 (imm_lshift_or_reg_neon): Ditto.
21 (imm_rshift_or_reg_neon): Ditto.
22
23 * optabs.c (init_optabs): Init optab codes for vashl, vashr, vlshr.
24
25 gcc/testsuite
26 2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru>
27 Dmitry Melnik <dm@ispras.ru>
28
29 * gcc.target/arm/neon-vshr-imm-1.c: New testcase.
30 * gcc.target/arm/neon-vshl-imm-1.c: New testcase.
31 * gcc.target/arm/neon-vlshr-imm-1.c: New testcase.
32
12011-07-01 Andrew Stubbs <ams@codesourcery.com>332011-07-01 Andrew Stubbs <ams@codesourcery.com>
234
3 Merge from FSF GCC 4.6.1 (svn branches/gcc-4_6-branch 175677).35 Merge from FSF GCC 4.6.1 (svn branches/gcc-4_6-branch 175677).
436
=== modified file 'gcc/config/arm/arm-protos.h'
--- gcc/config/arm/arm-protos.h 2011-06-14 16:00:30 +0000
+++ gcc/config/arm/arm-protos.h 2011-07-04 14:15:56 +0000
@@ -64,8 +64,12 @@
64extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);64extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
65extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,65extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
66 int *);66 int *);
67extern int neon_immediate_valid_for_shift (rtx, enum machine_mode, rtx *,
68 int *, bool);
67extern char *neon_output_logic_immediate (const char *, rtx *,69extern char *neon_output_logic_immediate (const char *, rtx *,
68 enum machine_mode, int, int);70 enum machine_mode, int, int);
71extern char *neon_output_shift_immediate (const char *, char, rtx *,
72 enum machine_mode, int, bool);
69extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,73extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,
70 rtx (*) (rtx, rtx, rtx));74 rtx (*) (rtx, rtx, rtx));
71extern rtx neon_make_constant (rtx);75extern rtx neon_make_constant (rtx);
7276
=== modified file 'gcc/config/arm/arm.c'
--- gcc/config/arm/arm.c 2011-06-29 09:13:17 +0000
+++ gcc/config/arm/arm.c 2011-07-04 14:15:56 +0000
@@ -8863,6 +8863,66 @@
8863 return 1;8863 return 1;
8864}8864}
88658865
8866/* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
8867 the immediate is valid, write a constant suitable for using as an operand
8868 to VSHR/VSHL to *MODCONST and the corresponding element width to
8869 *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
8870 because they have different limitations. */
8871
8872int
8873neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
8874 rtx *modconst, int *elementwidth,
8875 bool isleftshift)
8876{
8877 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
8878 unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
8879 unsigned HOST_WIDE_INT last_elt = 0;
8880 unsigned HOST_WIDE_INT maxshift;
8881
8882 /* Split vector constant out into a byte vector. */
8883 for (i = 0; i < n_elts; i++)
8884 {
8885 rtx el = CONST_VECTOR_ELT (op, i);
8886 unsigned HOST_WIDE_INT elpart;
8887
8888 if (GET_CODE (el) == CONST_INT)
8889 elpart = INTVAL (el);
8890 else if (GET_CODE (el) == CONST_DOUBLE)
8891 return 0;
8892 else
8893 gcc_unreachable ();
8894
8895 if (i != 0 && elpart != last_elt)
8896 return 0;
8897
8898 last_elt = elpart;
8899 }
8900
8901 /* Shift less than element size. */
8902 maxshift = innersize * 8;
8903
8904 if (isleftshift)
8905 {
8906 /* Left shift immediate value can be from 0 to <size>-1. */
8907 if (last_elt >= maxshift)
8908 return 0;
8909 }
8910 else
8911 {
8912 /* Right shift immediate value can be from 1 to <size>. */
8913 if (last_elt == 0 || last_elt > maxshift)
8914 return 0;
8915 }
8916
8917 if (elementwidth)
8918 *elementwidth = innersize * 8;
8919
8920 if (modconst)
8921 *modconst = CONST_VECTOR_ELT (op, 0);
8922
8923 return 1;
8924}
8925
8866/* Return a string suitable for output of Neon immediate logic operation8926/* Return a string suitable for output of Neon immediate logic operation
8867 MNEM. */8927 MNEM. */
88688928
@@ -8885,6 +8945,28 @@
8885 return templ;8945 return templ;
8886}8946}
88878947
8948/* Return a string suitable for output of Neon immediate shift operation
8949 (VSHR or VSHL) MNEM. */
8950
8951char *
8952neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
8953 enum machine_mode mode, int quad,
8954 bool isleftshift)
8955{
8956 int width, is_valid;
8957 static char templ[40];
8958
8959 is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
8960 gcc_assert (is_valid != 0);
8961
8962 if (quad)
8963 sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
8964 else
8965 sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
8966
8967 return templ;
8968}
8969
8888/* Output a sequence of pairwise operations to implement a reduction.8970/* Output a sequence of pairwise operations to implement a reduction.
8889 NOTE: We do "too much work" here, because pairwise operations work on two8971 NOTE: We do "too much work" here, because pairwise operations work on two
8890 registers-worth of operands in one go. Unfortunately we can't exploit those8972 registers-worth of operands in one go. Unfortunately we can't exploit those
88918973
=== modified file 'gcc/config/arm/neon.md'
--- gcc/config/arm/neon.md 2011-07-01 09:19:21 +0000
+++ gcc/config/arm/neon.md 2011-07-04 14:15:56 +0000
@@ -956,15 +956,57 @@
956; SImode elements.956; SImode elements.
957957
958(define_insn "vashl<mode>3"958(define_insn "vashl<mode>3"
959 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")959 [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
960 (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")960 (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
961 (match_operand:VDQIW 2 "s_register_operand" "w")))]961 (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
962 "TARGET_NEON"962 "TARGET_NEON"
963 "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"963 {
964 [(set (attr "neon_type")964 switch (which_alternative)
965 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))965 {
966 (const_string "neon_vshl_ddd")966 case 0: return "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
967 (const_string "neon_shift_3")))]967 case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2],
968 <MODE>mode,
969 VALID_NEON_QREG_MODE (<MODE>mode),
970 true);
971 default: gcc_unreachable ();
972 }
973 }
974 [(set (attr "neon_type")
975 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
976 (const_string "neon_vshl_ddd")
977 (const_string "neon_shift_3")))]
978)
979
980(define_insn "vashr<mode>3_imm"
981 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
982 (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
983 (match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
984 "TARGET_NEON"
985 {
986 return neon_output_shift_immediate ("vshr", 's', &operands[2],
987 <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
988 false);
989 }
990 [(set (attr "neon_type")
991 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
992 (const_string "neon_vshl_ddd")
993 (const_string "neon_shift_3")))]
994)
995
996(define_insn "vlshr<mode>3_imm"
997 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
998 (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
999 (match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
1000 "TARGET_NEON"
1001 {
1002 return neon_output_shift_immediate ("vshr", 'u', &operands[2],
1003 <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
1004 false);
1005 }
1006 [(set (attr "neon_type")
1007 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1008 (const_string "neon_vshl_ddd")
1009 (const_string "neon_shift_3")))]
968)1010)
9691011
970; Used for implementing logical shift-right, which is a left-shift by a negative1012; Used for implementing logical shift-right, which is a left-shift by a negative
@@ -1004,28 +1046,34 @@
1004(define_expand "vashr<mode>3"1046(define_expand "vashr<mode>3"
1005 [(set (match_operand:VDQIW 0 "s_register_operand" "")1047 [(set (match_operand:VDQIW 0 "s_register_operand" "")
1006 (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")1048 (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
1007 (match_operand:VDQIW 2 "s_register_operand" "")))]1049 (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
1008 "TARGET_NEON"1050 "TARGET_NEON"
1009{1051{
1010 rtx neg = gen_reg_rtx (<MODE>mode);1052 rtx neg = gen_reg_rtx (<MODE>mode);
10111053 if (REG_P (operands[2]))
1012 emit_insn (gen_neg<mode>2 (neg, operands[2]));1054 {
1013 emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));1055 emit_insn (gen_neg<mode>2 (neg, operands[2]));
10141056 emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
1057 }
1058 else
1059 emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2]));
1015 DONE;1060 DONE;
1016})1061})
10171062
1018(define_expand "vlshr<mode>3"1063(define_expand "vlshr<mode>3"
1019 [(set (match_operand:VDQIW 0 "s_register_operand" "")1064 [(set (match_operand:VDQIW 0 "s_register_operand" "")
1020 (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")1065 (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
1021 (match_operand:VDQIW 2 "s_register_operand" "")))]1066 (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
1022 "TARGET_NEON"1067 "TARGET_NEON"
1023{1068{
1024 rtx neg = gen_reg_rtx (<MODE>mode);1069 rtx neg = gen_reg_rtx (<MODE>mode);
10251070 if (REG_P (operands[2]))
1026 emit_insn (gen_neg<mode>2 (neg, operands[2]));1071 {
1027 emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));1072 emit_insn (gen_neg<mode>2 (neg, operands[2]));
10281073 emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
1074 }
1075 else
1076 emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2]));
1029 DONE;1077 DONE;
1030})1078})
10311079
10321080
=== modified file 'gcc/config/arm/predicates.md'
--- gcc/config/arm/predicates.md 2011-06-22 15:50:23 +0000
+++ gcc/config/arm/predicates.md 2011-07-04 14:15:56 +0000
@@ -585,6 +585,26 @@
585 return neon_immediate_valid_for_move (op, mode, NULL, NULL);585 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
586})586})
587587
588(define_predicate "imm_for_neon_lshift_operand"
589 (match_code "const_vector")
590{
591 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
592})
593
594(define_predicate "imm_for_neon_rshift_operand"
595 (match_code "const_vector")
596{
597 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
598})
599
600(define_predicate "imm_lshift_or_reg_neon"
601 (ior (match_operand 0 "s_register_operand")
602 (match_operand 0 "imm_for_neon_lshift_operand")))
603
604(define_predicate "imm_rshift_or_reg_neon"
605 (ior (match_operand 0 "s_register_operand")
606 (match_operand 0 "imm_for_neon_rshift_operand")))
607
588(define_predicate "imm_for_neon_logic_operand"608(define_predicate "imm_for_neon_logic_operand"
589 (match_code "const_vector")609 (match_code "const_vector")
590{610{
591611
=== modified file 'gcc/optabs.c'
--- gcc/optabs.c 2011-03-04 10:27:10 +0000
+++ gcc/optabs.c 2011-07-04 14:15:56 +0000
@@ -6171,6 +6171,9 @@
6171 init_optab (usashl_optab, US_ASHIFT);6171 init_optab (usashl_optab, US_ASHIFT);
6172 init_optab (ashr_optab, ASHIFTRT);6172 init_optab (ashr_optab, ASHIFTRT);
6173 init_optab (lshr_optab, LSHIFTRT);6173 init_optab (lshr_optab, LSHIFTRT);
6174 init_optabv (vashl_optab, ASHIFT);
6175 init_optabv (vashr_optab, ASHIFTRT);
6176 init_optabv (vlshr_optab, LSHIFTRT);
6174 init_optab (rotl_optab, ROTATE);6177 init_optab (rotl_optab, ROTATE);
6175 init_optab (rotr_optab, ROTATERT);6178 init_optab (rotr_optab, ROTATERT);
6176 init_optab (smin_optab, SMIN);6179 init_optab (smin_optab, SMIN);
61776180
=== added file 'gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c'
--- gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c 2011-07-04 14:15:56 +0000
@@ -0,0 +1,11 @@
1/* { dg-do compile } */
2/* { dg-require-effective-target arm_neon_ok } */
3/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
4/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
5
6/* Verify that VSHR immediate is used. */
7void f1(int n, unsigned int x[], unsigned int y[]) {
8 int i;
9 for (i = 0; i < n; ++i)
10 y[i] = x[i] >> 3;
11}
012
=== added file 'gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c'
--- gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c 2011-07-04 14:15:56 +0000
@@ -0,0 +1,11 @@
1/* { dg-do compile } */
2/* { dg-require-effective-target arm_neon_ok } */
3/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
4/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
5
6/* Verify that VSHR immediate is used. */
7void f1(int n, int x[], int y[]) {
8 int i;
9 for (i = 0; i < n; ++i)
10 y[i] = x[i] << 3;
11}
012
=== added file 'gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c'
--- gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c 2011-07-04 14:15:56 +0000
@@ -0,0 +1,11 @@
1/* { dg-do compile } */
2/* { dg-require-effective-target arm_neon_ok } */
3/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
4/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
5
6/* Verify that VSHR immediate is used. */
7void f1(int n, int x[], int y[]) {
8 int i;
9 for (i = 0; i < n; ++i)
10 y[i] = x[i] >> 3;
11}

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