Merge lp:~paul-codesourcery/gcc-linaro/fix-lp-605255 into lp:gcc-linaro/4.4
Status: | Merged |
---|---|
Merged at revision: | 93542 |
Proposed branch: | lp:~paul-codesourcery/gcc-linaro/fix-lp-605255 |
Merge into: | lp:gcc-linaro/4.4 |
Diff against target: |
185 lines (+50/-16) 4 files modified
ChangeLog.linaro (+17/-0) gcc/config/arm/predicates.md (+2/-3) gcc/config/arm/thumb2.md (+13/-13) gcc/testsuite/gcc.dg/long-long-shift-1.c (+18/-0) |
To merge this branch: | bzr merge lp:~paul-codesourcery/gcc-linaro/fix-lp-605255 |
Related bugs: |
Reviewer | Review Type | Date Requested | Status |
---|---|---|---|
Andrew Stubbs (community) | Approve | ||
Review via email: mp+30470@code.launchpad.net |
Description of the change
Fix ICE when building libtheora.
The failure involves a shift of a 64-bit variable inside a loop. The RTL loop
optimizers hoist this out of the loop, turning it into a shift-by-constant.
ARM has no 64-bit shift instruction, so the code for a variable shift looks
something like
low = (count > 32)
? (high >> (count - 32))
: (high << (count -32) | low >> count)
When a constant is substituted for count, some of these shifts become
negative. These will eventually be culled by DCE, but last long enough to
cause problems in the Thumb-2 patterns.
The fix is to tighten up the predicates on the Thumb-2 combined arith+shift
patterns so that only valid shift counts are accepted. The ICE does not effect
pure shifts or ARM mode as those patterns allow the shift count to be
reloaded into a register.
In theory we could allow and substitute alternate values for out-of-range
shifts but, given this is dead code, it's not worth the effort.
Paul, please add something suitable to ChangeLog.linaro. Then update this merge request.
Thanks
Andrew