Merge lp:~michaelh1/gcc-linaro/lp723185 into lp:gcc-linaro/4.6

[Michael Hope]

Backport r172297 from trunk to fix LP: #723185. Now pulls in the offset limit check.

[Linaro Toolchain Builder (cbuild)]

cbuild has taken a snapshot of this branch at r106755 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106755~michaelh1~lp723185.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106755~michaelh1~lp723185
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106754
cbuild-state: check

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on i686-lucid-cbuild127-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106755~michaelh1~lp723185/logs/i686-lucid-cbuild127-scorpius-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106754.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106755~michaelh1~lp723185/logs/i686-lucid-cbuild127-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild127-scorpius-i686r1

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on x86_64-maverick-cbuild127-crucis-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106755~michaelh1~lp723185/logs/x86_64-maverick-cbuild127-crucis-x86_64r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106754.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106755~michaelh1~lp723185/logs/x86_64-maverick-cbuild127-crucis-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-maverick-cbuild127-crucis-x86_64r1

[Richard Sandiford (rsandifo)]

I think you also need:

2011-04-20 Chung-Lin Tang <email address hidden>

 * config/arm/arm.c (arm_legitimize_reload_address): For NEON
 quad-word modes, reduce to 9-bit index range when above 1016 limit.

(fixes http://gcc.gnu.org/ml/gcc-patches/2011-04/msg01635.html )

review: Needs Fixing

[Ramana Radhakrishnan (ramana)]

On 9 June 2011 09:07, Richard Sandiford <email address hidden> wrote:
> Review: Needs Fixing
> I think you also need:

FTR, I had tried to backport the above mentioned fix to the FSF 4.6
branch and saw a few ICEs in the testsuite that I've posted about at
http://gcc.gnu.org/PR48250

cheers
Ramana

>
> 2011-04-20  Chung-Lin Tang  <email address hidden>
>
>        * config/arm/arm.c (arm_legitimize_reload_address): For NEON
>        quad-word modes, reduce to 9-bit index range when above 1016 limit.
>
> (fixes http://gcc.gnu.org/ml/gcc-patches/2011-04/msg01635.html )
>
>
> --
> https://code.launchpad.net/~michaelh1/gcc-linaro/lp723185/+merge/63937
> Your team Linaro Toolchain Developers is subscribed to branch lp:gcc-linaro/4.6.
>

[Michael Hope (michaelh1)]

I'm running this to see if the ICEs that Ramana saw occur.

[Linaro Toolchain Builder (cbuild)]

cbuild has taken a snapshot of this branch at r106756 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106756~michaelh1~lp723185.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106756~michaelh1~lp723185
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106754
cbuild-state: check

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on x86_64-maverick-cbuild127-crucis-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/x86_64-maverick-cbuild127-crucis-x86_64r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106754.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/x86_64-maverick-cbuild127-crucis-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-maverick-cbuild127-crucis-x86_64r1

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild127-ursa4-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild127-ursa4-cortexa9r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106754.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild127-ursa4-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-maverick-cbuild127-ursa4-cortexa9r1

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on i686-lucid-cbuild127-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/i686-lucid-cbuild127-scorpius-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106754.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/i686-lucid-cbuild127-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild127-scorpius-i686r1

[Michael Hope (michaelh1)]

The -mthumb -mfpu=neon build bootstrapped fine with no regressions. I'm running a -marm -mfpu=neon and -mthumb -fpu=vfpv3-d16 as well.

[Chung-Lin Tang (cltang)]

On 2011/6/10 07:51 AM, Michael Hope wrote:
> The -mthumb -mfpu=neon build bootstrapped fine with no regressions. I'm running a -marm -mfpu=neon and -mthumb -fpu=vfpv3-d16 as well.

This patch actually only affects ARM mode. The original ICE should not
have occurred in Thumb-2, IIRC.

[Michael Hope (michaelh1)]

Cortex-A9+NEON+ARM bootstraps fine. The testsuite comes out cleaner due to being in ARM mode.

Cortex-A8+VFP+Thumb2 bootstraps fine. The testsuite seems OK, but it's hard to tell due to the NEON vs non-NEON differences.

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild128-ursa3-cortexa8r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild128-ursa3-cortexa8r1

The test suite was not checked as the branch point lp:gcc-linaro/4.6+bzr106754 has nothing to compare against.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild128-ursa3-cortexa8r1/gcc-testsuite.txt

cbuild-checked: armv7l-maverick-cbuild128-ursa3-cortexa8r1

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild128-ursa4-cortexa9armr1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild128-ursa4-cortexa9armr1

The test suite was not checked as the branch point lp:gcc-linaro/4.6+bzr106754 has nothing to compare against.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~michaelh1~lp723185/logs/armv7l-maverick-cbuild128-ursa4-cortexa9armr1/gcc-testsuite.txt

cbuild-checked: armv7l-maverick-cbuild128-ursa4-cortexa9armr1

[Michael Hope (michaelh1)]

Any thoughts on this? GCC bootstraps in Thumb-2 NEON, Thumb-2 VFP, and ARM NEON modes.

[Richard Sandiford (rsandifo)]

Looks good. Sorry for the slow response.

review: Approve

=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro	2011-06-07 11:18:20 +0000
+++ ChangeLog.linaro	2011-06-09 09:02:19 +0000
@@ -1,3 +1,24 @@
[phone]  Michael Hope  <[e-mail]>
+
+	gcc/
+	Backport from mainline:
+
+	Chung-Lin Tang  <[e-mail]>
+	Richard Earnshaw  <[e-mail]>
+
+	PR target/48250
+	* config/arm/arm.c (arm_legitimize_reload_address): Update cases
+	to use sign-magnitude offsets. Reject unsupported unaligned
+	cases. Add detailed description in comments.
+	* config/arm/arm.md (reload_outdf): Disable for ARM mode; change
+	condition from TARGET_32BIT to TARGET_ARM.
+
+	Chung-Lin Tang  <[e-mail]>
+
+	* config/arm/arm.c (arm_legitimize_reload_address): For NEON
+	quad-word modes, reduce to 9-bit index range when above 1016
+	limit.
+
 2011-06-07  Andrew Stubbs  <[e-mail]>
 
 	Backport from FSF:
 
=== modified file 'gcc/config/arm/arm.c'
--- gcc/config/arm/arm.c	2011-05-11 14:49:48 +0000
+++ gcc/config/arm/arm.c	2011-06-09 09:02:19 +0000
@@ -6419,23 +6419,134 @@
       HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
       HOST_WIDE_INT low, high;
 
-      if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
-	low = ((val & 0xf) ^ 0x8) - 0x8;
-      else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
-	/* Need to be careful, -256 is not a valid offset.  */
-	low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
-      else if (mode == SImode
-	       || (mode == SFmode && TARGET_SOFT_FLOAT)
-	       || ((mode == HImode || mode == QImode) && ! arm_arch4))
-	/* Need to be careful, -4096 is not a valid offset.  */
-	low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
-      else if ((mode == HImode || mode == QImode) && arm_arch4)
-	/* Need to be careful, -256 is not a valid offset.  */
-	low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
-      else if (GET_MODE_CLASS (mode) == MODE_FLOAT
-	       && TARGET_HARD_FLOAT && TARGET_FPA)
-	/* Need to be careful, -1024 is not a valid offset.  */
-	low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
+      /* Detect coprocessor load/stores.  */
+      bool coproc_p = ((TARGET_HARD_FLOAT
+			&& (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
+			&& (mode == SFmode || mode == DFmode
+			    || (mode == DImode && TARGET_MAVERICK)))
+		       || (TARGET_REALLY_IWMMXT
+			   && VALID_IWMMXT_REG_MODE (mode))
+		       || (TARGET_NEON
+			   && (VALID_NEON_DREG_MODE (mode)
+			       || VALID_NEON_QREG_MODE (mode))));
+
+      /* For some conditions, bail out when lower two bits are unaligned.  */
+      if ((val & 0x3) != 0
+	  /* Coprocessor load/store indexes are 8-bits + '00' appended.  */
+	  && (coproc_p
+	      /* For DI, and DF under soft-float: */
+	      || ((mode == DImode || mode == DFmode)
+		  /* Without ldrd, we use stm/ldm, which does not
+		     fair well with unaligned bits.  */
+		  && (! TARGET_LDRD
+		      /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4.  */
+		      || TARGET_THUMB2))))
+	return false;
+
+      /* When breaking down a [reg+index] reload address into [(reg+high)+low],
+	 of which the (reg+high) gets turned into a reload add insn,
+	 we try to decompose the index into high/low values that can often
+	 also lead to better reload CSE.
+	 For example:
+	         ldr r0, [r2, #4100]  // Offset too large
+		 ldr r1, [r2, #4104]  // Offset too large
+
+	 is best reloaded as:
+	         add t1, r2, #4096
+		 ldr r0, [t1, #4]
+		 add t2, r2, #4096
+		 ldr r1, [t2, #8]
+
+	 which post-reload CSE can simplify in most cases to eliminate the
+	 second add instruction:
+	         add t1, r2, #4096
+		 ldr r0, [t1, #4]
+		 ldr r1, [t1, #8]
+
+	 The idea here is that we want to split out the bits of the constant
+	 as a mask, rather than as subtracting the maximum offset that the
+	 respective type of load/store used can handle.
+
+	 When encountering negative offsets, we can still utilize it even if
+	 the overall offset is positive; sometimes this may lead to an immediate
+	 that can be constructed with fewer instructions.
+	 For example:
+	         ldr r0, [r2, #0x3FFFFC]
+
+	 This is best reloaded as:
+	         add t1, r2, #0x400000
+		 ldr r0, [t1, #-4]
+
+	 The trick for spotting this for a load insn with N bits of offset
+	 (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
+	 negative offset that is going to make bit N and all the bits below
+	 it become zero in the remainder part.
+
+	 The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
+	 to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
+	 used in most cases of ARM load/store instructions.  */
+
+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N)					\
+      (((VAL) & ((1 << (N)) - 1))					\
+       ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N))	\
+       : 0)
+
+      if (coproc_p)
+	{
+	  low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
+
+	  /* NEON quad-word load/stores are made of two double-word accesses,
+	     so the valid index range is reduced by 8. Treat as 9-bit range if
+	     we go over it.  */
+	  if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016)
+	    low = SIGN_MAG_LOW_ADDR_BITS (val, 9);
+	}
+      else if (GET_MODE_SIZE (mode) == 8)
+	{
+	  if (TARGET_LDRD)
+	    low = (TARGET_THUMB2
+		   ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
+		   : SIGN_MAG_LOW_ADDR_BITS (val, 8));
+	  else
+	    /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
+	       to access doublewords. The supported load/store offsets are
+	       -8, -4, and 4, which we try to produce here.  */
+	    low = ((val & 0xf) ^ 0x8) - 0x8;
+	}
+      else if (GET_MODE_SIZE (mode) < 8)
+	{
+	  /* NEON element load/stores do not have an offset.  */
+	  if (TARGET_NEON_FP16 && mode == HFmode)
+	    return false;
+
+	  if (TARGET_THUMB2)
+	    {
+	      /* Thumb-2 has an asymmetrical index range of (-256,4096).
+		 Try the wider 12-bit range first, and re-try if the result
+		 is out of range.  */
+	      low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
+	      if (low < -255)
+		low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
+	    }
+	  else
+	    {
+	      if (mode == HImode || mode == HFmode)
+		{
+		  if (arm_arch4)
+		    low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
+		  else
+		    {
+		      /* The storehi/movhi_bytes fallbacks can use only
+			 [-4094,+4094] of the full ldrb/strb index range.  */
+		      low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
+		      if (low == 4095 || low == -4095)
+			return false;
+		    }
+		}
+	      else
+		low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
+	    }
+	}
       else
 	return false;
 
 
=== modified file 'gcc/config/arm/arm.md'
--- gcc/config/arm/arm.md	2011-06-02 15:58:33 +0000
+++ gcc/config/arm/arm.md	2011-06-09 09:02:19 +0000
@@ -6245,7 +6245,7 @@
   [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
    (match_operand:DF 1 "s_register_operand" "r")
    (match_operand:SI 2 "s_register_operand" "=&r")]
-  "TARGET_32BIT"
+  "TARGET_THUMB2"
   "
   {
     enum rtx_code code = GET_CODE (XEXP (operands[0], 0));