Merge lp:~epics-core/epics-base/devlib2mmio into lp:~epics-core/epics-base/3.15

[mdavidsaver]

From devLib2
adds calls to handle 8, 16, and 32 bit
Memory Mapped I/O reads and writes.

Adds X_iowriteY() and X_ioreadY().

where X is nat (native), be, or le.
Y is 16 or 32.

Also adds ioread8() and iowrite8().

[Ben Franksen (bfrk)]

Am Freitag, 10. Mai 2013, 22:33:26 schrieb mdavidsaver:
> mdavidsaver has proposed merging lp:~epics-core/epics-base/devlib2mmio into
> lp:epics-base.
>
> Requested reviews:
> EPICS Core Developers (epics-core)
>
> For more details, see:
> https://code.launchpad.net/~epics-core/epics-base/devlib2mmio/+merge/163365
>
> >From devLib2
>
> adds calls to handle 8, 16, and 32 bit
> Memory Mapped I/O reads and writes.
>
> Adds X_iowriteY() and X_ioreadY().
>
> where X is nat (native), be, or le.
> Y is 16 or 32.
>
> Also adds ioread8() and iowrite8().

+1 from me, it's high time something like this gets into base.

Cheers
--
Ben Franksen
() ascii ribbon campaign - against html e-mail
/\ www.asciiribbon.org - against proprietary attachm€nts

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[lp:~epics-core/epics-base/devlib2mmio]

12417. By mdavidsaver on 2013-08-23

rtems: mmio for m68k

[Andrew Johnson (anj)]

Michael, I'd like to merge this branch (I know, finally!), but there's no code in Base that actually uses the macros that it defines, so I don't know whether code using it would even compile for all our supported targets. If it had a test program that instantiated all the routines we would know that it compiles everywhere and can be linked into an executable that can be loaded. It also needs an announcement in the Release Notes, and documentation for the API in the Application Developers Guide (section 20.21 could probably use a major overhaul anyway).

review: Needs Fixing

[lp:~epics-core/epics-base/devlib2mmio]

12418. By mdavidsaver on 2013-11-30

update release notes

12419. By mdavidsaver on 2013-11-30

fix copyright header

12420. By mdavidsaver on 2013-11-30

test epicsMMIO.h

Check byte order swapping.

[mdavidsaver (mdavidsaver)]

Added release notes and unit test of byte order swapping. Also added documentation at lp:~mdavidsaver/epics-appdev/devlib2mmio

[Andrew Johnson (anj)]

When I started testing this code on VxWorks I came up with a major problem: There are two non-standards for the sysIn*/sysOut* PCIbus access routine names, and older (68K-based) boards don't have them at all.

The code works fine on the mv2700, mv5100 and mv6100 BSPs, but it won't load on the mv2100 or mv3100 without modifying the BSP. When I load the libCom tests on those boards I get this:

mv3100> load "bin/vxWorks-ppc32sf/libComTestHarness.munch"
Warning: module 0x31a9c0 holds reference to undefined symbol sysIn32.
Warning: module 0x31a9c0 holds reference to undefined symbol sysIn16.
Warning: module 0x31a9c0 holds reference to undefined symbol sysOut16.
Warning: module 0x31a9c0 holds reference to undefined symbol sysOut32.
ld(): module contains undefined symbol(s) and may be unusable.
value = 0 = 0x0

On these BSPs the access routines are named sysInLong(), sysInWord(), sysOutLong() and sysOutWord(), and of course we can't distinguish between them at compile-time since the same object code can be loaded on most boards.

On the 68K-based BSPs that don't have a PCIbus, I get this:

5.5.2> load "bin/vxWorks-68040/libComTestHarness.munch"
undefined symbol: _sysOutByte
undefined symbol: _sysInByte
undefined symbol: _sysOut16
undefined symbol: _sysIn16
undefined symbol: _sysOut32
undefined symbol: _sysIn32
ld error: Module contains undefined symbol(s) and may be unusable.
value = 0 = 0x0

The 68K family use a.out format binaries which don't support weak symbols, but those are available o the PowerPC boards and could be used. A better solution though would be to do symbol look-ups with symFindByNameEPICS() at C++ static initialization time, which will work on all architectures.

Sorry it has taken me this long to bring this issue to your attention.

- Andrew

[Andrew Johnson (anj)]

AJ to check args for sysInWord(), sysInLong() etc. MD to look at weak symbol implementation for VxWorks. Will try to fix this week.

[lp:~epics-core/epics-base/devlib2mmio]

12421. By mdavidsaver on 2014-07-16

mmio: vxWorks m68k use default, add weak symbols for old versions

[mdavidsaver (mdavidsaver)]

I've made at attempt at vxWorks 5.5 support. m68k uses the default (as with RTEMS). For other architectures a weak symbol version of the sysIn* sysOut* functions is added which uses the default implementation.

[Andrew Johnson (anj)]

This isn't actually VxWorks 5.5 support, it's support for certain BSPs, irrespective of OS version.

I just grepped through the sources for all the BSPs I have installed and noticed that all the PowerPC and Intel ones implement sys{In|Out}{Byte|Word|Long}. It's the sys{In|Out}{16,32} routines that only exist on a subset of the boards, so I think you can drop the weak symbol stuff if you switch to using the former routines. You will still need your default implementation for m68k though.

Note that the BSP implementations add sync and/or eieio instructions as appropriate after doing the I/O operation, which I don't think your native versions can do.

Sorry for misleading you about this, I should have checked more carefully before.

[mdavidsaver (mdavidsaver)]

Are the sys{In|Out}{Byte|Word|Long} prototypes present in any public headers?

Also, are the argument types of these functions char|short|int?

review: Needs Fixing

[lp:~epics-core/epics-base/devlib2mmio]

12422. By mdavidsaver on 2014-07-25

switch to use sysInWord and friends

[mdavidsaver (mdavidsaver)]

Done (assuming function prototypes are the same)

review: Needs Resubmitting

[lp:~epics-core/epics-base/devlib2mmio]

12423. By Andrew Johnson on 2014-07-31

Fixes for VxWorks implementation.

[Andrew Johnson (anj)]

The sys{In|Out}{Byte|Word|Long}() routines are declared in sysLib.h. On most architectures the address argument is a ULONG (same as epicsUInt32), except on x86 where it's an int (but that doesn't seem to matter). I removed your redeclarations and added appropriate casts to the various read and write functions, and fixed the 68K check in the header file. The result built on all my architectures and the tests all passed on my mv2100, so I committed my changes.

Then I ran the tests on my mv6100. Here the 16- and 32-bit tests fail (running the exact same binary):

# 16-bit ops
not ok 3 - H16.u16==0x1234
ok 4 - nat_ioread16(&H16.bytes)==0x1234
not ok 5 - H16.u16==BE16
ok 6 - be_ioread16(&H16.bytes)==0x1234
not ok 7 - H16.u16==LE16
ok 8 - le_ioread16(&H16.bytes)==0x1234
# 32-bit ops
not ok 9 - H32.u32==0x12345678
ok 10 - nat_ioread32(&H32.bytes)==0x12345678
not ok 11 - H32.u32==BE32
ok 12 - be_ioread32(&H32.bytes)==0x12345678
not ok 13 - H32.u32==LE32
ok 14 - le_ioread32(&H32.bytes)==0x12345678

Ouch, that looks like a byte-swapping issue, so I made the mistake of looking more closely at the implementations of sysInWord(), sysOutWord() and their relatives.

Children, please stop whatever you are doing immediately, go outside, and run away as far and as fast as you can. Don't stop running until it starts getting dark. Then find someplace to hide, shut your eyes and go to sleep. Never come to this place again.

[lp:~epics-core/epics-base/devlib2mmio]

12424. By Andrew Johnson on 2014-08-01

Fix vxWorks again, passes the tests on all my CPUs now.

[mdavidsaver (mdavidsaver)]

Are there any outstanding issues or requests on this branch?

[Andrew Johnson (anj)]

Nope.

review: Approve

[Andrew Johnson (anj)]

We forgot to test on Windows:

cl -nologo -D__STDC__=0 -D_CRT_SECURE_NO_DEPRECATE -D_CRT_NONSTDC_NO_DEPRECATE -Ox -GL -Oy- -W3 -w44355 -MT -I. -I../O.Common -I. -I. -I.. -I../../../../include/compiler/msvc -I../../../../include/os/WIN32 -I../../../../include -c ../epicsMMIOTest.c epicsMMIOTest.c
c:\jenkins\win32-1\workspace\epics-base-3.15-win32\include\os\win32\epicsMMIODef.h(116) : fatal error C1083: Cannot open include file: 'arpa/inet.h': No such file or directory

What is arpa/inet.h for?

[mdavidsaver (mdavidsaver)]

byte swapping w/ hton*()

[Andrew Johnson (anj)]

Needs Winsock2.h on Windows, according to this:
  http://msdn.microsoft.com/en-us/library/windows/desktop/ms738557(v=vs.85).aspx

We include that or arpa/inet.h in osdSock.h. I'll fix epicsMMIODef.h and commit.

[Andrew Johnson (anj)]

I also removed the "special RTEMS" code from epicsMMIODef.h. If the comment about the pc386 bsp was correct the fix should go in osdSock.h.

[Andrew Johnson (anj)]

If you can work out how to fix the remaining name decoration issue please go ahead, I have to switch to other work now.

=== modified file 'documentation/RELEASE_NOTES.html'
--- documentation/RELEASE_NOTES.html	2014-07-31 17:45:40 +0000
+++ documentation/RELEASE_NOTES.html	2014-08-01 21:06:59 +0000
@@ -15,6 +15,7 @@
 <h2 align="center">Changes between 3.15.0.1 and 3.15.0.2</h2>
 <!-- Insert new items immediately below here ... -->
 
+<<<<<<< TREE
 <h3>Implement EPICS_CAS_INTF_ADDR_LIST in rsrv</h3>
 
 <p>The IOC server can now bind to a single IP address (and optional port number)
@@ -130,6 +131,15 @@
 when changing this on applications where the IVOA field of output records is
 used, IVOA still requires an INVALID severity to trigger value replacement.</p>
 
+=======
+<h3>merge MMIO API from devLib2</h3>
+
+<p>adds calls to handle 8, 16, and 32 bit Memory Mapped I/O reads and writes.
+The calls added include X_iowriteY() and X_ioreadY().
+Where X is nat (native), be, or le, and Y is 16 or 32.
+Also added are ioread8() and iowrite8().</p>
+
+>>>>>>> MERGE-SOURCE
 <h3>New build target <q>tapfiles</q></h3>
 
 <p>This new make target runs the same tests as the <q>runtests</q> target, but

=== modified file 'src/libCom/osi/Makefile'
--- src/libCom/osi/Makefile	2014-05-23 19:14:49 +0000
+++ src/libCom/osi/Makefile	2014-08-01 21:06:59 +0000
@@ -61,6 +61,8 @@
 INC += devLibVME.h
 INC += devLibVMEImpl.h
 INC += osdVME.h
+INC += epicsMMIO.h
+INC += epicsMMIODef.h
 
 Com_SRCS += epicsThread.cpp
 Com_SRCS += epicsMutex.cpp

=== added file 'src/libCom/osi/os/RTEMS/epicsMMIO.h'
--- src/libCom/osi/os/RTEMS/epicsMMIO.h	1970-01-01 00:00:00 +0000
+++ src/libCom/osi/os/RTEMS/epicsMMIO.h	2014-08-01 21:06:59 +0000
@@ -0,0 +1,58 @@
+/*************************************************************************\
+* Copyright (c) 2010 Brookhaven Science Associates, as Operator of
+*     Brookhaven National Laboratory.
+* EPICS BASE is distributed subject to a Software License Agreement found
+* in file LICENSE that is included with this distribution.
+\*************************************************************************/
+/*
+ * Author: Michael Davidsaver <[e-mail]>
+ */
+
+#ifndef EPICSMMIO_H
+#define EPICSMMIO_H
+
+#include <epicsEndian.h>
+
+#if defined(_ARCH_PPC) || defined(__PPC__) || defined(__PPC)
+#  include <libcpu/io.h>
+
+/*NOTE: All READ/WRITE operations have an implicit read or write barrier */
+
+#  define ioread8(A)         in_8((volatile epicsUInt8*)(A))
+#  define iowrite8(A,D)      out_8((volatile epicsUInt8*)(A), D)
+#  define le_ioread16(A)     in_le16((volatile epicsUInt16*)(A))
+#  define le_ioread32(A)     in_le32((volatile epicsUInt32*)(A))
+#  define le_iowrite16(A,D)  out_le16((volatile epicsUInt16*)(A), D)
+#  define le_iowrite32(A,D)  out_le32((volatile epicsUInt32*)(A), D)
+#  define be_ioread16(A)     in_be16((volatile epicsUInt16*)(A))
+#  define be_ioread32(A)     in_be32((volatile epicsUInt32*)(A))
+#  define be_iowrite16(A,D)  out_be16((volatile epicsUInt16*)(A), D)
+#  define be_iowrite32(A,D)  out_be32((volatile epicsUInt32*)(A), D)
+
+#  define rbarr()  iobarrier_r()
+#  define wbarr()  iobarrier_w()
+#  define rwbarr() iobarrier_rw()
+
+/* Define native operations */
+#  define nat_ioread16  be_ioread16
+#  define nat_ioread32  be_ioread32
+#  define nat_iowrite16 be_iowrite16
+#  define nat_iowrite32 be_iowrite32
+
+#elif defined(i386) || defined(__i386__) || defined(__i386) || defined(__m68k__)
+
+/* X86 does not need special handling for read/write width.
+ *
+ * TODO: Memory barriers?
+ */
+
+#include "epicsMMIODef.h"
+
+#else
+#  warning I/O operations not defined for this RTEMS architecture
+
+#include "epicsMMIODef.h"
+
+#endif /* if defined PPC */
+
+#endif /* EPICSMMIO_H */

=== added file 'src/libCom/osi/os/default/epicsMMIO.h'
--- src/libCom/osi/os/default/epicsMMIO.h	1970-01-01 00:00:00 +0000
+++ src/libCom/osi/os/default/epicsMMIO.h	2014-08-01 21:06:59 +0000
@@ -0,0 +1,2 @@
+
+#include "epicsMMIODef.h"

=== added file 'src/libCom/osi/os/default/epicsMMIODef.h'
--- src/libCom/osi/os/default/epicsMMIODef.h	1970-01-01 00:00:00 +0000
+++ src/libCom/osi/os/default/epicsMMIODef.h	2014-08-01 21:06:59 +0000
@@ -0,0 +1,268 @@
+/*************************************************************************\
+* Copyright (c) 2010 Brookhaven Science Associates, as Operator of
+*     Brookhaven National Laboratory.
+* EPICS BASE is distributed subject to a Software License Agreement found
+* in file LICENSE that is included with this distribution.
+\*************************************************************************/
+/*
+ * Author: Michael Davidsaver <[e-mail]>
+ */
+
+#ifndef EPICSMMIODEF_H
+#define EPICSMMIODEF_H
+
+#include <epicsTypes.h>
+#include <epicsEndian.h>
+#include <shareLib.h>
+
+#ifdef __cplusplus
+#  ifndef INLINE
+#    define INLINE inline
+#  endif
+#endif
+
+/** @ingroup mmio
+ *@{
+ */
+
+/** @brief Read a single byte.
+ */
+INLINE
+epicsUInt8
+ioread8(volatile void* addr)
+{
+    return *(volatile epicsUInt8*)(addr);
+}
+
+/** @brief Write a single byte.
+ */
+INLINE
+void
+iowrite8(volatile void* addr, epicsUInt8 val)
+{
+    *(volatile epicsUInt8*)(addr) = val;
+}
+
+/** @brief Read two bytes in host order.
+ * Not byte swapping
+ */
+INLINE
+epicsUInt16
+nat_ioread16(volatile void* addr)
+{
+    return *(volatile epicsUInt16*)(addr);
+}
+
+/** @brief Write two byte in host order.
+ * Not byte swapping
+ */
+INLINE
+void
+nat_iowrite16(volatile void* addr, epicsUInt16 val)
+{
+    *(volatile epicsUInt16*)(addr) = val;
+}
+
+/** @brief Read four bytes in host order.
+ * Not byte swapping
+ */
+INLINE
+epicsUInt32
+nat_ioread32(volatile void* addr)
+{
+    return *(volatile epicsUInt32*)(addr);
+}
+
+/** @brief Write four byte in host order.
+ * Not byte swapping
+ */
+INLINE
+void
+nat_iowrite32(volatile void* addr, epicsUInt32 val)
+{
+    *(volatile epicsUInt32*)(addr) = val;
+}
+
+#if EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG
+
+/** @ingroup mmio
+ *@{
+ */
+
+#define bswap16(value) ((epicsUInt16) (  \
+        (((epicsUInt16)(value) & 0x00ff) << 8)    |       \
+        (((epicsUInt16)(value) & 0xff00) >> 8)))
+
+#define bswap32(value) (  \
+        (((epicsUInt32)(value) & 0x000000ff) << 24)   |                \
+        (((epicsUInt32)(value) & 0x0000ff00) << 8)    |                \
+        (((epicsUInt32)(value) & 0x00ff0000) >> 8)    |                \
+        (((epicsUInt32)(value) & 0xff000000) >> 24))
+
+#  define be_ioread16(A)    nat_ioread16(A)
+#  define be_ioread32(A)    nat_ioread32(A)
+#  define be_iowrite16(A,D) nat_iowrite16(A,D)
+#  define be_iowrite32(A,D) nat_iowrite32(A,D)
+
+#  define le_ioread16(A)    bswap16(nat_ioread16(A))
+#  define le_ioread32(A)    bswap32(nat_ioread32(A))
+#  define le_iowrite16(A,D) nat_iowrite16(A,bswap16(D))
+#  define le_iowrite32(A,D) nat_iowrite32(A,bswap32(D))
+
+/** @} */
+
+#elif EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE
+
+#include <arpa/inet.h>
+#ifdef __rtems__
+   /* some rtems bsps (pc386) don't provide htonl correctly */
+#  include <rtems/endian.h>
+#endif
+
+/** @ingroup mmio
+ *@{
+ */
+
+/* hton* is optimized or a builtin for most compilers
+ * so use it if possible
+ */
+#define bswap16(v) htons(v)
+#define bswap32(v) htonl(v)
+
+#  define be_ioread16(A)    bswap16(nat_ioread16(A))
+#  define be_ioread32(A)    bswap32(nat_ioread32(A))
+#  define be_iowrite16(A,D) nat_iowrite16(A,bswap16(D))
+#  define be_iowrite32(A,D) nat_iowrite32(A,bswap32(D))
+
+#  define le_ioread16(A)    nat_ioread16(A)
+#  define le_ioread32(A)    nat_ioread32(A)
+#  define le_iowrite16(A,D) nat_iowrite16(A,D)
+#  define le_iowrite32(A,D) nat_iowrite32(A,D)
+
+/** @} */
+
+#else
+#  error Unable to determine native byte order
+#endif
+
+/** @def bswap16
+ *  @brief Unconditional two byte swap
+ */
+/** @def bswap32
+ *  @brief Unconditional four byte swap
+ */
+/** @def be_ioread16
+ *  @brief Read two byte in big endian order.
+ */
+/** @def be_iowrite16
+ *  @brief Write two byte in big endian order.
+ */
+/** @def be_ioread32
+ *  @brief Read four byte in big endian order.
+ */
+/** @def be_iowrite32
+ *  @brief Write four byte in big endian order.
+ */
+/** @def le_ioread16
+ *  @brief Read two byte in little endian order.
+ */
+/** @def le_iowrite16
+ *  @brief Write two byte in little endian order.
+ */
+/** @def le_ioread32
+ *  @brief Read four byte in little endian order.
+ */
+/** @def le_iowrite32
+ *  @brief Write four byte in little endian order.
+ */
+
+/** @ingroup mmio
+ *@{
+ */
+
+/** @brief Explicit read memory barrier
+ * Prevents reordering of reads around it.
+ */
+#define rbarr()  do{}while(0)
+/** @brief Explicit write memory barrier
+ * Prevents reordering of writes around it.
+ */
+#define wbarr()  do{}while(0)
+/** @brief Explicit read/write memory barrier
+ * Prevents reordering of reads or writes around it.
+ */
+#define rwbarr() do{}while(0)
+
+/** @} */
+
+/** @defgroup mmio Memory Mapped I/O
+ *
+ * Safe operations on I/O memory.
+ *
+ *This files defines a set of macros for access to Memory Mapped I/O
+ *
+ *They are named T_ioread# and T_iowrite# where # can be 8, 16, or 32.
+ *'T' can either be 'le', 'be', or 'nat' (except ioread8 and
+ *iowrite8).
+ *
+ *The macros defined use OS specific extensions (when available)
+ *to ensure the following.
+ *
+ *@li Width.  A 16 bit operation will not be broken into two 8 bit operations,
+ *           or one half of a 32 bit operation.
+ *
+ *@li Order.  Writes to two different registers will not be reordered.
+ *           This only applies to MMIO operations, not between MMIO and
+ *           normal memory operations.
+ *
+ *PCI access should use either 'le_' or 'be_' as determined by the
+ *device byte order.
+ *
+ *VME access should always use 'nat_'.  If the device byte order is
+ *little endian then an explicit swap is required.
+ *
+ *@section mmioex Examples:
+ *
+ *@subsection mmioexbe Big endian device:
+ *
+ *@b PCI
+ *
+ @code
+  be_iowrite16(base+off, 14);
+  var = be_ioread16(base+off);
+ @endcode
+ *
+ *@b VME
+ *
+ @code
+  nat_iowrite16(base+off, 14);
+  var = nat_ioread16(base+off);
+ @endcode
+ *
+ *@subsection mmioexle Little endian device
+ *
+ *@b PCI
+ @code
+  le_iowrite16(base+off, 14);
+  var = le_ioread16(base+off);
+ @endcode
+ *@b VME
+ @code
+  nat_iowrite16(base+off, bswap16(14));
+  var = bswap16(nat_iowrite16(base+off));
+ @endcode
+ *This difference arises because VME bridges implement hardware byte
+ *swapping on little endian systems, while PCI bridges do not.
+ *Software accessing PCI devices must know if byte swapping is required.
+ *This conditional swap is implemented by the 'be_' and 'le_' macros.
+ *
+ *This is a fundamental difference between PCI and VME.
+ *
+ *Software accessing PCI @b must do conditional swapping.
+ *
+ *Software accessing VME must @b not do conditional swapping.
+ *
+ *@note All read and write operations have an implicit read or write barrier.
+ */
+
+#endif /* EPICSMMIODEF_H */

=== added file 'src/libCom/osi/os/vxWorks/epicsMMIO.h'
--- src/libCom/osi/os/vxWorks/epicsMMIO.h	1970-01-01 00:00:00 +0000
+++ src/libCom/osi/os/vxWorks/epicsMMIO.h	2014-08-01 21:06:59 +0000
@@ -0,0 +1,160 @@
+/*************************************************************************\
+* Copyright (c) 2014 Brookhaven Science Associates, as Operator of
+*     Brookhaven National Laboratory.
+* Copyright (c) 2014 UChicago Argonne LLC, as Operator of Argonne
+*     National Laboratory.
+* Copyright (c) 2006 The Regents of the University of California,
+*     as Operator of Los Alamos National Laboratory.
+* Copyright (c) 2006 The Board of Trustees of the Leland Stanford Junior
+*     University, as Operator of the Stanford Linear Accelerator Center.
+* EPICS BASE is distributed subject to a Software License Agreement found
+* in file LICENSE that is included with this distribution.
+\*************************************************************************/
+/*
+ * Original Author: Eric Bjorklund  (was called mrfSyncIO.h)
+ * Author: Michael Davidsaver <[e-mail]>
+ */
+
+#ifndef EPICSMMIO_H
+#define EPICSMMIO_H
+
+#if (CPU_FAMILY != PPC) && (CPU_FAMILY != I80X86)
+#  include "epicsMMIODef.h"
+#else
+
+/**************************************************************************************************/
+/*  Required Header Files                                                                         */
+/**************************************************************************************************/
+
+/* This is needed on vxWorks 6.8 */
+#ifndef _VSB_CONFIG_FILE
+#  define _VSB_CONFIG_FILE <../lib/h/config/vsbConfig.h>
+#endif
+
+#include  <vxWorks.h>                           /* vxWorks common definitions                     */
+#include  <sysLib.h>                            /* vxWorks System Library Definitions             */
+#include  <version.h>                           /* vxWorks Version Definitions                    */
+
+#include  <epicsTypes.h>                        /* EPICS Common Type Definitions                  */
+#include  <epicsEndian.h>                       /* EPICS Byte Order Definitions                   */
+
+/*=====================
+ * vxAtomicLib.h (which defines the memory barrier macros)
+ * is available on vxWorks 6.6 and above.
+ */
+
+#if _WRS_VXWORKS_MAJOR > 6
+#  include  <vxAtomicLib.h>
+#elif _WRS_VXWORKS_MAJOR == 6 && _WRS_VXWORKS_MINOR >= 6
+#  include  <vxAtomicLib.h>
+#endif
+
+#define bswap16(value) ((epicsUInt16) (  \
+        (((epicsUInt16)(value) & 0x00ff) << 8)    |       \
+        (((epicsUInt16)(value) & 0xff00) >> 8)))
+
+#define bswap32(value) (  \
+        (((epicsUInt32)(value) & 0x000000ff) << 24)   |                \
+        (((epicsUInt32)(value) & 0x0000ff00) << 8)    |                \
+        (((epicsUInt32)(value) & 0x00ff0000) >> 8)    |                \
+        (((epicsUInt32)(value) & 0xff000000) >> 24))
+
+#if EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG
+#  define be16_to_cpu(X) (epicsUInt16)(X)
+#  define be32_to_cpu(X) (epicsUInt32)(X)
+#  define le16_to_cpu(X) bswap16(X)
+#  define le32_to_cpu(X) bswap32(X)
+
+#elif EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE
+#  define be16_to_cpu(X) bswap16(X)
+#  define be32_to_cpu(X) bswap32(X)
+#  define le16_to_cpu(X) (epicsUInt16)(X)
+#  define le32_to_cpu(X) (epicsUInt32)(X)
+
+#else
+#  error Unable to determine native byte order
+#endif
+
+#if CPU_FAMILY == PPC
+
+/* All PowerPC BSPs that I have studied implement these functions
+ * with the same definition, byte-swapping the data and adding a
+ * sync and/or eieio instruction as necessary on that CPU board.
+ * They do *not* all implement the sys{In/Out}{Byte/Word/Long}
+ * functions to do the same thing though, so we can't use them.
+ */
+
+UINT8 sysPciInByte(UINT8 *addr);
+void sysPciOutByte(UINT8 *addr, UINT8 data);
+UINT16 sysPciInWord(UINT16 *addr);
+void sysPciOutWord(UINT16 *addr, UINT16 data);
+UINT32 sysPciInLong (UINT32 *addr);
+void sysPciOutLong (UINT32 *addr, UINT32 data);
+
+#define ioread8(address)           sysPciInByte((UINT8 *)(address))
+#define iowrite8(address,data)     sysPciOutByte((UINT8 *)(address), (epicsUInt8)(data))
+
+#define nat_ioread16(address)      bswap16(sysPciInWord((UINT16 *)(address)))
+#define nat_ioread32(address)      bswap32(sysPciInLong((UINT32 *)(address)))
+
+#define nat_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
+#define nat_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
+
+#define be_ioread16(address)       bswap16(sysPciInWord((UINT16 *)(address)))
+#define be_ioread32(address)       bswap32(sysPciInLong((UINT32 *)(address)))
+
+#define be_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
+#define be_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
+
+#define le_ioread16(address)       sysPciInWord((UINT16 *)(address))
+#define le_ioread32(address)       sysPciInLong((UINT32 *)(address))
+
+#define le_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), (data))
+#define le_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), (data))
+
+#else /* CPU_FAMILY == I80X86 */
+
+/* All Intel BSPs should implement the sys{In/Out}{Byte/Word/Long}
+ * functions, which are declared in the sysLib.h header.
+ */
+
+#define ioread8(address)           sysInByte   ((epicsUInt32)(address))
+#define iowrite8(address,data)     sysOutByte  ((epicsUInt32)(address), (epicsUInt8)(data))
+
+#define nat_ioread16(address)      sysInWord ((epicsUInt32)(address))
+#define nat_ioread32(address)      sysInLong ((epicsUInt32)(address))
+
+#define nat_iowrite16(address,data) sysOutWord((epicsUInt32)(address),(data))
+#define nat_iowrite32(address,data) sysOutLong((epicsUInt32)(address),(data))
+
+#define be_ioread16(address)       be16_to_cpu (sysInWord ((epicsUInt32)(address)))
+#define be_ioread32(address)       be32_to_cpu (sysInLong ((epicsUInt32)(address)))
+
+#define be_iowrite16(address,data) sysOutWord    ((epicsUInt32)(address), be16_to_cpu((epicsUInt16)(data)))
+#define be_iowrite32(address,data) sysOutLong    ((epicsUInt32)(address), be32_to_cpu((epicsUInt32)(data)))
+
+#define le_ioread16(address)       le16_to_cpu (sysInWord ((epicsUInt32)(address)))
+#define le_ioread32(address)       le32_to_cpu (sysInLong ((epicsUInt32)(address)))
+
+#define le_iowrite16(address,data) sysOutWord    ((epicsUInt32)(address), le16_to_cpu((epicsUInt16)(data)))
+#define le_iowrite32(address,data) sysOutLong    ((epicsUInt32)(address), le32_to_cpu((epicsUInt32)(data)))
+
+#endif /* I80X86 */
+
+
+#ifndef VX_MEM_BARRIER_R
+#  define VX_MEM_BARRIER_R() do{}while(0)
+#endif
+#ifndef VX_MEM_BARRIER_W
+#  define VX_MEM_BARRIER_W() do{}while(0)
+#endif
+#ifndef VX_MEM_BARRIER_RW
+#  define VX_MEM_BARRIER_RW() do{}while(0)
+#endif
+
+#define rbarr()  VX_MEM_BARRIER_R()
+#define wbarr()  VX_MEM_BARRIER_W()
+#define rwbarr() VX_MEM_BARRIER_RW()
+
+#endif /* CPU_FAMILY */
+#endif /* EPICSMMIO_H */

=== modified file 'src/libCom/test/Makefile'
--- src/libCom/test/Makefile	2014-07-29 21:05:24 +0000
+++ src/libCom/test/Makefile	2014-08-01 21:06:59 +0000
@@ -37,6 +37,11 @@
 testHarness_SRCS += epicsMathTest.c
 TESTS += epicsMathTest
 
+TESTPROD_HOST += epicsMMIOTest
+epicsMMIOTest_SRCS += epicsMMIOTest.c
+testHarness_SRCS += epicsMMIOTest.c
+TESTS += epicsMMIOTest
+
 TESTPROD_HOST += epicsEllTest
 epicsEllTest_SRCS += epicsEllTest.c
 testHarness_SRCS += epicsEllTest.c

=== added file 'src/libCom/test/epicsMMIOTest.c'
--- src/libCom/test/epicsMMIOTest.c	1970-01-01 00:00:00 +0000
+++ src/libCom/test/epicsMMIOTest.c	2014-08-01 21:06:59 +0000
@@ -0,0 +1,87 @@
+/*************************************************************************\
+* Copyright (c) 2013 Brookhaven Science Associates, as Operator of
+*     Brookhaven National Laboratory.
+* EPICS BASE is distributed subject to a Software License Agreement found
+* in file LICENSE that is included with this distribution.
+\*************************************************************************/
+/*
+ * Author: Michael Davidsaver <[e-mail]>
+ */
+
+#include "epicsAssert.h"
+#include "epicsEndian.h"
+#include "epicsTypes.h"
+#include "epicsUnitTest.h"
+#include "testMain.h"
+
+#include "epicsMMIO.h"
+
+#if EPICS_BYTE_ORDER==EPICS_ENDIAN_BIG
+#define BE16 0x1234
+#define BE32 0x12345678
+#define LE16 0x3412
+#define LE32 0x78563412
+#else
+#define LE16 0x1234
+#define LE32 0x12345678
+#define BE16 0x3412
+#define BE32 0x78563412
+#endif
+
+union hydra16 {
+    epicsUInt16 u16;
+    epicsUInt8 bytes[2];
+};
+
+union hydra32 {
+    epicsUInt32 u32;
+    epicsUInt8 bytes[4];
+};
+
+MAIN(epicsMMIOTest)
+{
+    epicsUInt8 B;
+    union hydra16 H16;
+    union hydra32 H32;
+
+    STATIC_ASSERT(sizeof(H16)==2);
+    STATIC_ASSERT(sizeof(H32)==4);
+
+    testPlan(0);
+
+    testDiag("8-bit ops");
+
+    iowrite8(&B, 5);
+    testOk1(B==5);
+    testOk1(ioread8(&B)==5);
+
+    testDiag("16-bit ops");
+
+    nat_iowrite16(&H16.bytes, 0x1234);
+    testOk1(H16.u16==0x1234);
+    testOk1(nat_ioread16(&H16.bytes)==0x1234);
+
+    be_iowrite16(&H16.bytes, 0x1234);
+    testOk1(H16.u16==BE16);
+    testOk1(be_ioread16(&H16.bytes)==0x1234);
+
+    le_iowrite16(&H16.bytes, 0x1234);
+    testOk1(H16.u16==LE16);
+    testOk1(le_ioread16(&H16.bytes)==0x1234);
+
+    testDiag("32-bit ops");
+
+    nat_iowrite32(&H32.bytes, 0x12345678);
+    testOk1(H32.u32==0x12345678);
+    testOk1(nat_ioread32(&H32.bytes)==0x12345678);
+
+    be_iowrite32(&H32.bytes, 0x12345678);
+    testOk1(H32.u32==BE32);
+    testOk1(be_ioread32(&H32.bytes)==0x12345678);
+
+    le_iowrite32(&H32.bytes, 0x12345678);
+    testOk1(H32.u32==LE32);
+    testOk1(le_ioread32(&H32.bytes)==0x12345678);
+
+    return testDone();
+}

=== modified file 'src/libCom/test/epicsRunLibComTests.c'
--- src/libCom/test/epicsRunLibComTests.c	2014-07-31 17:45:40 +0000
+++ src/libCom/test/epicsRunLibComTests.c	2014-08-01 21:06:59 +0000
@@ -18,7 +18,11 @@
 
 int epicsThreadTest(void);
 int epicsTimerTest(void);
+<<<<<<< TREE
 int epicsSpinTest(void);
+=======
+int epicsMMIOTest(void);
+>>>>>>> MERGE-SOURCE
 int epicsAlgorithm(void);
 int epicsEllTest(void);
 int epicsEnvTest(void);
@@ -62,8 +66,13 @@
      */
     runTest(epicsTimerTest);
 
+<<<<<<< TREE
     runTest(epicsSpinTest);
 
+=======
+    runTest(epicsMMIOTest);
+
+>>>>>>> MERGE-SOURCE
     runTest(epicsAlgorithm);
 
     runTest(epicsEllTest);