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Branches

Name Last Modified Last Commit
spe-acpi-disco 2019-07-16 00:28:43 UTC 2019-07-16
perf: arm_spe: Enable ACPI/Platform automatic module loading

Author: Jeremy Linton
Author Date: 2019-06-26 21:37:18 UTC

perf: arm_spe: Enable ACPI/Platform automatic module loading

Lets add the MODULE_TABLE and platform id_table entries so that
the SPE driver can attach to the ACPI platform device created by
the core pmu code.

Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit d482e575fbf0f7ec9319bded951f21bbc84312bf)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hi1620-unstable-v2 2019-06-26 22:26:44 UTC 2019-06-26
RDMa/hns: Don't stuck in endless timeout loop

Author: Leon Romanovsky
Author Date: 2019-06-16 12:05:58 UTC

RDMa/hns: Don't stuck in endless timeout loop

BugLink: https://bugs.launchpad.net/bugs/1830815

The "end" variable is declared as unsigned and can't be negative, it
leads to the situation where timeout limit is not honored, so let's
convert logic to ensure that loop is bounded.

drivers/infiniband/hw/hns/hns_roce_hw_v1.c: In function _hns_roce_v1_clear_hem_:
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2471:12: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
 2471 | if (end < 0) {
      | ^

Fixes: 669cefb654cb ("RDMA/hns: Remove jiffies operation in disable interrupt context")
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
(cherry picked from commit da3929218a4481fc12f9eaa30c9edb09aad5ff24 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hi1620-disco-v3 2019-06-26 22:03:05 UTC 2019-06-26
RDMa/hns: Don't stuck in endless timeout loop

Author: Leon Romanovsky
Author Date: 2019-06-16 12:05:58 UTC

RDMa/hns: Don't stuck in endless timeout loop

BugLink: https://bugs.launchpad.net/bugs/1830815

The "end" variable is declared as unsigned and can't be negative, it
leads to the situation where timeout limit is not honored, so let's
convert logic to ensure that loop is bounded.

drivers/infiniband/hw/hns/hns_roce_hw_v1.c: In function _hns_roce_v1_clear_hem_:
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2471:12: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
 2471 | if (end < 0) {
      | ^

Fixes: 669cefb654cb ("RDMA/hns: Remove jiffies operation in disable interrupt context")
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
(cherry picked from commit da3929218a4481fc12f9eaa30c9edb09aad5ff24 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hi1620-unstable 2019-06-24 16:44:28 UTC 2019-06-24
net: hns3: Fix inconsistent indenting

Author: Krzysztof Kozlowski
Author Date: 2019-06-18 18:54:22 UTC

net: hns3: Fix inconsistent indenting

BugLink: https://bugs.launchpad.net/bugs/1830815

Fix wrong indentation of goto return.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit bf6de2315362473e14817ccbdbd00ade6de2756e linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hi1620-disco-v2 2019-06-21 22:46:51 UTC 2019-06-21
net: hns3: Fix inconsistent indenting

Author: Krzysztof Kozlowski
Author Date: 2019-06-18 18:54:22 UTC

net: hns3: Fix inconsistent indenting

BugLink: https://bugs.launchpad.net/bugs/1830815

Fix wrong indentation of goto return.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit bf6de2315362473e14817ccbdbd00ade6de2756e linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-fixes-bionic 2019-06-18 00:02:31 UTC 2019-06-18
net: hns: fix unsigned comparison to less than zero

Author: Colin Ian King
Author Date: 2019-04-05 13:59:16 UTC

net: hns: fix unsigned comparison to less than zero

BugLink: https://bugs.launchpad.net/bugs/1833140

Currently mskid is unsigned and hence comparisons with negative
error return values are always false. Fix this by making mskid an
int.

Fixes: f058e46855dc ("net: hns: fix ICMP6 neighbor solicitation messages discard problem")
Addresses-Coverity: ("Operands don't affect result")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ea401685a20b5d631957f024bda86e1f6118eb20)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-fixes-cosmic 2019-06-17 23:51:41 UTC 2019-06-17
net: hns: fix unsigned comparison to less than zero

Author: Colin Ian King
Author Date: 2019-04-05 13:59:16 UTC

net: hns: fix unsigned comparison to less than zero

BugLink: https://bugs.launchpad.net/bugs/1833140

Currently mskid is unsigned and hence comparisons with negative
error return values are always false. Fix this by making mskid an
int.

Fixes: f058e46855dc ("net: hns: fix ICMP6 neighbor solicitation messages discard problem")
Addresses-Coverity: ("Operands don't affect result")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ea401685a20b5d631957f024bda86e1f6118eb20)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-fixes-disco 2019-06-17 22:35:41 UTC 2019-06-17
net: hns: Fix loopback test failed at copper ports

Author: Yonglong Liu
Author Date: 2019-05-31 08:59:50 UTC

net: hns: Fix loopback test failed at copper ports

BugLink: https://bugs.launchpad.net/bugs/1833132

When doing a loopback test at copper ports, the serdes loopback
and the phy loopback will fail, because of the adjust link had
not finished, and phy not ready.

Adds sleep between adjust link and test process to fix it.

Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 2e1f164861e500f4e068a9d909bbd3fcc7841483)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hi1620-disco 2019-05-29 00:49:09 UTC 2019-05-29
net: hns3: remove redundant assignment of l2_hdr to itself

Author: Colin Ian King
Author Date: 2019-05-08 10:51:35 UTC

net: hns3: remove redundant assignment of l2_hdr to itself

BugLink: https://bugs.launchpad.net/bugs/1830815

The pointer l2_hdr is being assigned to itself, this is redundant
and can be removed.

Addresses-Coverity: ("Evaluation order violation")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit c264ed44d857c50f43be08572668afa374bf6a48)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

rdma-hns-disco 2019-04-02 22:40:46 UTC 2019-04-02
RDMA/hns: Use GFP_ATOMIC in hns_roce_v2_modify_qp

Author: YueHaibing
Author Date: 2019-03-04 02:56:20 UTC

RDMA/hns: Use GFP_ATOMIC in hns_roce_v2_modify_qp

BugLink: https://bugs.launchpad.net/bugs/1822897

The the below commit, hns_roce_v2_modify_qp is called inside spinlock
while using GFP_KERNEL. Change it to GFP_ATOMIC.

Fixes: 0425e3e6e0c7 ("RDMA/hns: Support flush cqe for hip08 in kernel space")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
(cherry picked from commit 4e69cf1fe2c52d189acdd06c1fd99cc258aba61f)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-disco 2019-03-29 22:37:20 UTC 2019-03-29
scsi: hisi_sas: Add softreset in hisi_sas_I_T_nexus_reset()

Author: Luo Jiaxing
Author Date: 2019-03-20 10:21:34 UTC

scsi: hisi_sas: Add softreset in hisi_sas_I_T_nexus_reset()

BugLink: https://bugs.launchpad.net/bugs/1822385

We found out that for v2 hw, a SATA disk can not be written to after the
system comes up.

In commit ffb1c820b8b6 ("scsi: hisi_sas: remove the check of sas_dev status
in hisi_sas_I_T_nexus_reset()"), we introduced a path where we may issue an
internal abort for a SATA device, but without following it with a
softreset.

We need to always follow an internal abort with a software reset, as per HW
programming flow, so add this.

Fixes: ffb1c820b8b6 ("scsi: hisi_sas: remove the check of sas_dev status in hisi_sas_I_T_nexus_reset()")
Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 0e83fc61eee62979260f6aeadd23ee8b615ee1a2)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

sdei 2019-03-27 23:18:16 UTC 2019-03-27
ACPI / APEI: Add support for the SDEI GHES Notification type

Author: James Morse
Author Date: 2019-01-29 18:49:02 UTC

ACPI / APEI: Add support for the SDEI GHES Notification type

BugLink: https://bugs.launchpad.net/bugs/1822005

If the GHES notification type is SDEI, register the provided event
using the SDEI-GHES helper.

SDEI may be one of two types of event, normal and critical. Critical
events can interrupt normal events, so these must have separate
fixmap slots and locks in case both event types are in use.

Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit f9f05395f384ee858520b6c65d7e3e436af20c53)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-updates-51-mw 2019-03-11 21:22:29 UTC 2019-03-11
net: hns3: fix to stop multiple HNS reset due to the AER changes

Author: Shiju Jose
Author Date: 2019-03-10 06:47:51 UTC

net: hns3: fix to stop multiple HNS reset due to the AER changes

BugLink: https://bugs.launchpad.net/bugs/1819535

The commit bfcb79fca19d
("PCI/ERR: Run error recovery callbacks for all affected devices")
affected the non-fatal error recovery logic for the HNS and RDMA devices.
This is because each HNS PF under PCIe bus receive callbacks
from the AER driver when an error is reported for one of the PF.
This causes unwanted PF resets because
the HNS decides which PF to reset based on the reset type set.
The HNS error handling code sets the reset type based on the hw error
type detected.

This patch provides fix for the above issue for the recovery of
the hw errors in the HNS and RDMA devices.

This patch needs backporting to the kernel v5.0+

Fixes: 332fbf576579 ("net: hns3: add handling of hw ras errors using new set of commands")
Reported-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 69b51bbb03f73e04c486f79d1556b2d9becf4dbc)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-debugfs 2019-03-11 18:16:18 UTC 2019-03-11
scsi: hisi_sas: Add debugfs ITCT file and add file operations

Author: Luo Jiaxing
Author Date: 2019-01-25 14:22:29 UTC

scsi: hisi_sas: Add debugfs ITCT file and add file operations

BugLink: https://bugs.launchpad.net/bugs/1819500

This patch creates debugfs file for ITCT and adds file operations.

Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 5979f33b982dca807ea802b512480bc62f81396a)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

pearl2-5.0.0-2.3 2019-01-31 01:51:28 UTC 2019-01-31
UBUNTU: Ubuntu-5.0.0-2.3~18.04.1+pearl2.1

Author: dann frazier
Author Date: 2019-01-31 01:51:28 UTC

UBUNTU: Ubuntu-5.0.0-2.3~18.04.1+pearl2.1

Signed-off-by: dann frazier <dann.frazier@canonical.com>

pearl2-5.0.0-1.2 2019-01-25 16:20:48 UTC 2019-01-25
UBUNTU: Ubuntu-5.0.0-1.2~18.04.2

Author: dann frazier
Author Date: 2019-01-25 00:29:27 UTC

UBUNTU: Ubuntu-5.0.0-1.2~18.04.2

Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-soc-updates-bionic 2019-01-08 22:30:19 UTC 2019-01-08
net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

Author: Huazhong Tan
Author Date: 2018-12-31 02:58:29 UTC

net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

BugLink: https://bugs.launchpad.net/bugs/1810457

For HNAE3_DOWN_CLIENT calling hns3_nic_net_stop(), HNAE3_UP_CLIENT
should call hns3_nic_net_open(), since if the number of queue or
the map of TC has is changed before HHAE3_UP_CLIENT is called,
it will cause problem.

Also the HNS3_NIC_STATE_RESETTING flag needs to be cleared before
hns3_nic_net_open() called, and set it back while hns3_nic_net_open()
failed.

Fixes: bb6b94a896d4 ("net: hns3: Add reset interface implementation in client")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit e888402789b9db5de4fcda361331d66dbf0cd9fd)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-soc-updates-cosmic 2019-01-08 22:26:41 UTC 2019-01-08
net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

Author: Huazhong Tan
Author Date: 2018-12-31 02:58:29 UTC

net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

BugLink: https://bugs.launchpad.net/bugs/1810457

For HNAE3_DOWN_CLIENT calling hns3_nic_net_stop(), HNAE3_UP_CLIENT
should call hns3_nic_net_open(), since if the number of queue or
the map of TC has is changed before HHAE3_UP_CLIENT is called,
it will cause problem.

Also the HNS3_NIC_STATE_RESETTING flag needs to be cleared before
hns3_nic_net_open() called, and set it back while hns3_nic_net_open()
failed.

Fixes: bb6b94a896d4 ("net: hns3: Add reset interface implementation in client")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit e888402789b9db5de4fcda361331d66dbf0cd9fd)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-soc-updates-disco 2019-01-08 22:25:31 UTC 2019-01-08
net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

Author: Huazhong Tan
Author Date: 2018-12-31 02:58:29 UTC

net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

BugLink: https://bugs.launchpad.net/bugs/1810457

For HNAE3_DOWN_CLIENT calling hns3_nic_net_stop(), HNAE3_UP_CLIENT
should call hns3_nic_net_open(), since if the number of queue or
the map of TC has is changed before HHAE3_UP_CLIENT is called,
it will cause problem.

Also the HNS3_NIC_STATE_RESETTING flag needs to be cleared before
hns3_nic_net_open() called, and set it back while hns3_nic_net_open()
failed.

Fixes: bb6b94a896d4 ("net: hns3: Add reset interface implementation in client")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit e888402789b9db5de4fcda361331d66dbf0cd9fd)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-signed 2019-01-08 20:37:13 UTC 2019-01-08
update changelog for test build

Author: Seth Forshee
Author Date: 2019-01-08 20:37:13 UTC

update changelog for test build

Signed-off-by: Seth Forshee <seth.forshee@canonical.com>

hisi-soc-updates-unstable 2019-01-07 22:40:51 UTC 2019-01-07
net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

Author: Huazhong Tan
Author Date: 2018-12-31 02:58:29 UTC

net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT

BugLink: https://bugs.launchpad.net/bugs/1810457

For HNAE3_DOWN_CLIENT calling hns3_nic_net_stop(), HNAE3_UP_CLIENT
should call hns3_nic_net_open(), since if the number of queue or
the map of TC has is changed before HHAE3_UP_CLIENT is called,
it will cause problem.

Also the HNS3_NIC_STATE_RESETTING flag needs to be cleared before
hns3_nic_net_open() called, and set it back while hns3_nic_net_open()
failed.

Fixes: bb6b94a896d4 ("net: hns3: Add reset interface implementation in client")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit e888402789b9db5de4fcda361331d66dbf0cd9fd)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

iommu-non-strict-bionic 2018-12-20 00:14:18 UTC 2018-12-20
packaging

Author: dann frazier
Author Date: 2018-12-20 00:14:18 UTC

packaging

iommu-non-strict-b 2018-12-20 00:04:16 UTC 2018-12-20
iommu/arm-smmu: Support non-strict mode

Author: Robin Murphy
Author Date: 2018-09-20 16:10:27 UTC

iommu/arm-smmu: Support non-strict mode

BugLink: https://bugs.launchpad.net/bugs/1806488

All we need is to wire up .flush_iotlb_all properly and implement the
domain attribute, and iommu-dma and io-pgtable will do the rest for us.
The only real subtlety is documenting the barrier semantics we're
introducing between io-pgtable and the drivers for non-strict flushes.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(backported from commit 44f6876a00e83df5fd28681502b19b0f51e4a3c6)
[ dannf: trivial context fix in arm_smmu_ops struct ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

iommu-non-strict-cosmic 2018-12-19 03:58:55 UTC 2018-12-19
iommu/arm-smmu: Support non-strict mode

Author: Robin Murphy
Author Date: 2018-09-20 16:10:27 UTC

iommu/arm-smmu: Support non-strict mode

BugLink: https://bugs.launchpad.net/bugs/1806488

All we need is to wire up .flush_iotlb_all properly and implement the
domain attribute, and iommu-dma and io-pgtable will do the rest for us.
The only real subtlety is documenting the barrier semantics we're
introducing between io-pgtable and the drivers for non-strict flushes.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(backported from commit 44f6876a00e83df5fd28681502b19b0f51e4a3c6)
[ dannf: trivial context fix in arm_smmu_ops struct ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

iommu-non-strict-disco 2018-12-13 20:59:58 UTC 2018-12-13
iommu/arm-smmu: Support non-strict mode

Author: Robin Murphy
Author Date: 2018-09-20 16:10:27 UTC

iommu/arm-smmu: Support non-strict mode

BugLink: https://bugs.launchpad.net/bugs/1806488

All we need is to wire up .flush_iotlb_all properly and implement the
domain attribute, and iommu-dma and io-pgtable will do the rest for us.
The only real subtlety is documenting the barrier semantics we're
introducing between io-pgtable and the drivers for non-strict flushes.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 44f6876a00e83df5fd28681502b19b0f51e4a3c6)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

d05-kdump-d-v2 2018-12-05 15:51:52 UTC 2018-12-05
efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

Author: Ard Biesheuvel
Author Date: 2018-11-23 21:51:32 UTC

efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

BugLink: https://bugs.launchpad.net/bugs/1806766

Mapping the MEMRESERVE EFI configuration table from an early initcall
is too late: the GICv3 ITS code that creates persistent reservations
for the boot CPU's LPI tables is invoked from init_IRQ(), which runs
much earlier than the handling of the initcalls. This results in a
WARN() splat because the LPI tables cannot be reserved persistently,
which will result in silent memory corruption after a kexec reboot.

So instead, invoke the initialization performed by the initcall from
efi_mem_reserve_persistent() itself as well, but keep the initcall so
that the init is guaranteed to have been called before SMP boot.

Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Jan Glauber <jglauber@cavium.com>
Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Fixes: 63eb322d89c8 ("efi: Permit calling efi_mem_reserve_persistent() ...")
Link: http://lkml.kernel.org/r/20181123215132.7951-2-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 976b489120cdab2b1b3a41ffa14661db43d58190)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

d05-kdump-c 2018-12-05 15:49:32 UTC 2018-12-05
efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

Author: Ard Biesheuvel
Author Date: 2018-11-23 21:51:32 UTC

efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

BugLink: https://bugs.launchpad.net/bugs/1806766

Mapping the MEMRESERVE EFI configuration table from an early initcall
is too late: the GICv3 ITS code that creates persistent reservations
for the boot CPU's LPI tables is invoked from init_IRQ(), which runs
much earlier than the handling of the initcalls. This results in a
WARN() splat because the LPI tables cannot be reserved persistently,
which will result in silent memory corruption after a kexec reboot.

So instead, invoke the initialization performed by the initcall from
efi_mem_reserve_persistent() itself as well, but keep the initcall so
that the init is guaranteed to have been called before SMP boot.

Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Jan Glauber <jglauber@cavium.com>
Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Fixes: 63eb322d89c8 ("efi: Permit calling efi_mem_reserve_persistent() ...")
Link: http://lkml.kernel.org/r/20181123215132.7951-2-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 976b489120cdab2b1b3a41ffa14661db43d58190)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

d05-kdump-d 2018-12-04 21:35:50 UTC 2018-12-04
efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

Author: Ard Biesheuvel
Author Date: 2018-11-23 21:51:32 UTC

efi: Prevent GICv3 WARN() by mapping the memreserve table before first use

BugLink: https://bugs.launchpad.net/bugs/1806766

Mapping the MEMRESERVE EFI configuration table from an early initcall
is too late: the GICv3 ITS code that creates persistent reservations
for the boot CPU's LPI tables is invoked from init_IRQ(), which runs
much earlier than the handling of the initcalls. This results in a
WARN() splat because the LPI tables cannot be reserved persistently,
which will result in silent memory corruption after a kexec reboot.

So instead, invoke the initialization performed by the initcall from
efi_mem_reserve_persistent() itself as well, but keep the initcall so
that the init is guaranteed to have been called before SMP boot.

Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Jan Glauber <jglauber@cavium.com>
Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Fixes: 63eb322d89c8 ("efi: Permit calling efi_mem_reserve_persistent() ...")
Link: http://lkml.kernel.org/r/20181123215132.7951-2-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 976b489120cdab2b1b3a41ffa14661db43d58190)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

xenial-arm64-acpi-pci 2018-10-29 18:03:40 UTC 2018-10-29
ARM64: PCI: Support ACPI-based PCI host controller

Author: Tomasz Nowicki
Author Date: 2016-06-10 19:55:19 UTC

ARM64: PCI: Support ACPI-based PCI host controller

BugLink: https://bugs.launchpad.net/bugs/1797092

Implement pci_acpi_scan_root() and other arch-specific calls so ARM64 can
use ACPI to setup and enumerate PCI buses.

Use memory-mapped configuration space information from either the ACPI
_CBA method or the MCFG table and the ECAM library and generic ECAM config
accessor ops.

Implement acpi_pci_bus_find_domain_nr() to retrieve the domain number from
the acpi_pci_root structure.

Implement pcibios_add_bus() and pcibios_remove_bus() to call
acpi_pci_add_bus() and acpi_pci_remove_bus() for ACPI slot management and
other configuration.

Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
(backported from commit 0cb0786bac159ee4c983abab51093ef623849afa)
[ dannf: Kconfig offset fixup ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisilicon-fixes 2018-09-24 21:06:48 UTC 2018-09-24
net: hns3: Add vlan filter setting by ethtool command -K

Author: Peng Li
Author Date: 2018-08-14 16:13:19 UTC

net: hns3: Add vlan filter setting by ethtool command -K

BugLink: https://bugs.launchpad.net/bugs/1793394

Revision(0x20) HW does not support enabling or disabling individual
netdev's HW_VLAN_CTAG_FILTER feature, and Revision(0x21) supports
enabling or disabling individual netdev's HW_VLAN_CTAG_FILTER
feature.

Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 3e85af6a6812d2d4778c3b19f17384c2a9f73200)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-upstream-unstable 2018-08-28 22:02:36 UTC 2018-08-28
net: hns3: Fix for phy link issue when using marvell phy driver

Author: Jian Shen
Author Date: 2018-08-14 16:13:15 UTC

net: hns3: Fix for phy link issue when using marvell phy driver

BugLink: https://bugs.launchpad.net/bugs/1787477

For marvell phy m88e1510, bit SUPPORTED_FIBRE of phydev->supported
is default on. Both phy_resume() and phy_suspend() will check the
SUPPORTED_FIBRE bit and write register of fibre page.

Currently in hns3 driver, the SUPPORTED_FIBRE bit will be cleared
after phy_connect_direct() finished. Because phy_resume() is called
in phy_connect_direct(), and phy_suspend() is called when disconnect
phy device, so the operation for fibre page register is not symmetrical.
It will cause phy link issue when reload hns3 driver.

This patch fixes it by disable the SUPPORTED_FIBRE before connecting
phy.

Fixes: 256727da7395 ("net: hns3: Add MDIO support to HNS3 Ethernet driver for hip08 SoC")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 60081dcc4fce385ade26d3145b2479789df0b7e5)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-upstream-cosmic 2018-08-17 17:14:00 UTC 2018-08-17
UBUNTU: SAUCE: {topost} net: hns3: separate roce from nic when resetting

Author: Huazhong Tan
Author Date: 2018-05-07 06:42:55 UTC

UBUNTU: SAUCE: {topost} net: hns3: separate roce from nic when resetting

BugLink: https://bugs.launchpad.net/bugs/1787477

While doing resetting, roce should do its uninitailization part
before nic's, and do its initialization part after nic's.

Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-upstream-bionic 2018-08-17 14:58:11 UTC 2018-08-17
UBUNTU: SAUCE: {topost} net: hns3: separate roce from nic when resetting

Author: Huazhong Tan
Author Date: 2018-05-07 06:42:55 UTC

UBUNTU: SAUCE: {topost} net: hns3: separate roce from nic when resetting

BugLink: https://bugs.launchpad.net/bugs/1787477

While doing resetting, roce should do its uninitailization part
before nic's, and do its initialization part after nic's.

Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi_sas-bionic 2018-06-19 23:13:46 UTC 2018-06-19
scsi: hisi_sas: Update a couple of register settings for v3 hw

Author: John Garry
Author Date: 2018-05-31 12:50:50 UTC

scsi: hisi_sas: Update a couple of register settings for v3 hw

BugLink: https://bugs.launchpad.net/bugs/1777736

Update CFG_1US_TIMER_TRSH and CON_CFG_DRIVER settings.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 7bfa2e5f7b677688f609cf39274eb5bf1174af16 scsi)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

netsec-unstable 2018-06-08 16:28:38 UTC 2018-06-08
net: socionext: reset hardware in ndo_stop

Author: Masahisa KOJIMA
Author Date: 2018-04-16 07:39:59 UTC

net: socionext: reset hardware in ndo_stop

When the interface is down, head/tail of the descriptor
ring address is set to 0 in netsec_netdev_stop().
But netsec hardware still keeps the previous descriptor
ring address, so there is inconsistency between driver
and hardware after interface is up at a later time.
To address this inconsistency, add netsec_reset_hardware()
when the interface is down.

In addition, to minimize the reset process,
add flag to decide whether driver loads the netsec microcode.
Even if driver resets the netsec hardware, netsec microcode
keeps resident on RAM, so it is ok we only load the microcode
at initialization.

This patch is critical for installation over network.

Signed-off-by: Masahisa KOJIMA <masahisa.kojima@linaro.org>
Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver")
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 9a00b697ce31e38c670a3042cf9f1e9cf28dabb5)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

netsec-bionic 2018-06-08 16:08:26 UTC 2018-06-08
net: netsec: reduce DMA mask to 40 bits

Author: Ard Biesheuvel
Author Date: 2018-05-25 12:50:37 UTC

net: netsec: reduce DMA mask to 40 bits

The netsec network controller IP can drive 64 address bits for DMA, and
the DMA mask is set accordingly in the driver. However, the SynQuacer
SoC, which is the only silicon incorporating this IP at the moment,
integrates this IP in a manner that leaves address bits [63:40]
unconnected.

Up until now, this has not resulted in any problems, given that the DDR
controller doesn't decode those bits to begin with. However, recent
firmware updates for platforms incorporating this SoC allow the IOMMU
to be enabled, which does decode address bits [47:40], and allocates
top down from the IOVA space, producing DMA addresses that have bits
set that have been left unconnected.

Both the DT and ACPI (IORT) descriptions of the platform take this into
account, and only describe a DMA address space of 40 bits (using either
dma-ranges DT properties, or DMA address limits in IORT named component
nodes). However, even though our IOMMU and bus layers may take such
limitations into account by setting a narrower DMA mask when creating
the platform device, the netsec probe() entrypoint follows the common
practice of setting the DMA mask uncondionally, according to the
capabilities of the IP block itself rather than to its integration into
the chip.

It is currently unclear what the correct fix is here. We could hack around
it by only setting the DMA mask if it deviates from its default value of
DMA_BIT_MASK(32). However, this makes it impossible for the bus layer to
use DMA_BIT_MASK(32) as the bus limit, and so it appears that a more
comprehensive approach is required to take DMA limits imposed by the
SoC as a whole into account.

In the mean time, let's limit the DMA mask to 40 bits. Given that there
is currently only one SoC that incorporates this IP, this is a reasonable
approach that can be backported to -stable and buys us some time to come
up with a proper fix going forward.

Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver")
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 312564269535892cc082bc80592150cd1f5e8ec3)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-roce-unstable 2018-06-07 17:48:16 UTC 2018-06-07
RDMA/hns: Implement the disassociate_ucontext API

Author: Wei Hu(Xavier)
Author Date: 2018-05-28 11:39:27 UTC

RDMA/hns: Implement the disassociate_ucontext API

BugLink: https://bugs.launchpad.net/bugs/1770974

This patch implemented the IB core disassociate_ucontext API.

Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
(cherry picked from commit fedc3abe7bd2dcc4c80bcf3cff8708a3908d8219 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-roce-bionic 2018-06-07 17:28:50 UTC 2018-06-07
RDMA/hns: Implement the disassociate_ucontext API

Author: Wei Hu(Xavier)
Author Date: 2018-05-28 11:39:27 UTC

RDMA/hns: Implement the disassociate_ucontext API

BugLink: https://bugs.launchpad.net/bugs/1770974

This patch implemented the IB core disassociate_ucontext API.

Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
(cherry picked from commit fedc3abe7bd2dcc4c80bcf3cff8708a3908d8219 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-updates-v3-unstable 2018-06-05 22:49:30 UTC 2018-06-05
UBUNTU: SAUCE: net: hns3: Optimize PF CMDQ interrupt switching process

Author: Xi Wang
Author Date: 2018-06-05 22:21:04 UTC

UBUNTU: SAUCE: net: hns3: Optimize PF CMDQ interrupt switching process

BugLink: https://bugs.launchpad.net/bugs/1768670

When the PF frequently switches the CMDQ interrupt, if the CMDQ_SRC is
not cleared before the hardware interrupt is generated, the new interrupt
will not be reported.

This patch optimizes this problem by clearing CMDQ_SRC and RESET_STS
before enabling interrupt and syncing pending IRQ handlers after disabling
interrupt.

Fixes: 466b0c00391b ("net: hns3: Add support for misc interrupt")
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-updates-v3 2018-06-05 22:21:07 UTC 2018-06-05
UBUNTU: SAUCE: net: hns3: Optimize PF CMDQ interrupt switching process

Author: Xi Wang
Author Date: 2018-06-05 22:21:04 UTC

UBUNTU: SAUCE: net: hns3: Optimize PF CMDQ interrupt switching process

BugLink: https://bugs.launchpad.net/bugs/1768670

When the PF frequently switches the CMDQ interrupt, if the CMDQ_SRC is
not cleared before the hardware interrupt is generated, the new interrupt
will not be reported.

This patch optimizes this problem by clearing CMDQ_SRC and RESET_STS
before enabling interrupt and syncing pending IRQ handlers after disabling
interrupt.

Fixes: 466b0c00391b ("net: hns3: Add support for misc interrupt")
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi_sas-updates-unstable 2018-05-31 21:40:42 UTC 2018-05-31
scsi: hisi_sas: Mark PHY as in reset for nexus reset

Author: Xiang Chen
Author Date: 2018-05-21 10:09:25 UTC

scsi: hisi_sas: Mark PHY as in reset for nexus reset

BugLink: https://bugs.launchpad.net/bugs/1774466

When issuing a nexus reset for directly attached device, we want to ignore
the PHY down events so libsas will not deform and reform the port.

In the case that the attached SAS changes for the reset, libsas will deform
and form a port.

For scenario that the PHY does not come up after a timeout period, then
report the PHY down to libsas.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 3e1fb1b8abf0c862a7f5d39cb3354a1fd5e9f96a linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi_sas-updates-bionic 2018-05-31 21:18:44 UTC 2018-05-31
scsi: hisi_sas: Mark PHY as in reset for nexus reset

Author: Xiang Chen
Author Date: 2018-05-21 10:09:25 UTC

scsi: hisi_sas: Mark PHY as in reset for nexus reset

BugLink: https://bugs.launchpad.net/bugs/1774466

When issuing a nexus reset for directly attached device, we want to ignore
the PHY down events so libsas will not deform and reform the port.

In the case that the attached SAS changes for the reset, libsas will deform
and form a port.

For scenario that the PHY does not come up after a timeout period, then
report the PHY down to libsas.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 3e1fb1b8abf0c862a7f5d39cb3354a1fd5e9f96a linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

pptt-bionic 2018-05-30 16:40:01 UTC 2018-05-30
arm64: topology: divorce MC scheduling domain from core_siblings

Author: Jeremy Linton
Author Date: 2018-05-11 23:58:07 UTC

arm64: topology: divorce MC scheduling domain from core_siblings

BugLink: https://bugs.launchpad.net/bugs/1770231

Now that we have an accurate view of the physical topology
we need to represent it correctly to the scheduler. Generally MC
should equal the LLC in the system, but there are a number of
special cases that need to be dealt with.

In the case of NUMA in socket, we need to assure that the sched
domain we build for the MC layer isn't larger than the DIE above it.
Similarly for LLC's that might exist in cross socket interconnect or
directory hardware we need to assure that MC is shrunk to the socket
or NUMA node.

This patch builds a sibling mask for the LLC, and then picks the
smallest of LLC, socket siblings, or NUMA node siblings, which
gives us the behavior described above. This is ever so slightly
different than the similar alternative where we look for a cache
layer less than or equal to the socket/NUMA siblings.

The logic to pick the MC layer affects all arm64 machines, but
only changes the behavior for DT/MPIDR systems if the NUMA domain
is smaller than the core siblings (generally set to the cluster).
Potentially this fixes a possible bug in DT systems, but really
it only affects ACPI systems where the core siblings is correctly
set to the socket siblings. Thus all currently available ACPI
systems should have MC equal to LLC, including the NUMA in socket
machines where the LLC is partitioned between the NUMA nodes.

Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Morten Rasmussen <morten.rasmussen@arm.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 37c3ec2d810f87eac73822f76b30391a83bded19 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

pptt+hns3-updates 2018-05-29 19:44:03 UTC 2018-05-29
net: hns3: Fix for CMDQ and Misc. interrupt init order problem

Author: Yunsheng Lin
Author Date: 2018-05-19 15:53:23 UTC

net: hns3: Fix for CMDQ and Misc. interrupt init order problem

BugLink: https://bugs.launchpad.net/bugs/1768670

When vf module is loading, the cmd queue initialization should
happen before misc interrupt initialization, otherwise the misc
interrupt handle will cause using uninitialized cmd queue problem.
There is also the same issue when vf module is unloading.

This patch fixes it by adjusting the location of some function.

Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eddf04626d1d6d0bcd01ac6a287e49f5ddb90a26 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

pptt-unstable 2018-05-25 20:54:24 UTC 2018-05-25
arm64: topology: divorce MC scheduling domain from core_siblings

Author: Jeremy Linton
Author Date: 2018-05-11 23:58:07 UTC

arm64: topology: divorce MC scheduling domain from core_siblings

BugLink: https://bugs.launchpad.net/bugs/1770231

Now that we have an accurate view of the physical topology
we need to represent it correctly to the scheduler. Generally MC
should equal the LLC in the system, but there are a number of
special cases that need to be dealt with.

In the case of NUMA in socket, we need to assure that the sched
domain we build for the MC layer isn't larger than the DIE above it.
Similarly for LLC's that might exist in cross socket interconnect or
directory hardware we need to assure that MC is shrunk to the socket
or NUMA node.

This patch builds a sibling mask for the LLC, and then picks the
smallest of LLC, socket siblings, or NUMA node siblings, which
gives us the behavior described above. This is ever so slightly
different than the similar alternative where we look for a cache
layer less than or equal to the socket/NUMA siblings.

The logic to pick the MC layer affects all arm64 machines, but
only changes the behavior for DT/MPIDR systems if the NUMA domain
is smaller than the core siblings (generally set to the cluster).
Potentially this fixes a possible bug in DT systems, but really
it only affects ACPI systems where the core siblings is correctly
set to the socket siblings. Thus all currently available ACPI
systems should have MC equal to LLC, including the NUMA in socket
machines where the LLC is partitioned between the NUMA nodes.

Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Morten Rasmussen <morten.rasmussen@arm.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 37c3ec2d810f87eac73822f76b30391a83bded19 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-updates-unstable 2018-05-25 20:22:16 UTC 2018-05-25
net: hns3: Fix for CMDQ and Misc. interrupt init order problem

Author: Yunsheng Lin
Author Date: 2018-05-19 15:53:23 UTC

net: hns3: Fix for CMDQ and Misc. interrupt init order problem

BugLink: https://bugs.launchpad.net/bugs/1768670

When vf module is loading, the cmd queue initialization should
happen before misc interrupt initialization, otherwise the misc
interrupt handle will cause using uninitialized cmd queue problem.
There is also the same issue when vf module is unloading.

This patch fixes it by adjusting the location of some function.

Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eddf04626d1d6d0bcd01ac6a287e49f5ddb90a26 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-updates-v2 2018-05-25 19:53:25 UTC 2018-05-25
net: hns3: Fix for CMDQ and Misc. interrupt init order problem

Author: Yunsheng Lin
Author Date: 2018-05-19 15:53:23 UTC

net: hns3: Fix for CMDQ and Misc. interrupt init order problem

BugLink: https://bugs.launchpad.net/bugs/1768670

When vf module is loading, the cmd queue initialization should
happen before misc interrupt initialization, otherwise the misc
interrupt handle will cause using uninitialized cmd queue problem.
There is also the same issue when vf module is unloading.

This patch fixes it by adjusting the location of some function.

Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eddf04626d1d6d0bcd01ac6a287e49f5ddb90a26 linux-next)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

pearl2-4.15.0-21.22 2018-05-14 17:18:13 UTC 2018-05-14
UBUNTU: Ubuntu-4.15.0-21.22+pearl2.3

Author: dann frazier
Author Date: 2018-05-14 15:57:34 UTC

UBUNTU: Ubuntu-4.15.0-21.22+pearl2.3

Signed-off-by: dann frazier <dann.frazier@canonical.com>

pearl2-4.15.0-20.21 2018-05-08 00:47:39 UTC 2018-05-08
ACPI: APEI: call into AER handling regardless of severity

Author: Tyler Baicar
Author Date: 2017-11-28 21:48:09 UTC

ACPI: APEI: call into AER handling regardless of severity

BugLink: https://bugs.launchpad.net/bugs/1769730

Currently the GHES code only calls into the AER driver for
recoverable type errors. This is incorrect because errors of
other severities do not get logged by the AER driver and do not
get exposed to user space via the AER trace event. So, call
into the AER driver for PCIe errors regardless of the severity

Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit 9852ce9ae213d39a98f161db84b90b047fbdc436)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-updates 2018-05-04 01:48:52 UTC 2018-05-04
scsi: hisi_sas: Code cleanup and minor bug fixes

Author: Xiang Chen
Author Date: 2018-03-07 12:25:12 UTC

scsi: hisi_sas: Code cleanup and minor bug fixes

BugLink: https://bugs.launchpad.net/bugs/1768974

The patch does some code cleanup and fixes some small bugs:

- Correct return status of phy_up_v3_hw() and phy_bcast_v3_hw()
- Add static for function phy_get_max_linkrate_v3_hw()
- Change exception return status when no reset method
- Change magic value to ts->stat in slot_complete_vx_hw()
- Remove unnecessary check for dev_is_sata()
- Fix some issues of alignment and indents (Authored by Xiaofei Tan in
  another patch, but added here to be practical)

Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit edafeef4f28ded4ea9ba7876cc35861d43c7b2b1)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns3-updates 2018-05-03 00:42:57 UTC 2018-05-03
net: hns3: fix length overflow when CONFIG_ARM64_64K_PAGES

Author: Tan Xiaojun
Author Date: 2018-04-04 09:40:48 UTC

net: hns3: fix length overflow when CONFIG_ARM64_64K_PAGES

BugLink: https://bugs.launchpad.net/bugs/1768670

When enable the config item "CONFIG_ARM64_64K_PAGES", the size of PAGE_SIZE
is 65536(64K). But the type of length is u16, it will overflow. So change it
to u32.

Signed-off-by: Tan Xiaojun <tanxiaojun@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 48d154e7f56ed03c61a02436e86d25e6b37c0256)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

upstream-lpc-bionic-v2 2018-04-10 15:32:35 UTC 2018-04-10
MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver

Author: John Garry
Author Date: 2018-03-14 18:15:59 UTC

MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver

BugLink: https://bugs.launchpad.net/bugs/1762758

Add John Garry as maintainer for drivers/bus/hisi_lpc.c, the HiSilicon LPC
driver.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 6183d9b3ce7979eda940e594a5c342171a5da998)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

rdma-hns-bionic 2018-04-10 15:26:03 UTC 2018-04-10
RDMA/hns: ensure for-loop actually iterates and free's buffers

Author: Colin Ian King
Author Date: 2018-03-26 15:10:18 UTC

RDMA/hns: ensure for-loop actually iterates and free's buffers

BugLink: https://bugs.launchpad.net/bugs/1762757

The current for-loop zeros variable i and only loops once, hence
not all the buffers are free'd. Fix this by setting i correctly.

Detected by CoverityScan, CID#1463415 ("Operands don't affect result")

Fixes: a5073d6054f7 ("RDMA/hns: Add eq support of hip08")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Yixian Liu <liuyixian@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
(cherry picked from commit 38759d6175d338fbf9282c8ea2b51f3b7ab9bc98)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

upstream-lpc-bionic 2018-04-09 22:06:33 UTC 2018-04-09
MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver

Author: John Garry
Author Date: 2018-03-14 18:15:59 UTC

MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver

BugLink: https://bugs.launchpad.net/bugs/1677319

Add John Garry as maintainer for drivers/bus/hisi_lpc.c, the HiSilicon LPC
driver.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 6183d9b3ce7979eda940e594a5c342171a5da998)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hclge-autoload 2018-04-05 21:53:37 UTC 2018-04-05
UBUNTU: d-i: Add hns3 drivers to nic-modules

Author: dann frazier
Author Date: 2018-04-05 21:28:30 UTC

UBUNTU: d-i: Add hns3 drivers to nic-modules

BugLink: https://bugs.launchpad.net/bugs/1761610

Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1760712-bionic 2018-04-03 18:18:32 UTC 2018-04-03
perf vendor events arm64: Enable JSON events for ThunderX2 B0

Author: Ganapatrao Kulkarni
Author Date: 2018-03-07 11:08:03 UTC

perf vendor events arm64: Enable JSON events for ThunderX2 B0

BugLink: https://bugs.launchpad.net/bugs/1760712

There is MIDR change on ThunderX2 B0, adding an entry to mapfile to
enable JSON events for B0.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ganapatrao Kulkarni <gpkulkarni@gklkml16.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <robert.richter@cavium.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20180307110803.32418-1-ganapatrao.kulkarni@cavium.com
[ Fixup wrt recent patchset by John Garry ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
(cherry picked from commit a8685f088819d21cd5aea5de4c184de427c3625d)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

xenial-spcr-annotated 2018-02-28 17:17:16 UTC 2018-02-28
serial: pl011: add console matching function

Author: Aleksey Makarov
Author Date: 2016-10-04 07:15:32 UTC

serial: pl011: add console matching function

BugLink: https://bugs.launchpad.net/bugs/1744754

This patch adds function pl011_console_match() that implements
method match of struct console. It allows to match consoles against
data specified in a string, for example taken from command line or
compiled by ACPI SPCR table handler.

This patch was merged to tty-next but then reverted because of
conflict with

commit 46e36683f433 ("serial: earlycon: Extend earlycon command line option to support 64-bit addresses")

Now it is fixed.

Signed-off-by: Aleksey Makarov <aleksey.makarov@linaro.org>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(backported from commit 10879ae5f12e9cab3c4e8e9504c1aaa8a033bde7)
[ dannf: undo resource_size_t conversion that didn't occur upstream until
  46e36683f433 ("serial: earlycon: Extend earlycon command line option to support 64-bit addresses") ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

libsas-bionic 2018-02-27 18:28:02 UTC 2018-02-27
scsi: libsas: notify event PORTE_BROADCAST_RCVD in sas_enable_revalidation()

Author: Jason Yan
Author Date: 2017-12-08 09:42:10 UTC

scsi: libsas: notify event PORTE_BROADCAST_RCVD in sas_enable_revalidation()

BugLink: https://bugs.launchpad.net/bugs/1752146

There are two places queuing the disco event DISCE_REVALIDATE_DOMAIN.
One is in sas_porte_broadcast_rcvd() and uses sas_chain_event() to queue
the event. The other is in sas_enable_revalidation() and uses
sas_queue_event() to queue the event. We have diffrent work queues for
event and discovery now, so the DISCE_REVALIDATE_DOMAIN event may be
processed in both event queue and discovery queue.

Now since we do synchronous event handling, we cannot do it in discovery
queue, so have to trigger a fake broadcast event to re-trigger the
revalidation from event queue.

Signed-off-by: Jason Yan <yanaijie@huawei.com>
CC: John Garry <john.garry@huawei.com>
CC: Johannes Thumshirn <jthumshirn@suse.de>
CC: Ewan Milne <emilne@redhat.com>
CC: Christoph Hellwig <hch@lst.de>
CC: Tomas Henzl <thenzl@redhat.com>
CC: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit 1689c9367bfaf4b5ff3973f26f5acbff16b63bfb)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lpc-bionic-v14 2018-02-21 00:25:32 UTC 2018-02-21
UBUNTU: SAUCE: MAINTAINERS: Add maintainer for HiSilicon LPC driver

Author: John Garry
Author Date: 2018-02-19 17:48:40 UTC

UBUNTU: SAUCE: MAINTAINERS: Add maintainer for HiSilicon LPC driver

BugLink: https://bugs.launchpad.net/bugs/1677319

Added maintainer for drivers/bus/hisi_lpc.c

Signed-off-by: John Garry <john.garry@huawei.com>
[ v14 submittal ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

kpti-thunder-artful 2018-02-14 22:53:39 UTC 2018-02-14
arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives

Author: Will Deacon
Author Date: 2018-01-29 12:00:00 UTC

arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives

BugLink: https://bugs.launchpad.net/bugs/1749040

The identity map is mapped as both writeable and executable by the
SWAPPER_MM_MMUFLAGS and this is relied upon by the kpti code to manage
a synchronisation flag. Update the .pushsection flags to reflect the
actual mapping attributes.

Reported-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 439e70e27a51fe374806f460848066b237b0c10b)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

minacpi-x 2018-01-31 23:12:16 UTC 2018-01-31
serial: pl011: add console matching function

Author: Aleksey Makarov
Author Date: 2016-10-04 07:15:32 UTC

serial: pl011: add console matching function

BugLink: https://bugs.launchpad.net/bugs/1744754

This patch adds function pl011_console_match() that implements
method match of struct console. It allows to match consoles against
data specified in a string, for example taken from command line or
compiled by ACPI SPCR table handler.

This patch was merged to tty-next but then reverted because of
conflict with

commit 46e36683f433 ("serial: earlycon: Extend earlycon command line option to support 64-bit addresses")

Now it is fixed.

Signed-off-by: Aleksey Makarov <aleksey.makarov@linaro.org>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(backported from commit 10879ae5f12e9cab3c4e8e9504c1aaa8a033bde7)
[ dannf: undo resource_size_t conversion that didn't occur upstream until
  46e36683f433 ("serial: earlycon: Extend earlycon command line option to support 64-bit addresses") ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1739807-aa 2017-12-22 23:22:26 UTC 2017-12-22
scsi: hisi_sas: complete all tasklets prior to host reset

Author: tanxiaofei
Author Date: 2017-10-24 15:51:47 UTC

scsi: hisi_sas: complete all tasklets prior to host reset

BugLink: https://bugs.launchpad.net/bugs/1739807

The CQ event is handled in tasklet context, and it could be delayed if
the system loading is high.

It is possible to run into some problems when executing a host reset
when cq_tasklet_vx_hw() is being executed.

So, prior to host reset, execute tasklet_kill() to ensure that all CQ
tasklets are complete.

Besides, as the function hisi_sas_wait_tasklets_done() is added to do
tasklet_kill(), this patch refactors some code where tasklet_kill() is
used.

Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(backported from commit 571295f8055c0b69c9911021ae6cf1a6973cf517)
[ dannf: dropped change in hisi_sas_v3_hw.c reset handler, which didn't
  yet exit; resolved trivial merge conflict in hisi_sas.h ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1710019-z 2017-11-10 17:29:06 UTC 2017-11-10
KVM: arm/arm64: vgic-its: Fix return value for device table restore

Author: wanghaibin
Author Date: 2017-10-26 15:23:03 UTC

KVM: arm/arm64: vgic-its: Fix return value for device table restore

BugLink: https://bugs.launchpad.net/bugs/1710019

If ITT only contains invalid entries, vgic_its_restore_itt
returns 1 and this is considered as an an error in
vgic_its_restore_dte.

Also in case the device table only contains invalid entries,
the table restore fails and this is not correct.

This patch fixes those 2 issues:
- vgic_its_restore_itt now returns <= 0 values. If all
  ITEs are invalid, this is considered as successful.
- vgic_its_restore_device_tables also returns <= 0 values.

We also simplify the returned value computation in
handle_l1_dte.

Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit b92382620e33c9f1bcbcd7c169262b9bf0525871)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1721365-z 2017-11-03 18:32:56 UTC 2017-11-03
net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag

Author: Ding Tianhong
Author Date: 2017-08-18 06:21:05 UTC

net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag

BugLink: https://bugs.launchpad.net/bugs/1721365

The ixgbe driver use the compile check to determine if it can
send TLPs to Root Port with the Relaxed Ordering Attribute set,
this is too inconvenient, now the new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING
has been added to the kernel and we could check the bit4 in the PCIe
Device Control register to determine whether we should use the Relaxed
Ordering Attributes or not, so use this new way in the ixgbe driver.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
(cherry picked from commit 5e0fac63a694918870af9d6eaf716af19e7f5652)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-arch-timer-fixes-z 2017-08-29 22:57:42 UTC 2017-08-29
clocksource/drivers/arm_arch_timer: Avoid infinite recursion when ftrace is e...

Author: Ding Tianhong
Author Date: 2017-08-10 02:52:45 UTC

clocksource/drivers/arm_arch_timer: Avoid infinite recursion when ftrace is enabled

BugLink: https://bugs.launchpad.net/bugs/1713821

On platforms with an arch timer erratum workaround, it's possible for
arch_timer_reg_read_stable() to recurse into itself when certain
tracing options are enabled, leading to stack overflows and related
problems.

For example, when PREEMPT_TRACER and FUNCTION_GRAPH_TRACER are
selected, it's possible to trigger this with:

$ mount -t debugfs nodev /sys/kernel/debug/
$ echo function_graph > /sys/kernel/debug/tracing/current_tracer

The problem is that in such cases, preempt_disable() instrumentation
attempts to acquire a timestamp via trace_clock(), resulting in a call
back to arch_timer_reg_read_stable(), and hence recursion.

This patch changes arch_timer_reg_read_stable() to use
preempt_{disable,enable}_notrace(), which avoids this.

This problem is similar to the fixed by upstream commit 96b3d28bf4
("sched/clock: Prevent tracing recursion in sched_clock_cpu()").

Fixes: 6acc71ccac71 ("arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs")
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from commit adb4f11e0a8f4e29900adb2b7af28b6bbd5c1fa4)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-arch-timer-fixes-aa 2017-08-29 22:56:36 UTC 2017-08-29
clocksource/drivers/arm_arch_timer: Avoid infinite recursion when ftrace is e...

Author: Ding Tianhong
Author Date: 2017-08-10 02:52:45 UTC

clocksource/drivers/arm_arch_timer: Avoid infinite recursion when ftrace is enabled

BugLink: https://bugs.launchpad.net/bugs/1713821

On platforms with an arch timer erratum workaround, it's possible for
arch_timer_reg_read_stable() to recurse into itself when certain
tracing options are enabled, leading to stack overflows and related
problems.

For example, when PREEMPT_TRACER and FUNCTION_GRAPH_TRACER are
selected, it's possible to trigger this with:

$ mount -t debugfs nodev /sys/kernel/debug/
$ echo function_graph > /sys/kernel/debug/tracing/current_tracer

The problem is that in such cases, preempt_disable() instrumentation
attempts to acquire a timestamp via trace_clock(), resulting in a call
back to arch_timer_reg_read_stable(), and hence recursion.

This patch changes arch_timer_reg_read_stable() to use
preempt_{disable,enable}_notrace(), which avoids this.

This problem is similar to the fixed by upstream commit 96b3d28bf4
("sched/clock: Prevent tracing recursion in sched_clock_cpu()").

Fixes: 6acc71ccac71 ("arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs")
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from commit adb4f11e0a8f4e29900adb2b7af28b6bbd5c1fa4)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-perf-zesty 2017-08-04 19:38:16 UTC 2017-08-04
scsi: hisi_sas: optimise DMA slot memory

Author: tanxiaofei
Author Date: 2017-06-29 13:02:14 UTC

scsi: hisi_sas: optimise DMA slot memory

BugLink: https://bugs.launchpad.net/bugs/1708734

Currently we allocate 3 sets of DMA memories from separate pools for
each slot. This is inefficient in terms of memory usage
(buffers are less than 1 page in size, so we lose due to alignment),
and also time spent in doing 3 allocations + de-allocations per slot,
instead of 1.

To optimise, combine the 3 DMA buffers into a single buffer from a
single pool.

Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(backported from commit f557e32c0023ea0d67cdaa81b3398550dc1e4876)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-perf-artful 2017-08-04 19:37:57 UTC 2017-08-04
scsi: hisi_sas: optimise DMA slot memory

Author: tanxiaofei
Author Date: 2017-06-29 13:02:14 UTC

scsi: hisi_sas: optimise DMA slot memory

BugLink: https://bugs.launchpad.net/bugs/1708734

Currently we allocate 3 sets of DMA memories from separate pools for
each slot. This is inefficient in terms of memory usage
(buffers are less than 1 page in size, so we lose due to alignment),
and also time spent in doing 3 allocations + de-allocations per slot,
instead of 1.

To optimise, combine the 3 DMA buffers into a single buffer from a
single pool.

Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(backported from commit f557e32c0023ea0d67cdaa81b3398550dc1e4876)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas-perf-unstable 2017-08-04 19:34:53 UTC 2017-08-04
scsi: hisi_sas: optimise DMA slot memory

Author: tanxiaofei
Author Date: 2017-06-29 13:02:14 UTC

scsi: hisi_sas: optimise DMA slot memory

BugLink: https://bugs.launchpad.net/bugs/1708734

Currently we allocate 3 sets of DMA memories from separate pools for
each slot. This is inefficient in terms of memory usage
(buffers are less than 1 page in size, so we lose due to alignment),
and also time spent in doing 3 allocations + de-allocations per slot,
instead of 1.

To optimise, combine the 3 DMA buffers into a single buffer from a
single pool.

Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(backported from commit f557e32c0023ea0d67cdaa81b3398550dc1e4876)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1673564-zesty 2017-08-03 19:04:06 UTC 2017-08-03
KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

Author: Marc Zyngier
Author Date: 2017-06-09 11:49:56 UTC

KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

BugLink: https://bugs.launchpad.net/bugs/1673564

A write-to-read-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(backported picked from commit 7b1dba1f7325629427c0e5bdf014159b229d16c8)
[ dannf: Recoded sys_reg_descs[] entries to use pre-SYS_DESC() syntax and
  minor context changes. ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1673564-artful 2017-07-20 21:31:07 UTC 2017-07-20
KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

Author: Marc Zyngier
Author Date: 2017-06-09 11:49:56 UTC

KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

BugLink: https://bugs.launchpad.net/bugs/1673564

A write-to-read-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(backported picked from commit 7b1dba1f7325629427c0e5bdf014159b229d16c8)
[ dannf: Recoded sys_reg_descs[] entries to use pre-SYS_DESC() syntax and
  minor context changes. ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-led 2017-07-18 22:18:46 UTC 2017-07-18
UBUNTU: Ubuntu-4.10.0-27.30~16.04.2+hnsled.2

Author: dann frazier
Author Date: 2017-07-18 22:18:46 UTC

UBUNTU: Ubuntu-4.10.0-27.30~16.04.2+hnsled.2

Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1673564-unstable 2017-07-12 21:40:52 UTC 2017-07-12
KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

Author: Marc Zyngier
Author Date: 2017-06-09 11:49:56 UTC

KVM: arm64: Log an error if trapping a write-to-read-only GICv3 access

BugLink: https://bugs.launchpad.net/bugs/1673564

A write-to-read-only GICv3 access should UNDEF at EL1. But since
we're in complete paranoia-land with broken CPUs, let's assume the
worse and gracefully handle the case.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(cherry picked from commit 7b1dba1f7325629427c0e5bdf014159b229d16c8)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1702749 2017-07-06 19:53:23 UTC 2017-07-06
arm64: mm: select CONFIG_ARCH_PROC_KCORE_TEXT

Author: Ard Biesheuvel
Author Date: 2017-06-14 10:43:55 UTC

arm64: mm: select CONFIG_ARCH_PROC_KCORE_TEXT

BugLink: https://bugs.launchpad.net/bugs/1702749

To avoid issues with the /proc/kcore code getting confused about the
kernels block mappings in the VMALLOC region, enable the existing
facility that describes the [_text, _end) interval as a separate
KCORE_TEXT region, which supersedes the KCORE_VMALLOC region that
it intersects with on arm64.

Reported-by: Tan Xiaojun <tanxiaojun@huawei.com>
Tested-by: Tan Xiaojun <tanxiaojun@huawei.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Laura Abbott <labbott@redhat.com>
Reviewed-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 8f36094802e4e6de180b36bcac4cfd9d319e1b64)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-kdump-zesty 2017-06-20 23:32:01 UTC 2017-06-20
efi/libstub/arm*: Set default address and size cells values for an empty dtb

Author: Sameer Goel
Author Date: 2017-04-03 02:26:33 UTC

efi/libstub/arm*: Set default address and size cells values for an empty dtb

BugLink: https://bugs.launchpad.net/bugs/1694859

In cases where a device tree is not provided (ie ACPI based system), an
empty fdt is generated by efistub. #address-cells and #size-cells are not
set in the empty fdt, so they default to 1 (4 byte wide). This can be an
issue on 64-bit systems where values representing addresses, etc may be
8 bytes wide as the default value does not align with the general
requirements for an empty DTB, and is fragile when passed to other agents
as extra care is required to read the entire width of a value.

This issue is observed on Qualcomm Technologies QDF24XX platforms when
kexec-tools inserts 64-bit addresses into the "linux,elfcorehdr" and
"linux,usable-memory-range" properties of the fdt. When the values are
later consumed, they are truncated to 32-bit.

Setting #address-cells and #size-cells to 2 at creation of the empty fdt
resolves the observed issue, and makes the fdt less fragile.

Signed-off-by: Sameer Goel <sgoel@codeaurora.org>
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit ae8a442dfdc4fc3197c8aa09bb179345b2c1f49e)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-kdump-artful 2017-06-20 21:31:55 UTC 2017-06-20
efi/libstub/arm*: Set default address and size cells values for an empty dtb

Author: Sameer Goel
Author Date: 2017-04-03 02:26:33 UTC

efi/libstub/arm*: Set default address and size cells values for an empty dtb

BugLink: https://bugs.launchpad.net/bugs/1694859

In cases where a device tree is not provided (ie ACPI based system), an
empty fdt is generated by efistub. #address-cells and #size-cells are not
set in the empty fdt, so they default to 1 (4 byte wide). This can be an
issue on 64-bit systems where values representing addresses, etc may be
8 bytes wide as the default value does not align with the general
requirements for an empty DTB, and is fragile when passed to other agents
as extra care is required to read the entire width of a value.

This issue is observed on Qualcomm Technologies QDF24XX platforms when
kexec-tools inserts 64-bit addresses into the "linux,elfcorehdr" and
"linux,usable-memory-range" properties of the fdt. When the values are
later consumed, they are truncated to 32-bit.

Setting #address-cells and #size-cells to 2 at creation of the empty fdt
resolves the observed issue, and makes the fdt less fragile.

Signed-off-by: Sameer Goel <sgoel@codeaurora.org>
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit ae8a442dfdc4fc3197c8aa09bb179345b2c1f49e)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hns-update 2017-06-13 02:19:21 UTC 2017-06-13
net: hns: fix ethtool_get_strings overflow in hns driver

Author: Timmy
Author Date: 2017-05-02 02:46:52 UTC

net: hns: fix ethtool_get_strings overflow in hns driver

BugLink: https://bugs.launchpad.net/bugs/1696031

hns_get_sset_count() returns HNS_NET_STATS_CNT and the data space allocated
is not enough for ethtool_get_strings(), which will cause random memory
corruption.

When SLAB and DEBUG_SLAB are both enabled, memory corruptions like the
the following can be observed without this patch:
[ 43.115200] Slab corruption (Not tainted): Acpi-ParseExt start=ffff801fb0b69030, len=80
[ 43.115206] Redzone: 0x9f911029d006462/0x5f78745f31657070.
[ 43.115208] Last user: [<5f7272655f746b70>](0x5f7272655f746b70)
[ 43.115214] 010: 70 70 65 31 5f 74 78 5f 70 6b 74 00 6b 6b 6b 6b ppe1_tx_pkt.kkkk
[ 43.115217] 030: 70 70 65 31 5f 74 78 5f 70 6b 74 5f 6f 6b 00 6b ppe1_tx_pkt_ok.k
[ 43.115218] Next obj: start=ffff801fb0b69098, len=80
[ 43.115220] Redzone: 0x706d655f6f666966/0x9f911029d74e35b.
[ 43.115229] Last user: [<ffff0000084b11b0>](acpi_os_release_object+0x28/0x38)
[ 43.115231] 000: 74 79 00 6b 6b 6b 6b 6b 70 70 65 31 5f 74 78 5f ty.kkkkkppe1_tx_
[ 43.115232] 010: 70 6b 74 5f 65 72 72 5f 63 73 75 6d 5f 66 61 69 pkt_err_csum_fai

Signed-off-by: Timmy Li <lixiaoping3@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 412b65d15a7f8a93794653968308fc100f2aa87c)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

hisi-sas 2017-06-05 21:27:00 UTC 2017-06-05
scsi: hisi_sas: controller reset for multi-bits ECC and AXI fatal errors

Author: Xiang Chen
Author Date: 2017-04-10 13:22:01 UTC

scsi: hisi_sas: controller reset for multi-bits ECC and AXI fatal errors

BugLink: https://bugs.launchpad.net/bugs/1695999

For 1 bit ECC errors, those errors can be recovered by hw. But for
multi-bits ECC and AXI errors, there are something wrong with whole
module or system, so try reset the controller to recover those errors
instead of calling panic().

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
(cherry picked from commit e281f42f41db2820b079543fffb64c50b903215b)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

4.10.0-22.24+arm64-kdump 2017-05-31 20:33:21 UTC 2017-05-31
UBUNTU: Ubuntu-4.10.0-22.24+arm64kdump.1

Author: dann frazier
Author Date: 2017-05-31 20:33:21 UTC

UBUNTU: Ubuntu-4.10.0-22.24+arm64kdump.1

Signed-off-by: dann frazier <dann.frazier@canonical.com>

mbigen-v2 2017-05-31 14:33:44 UTC 2017-05-31
irqchip/mbigen: Fix the clear register offset calculation

Author: MaJun
Author Date: 2017-05-12 03:55:28 UTC

irqchip/mbigen: Fix the clear register offset calculation

BugLink: https://bugs.launchpad.net/bugs/1692783

The register array offset for clearing an interrupt is calculated by:

    offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / 32;

This is wrong because the clear register array includes the reserved
interrupts. So the clear operation ends up in the wrong register.

This went unnoticed so far, because the hardware clears the real bit
through a timeout mechanism when the hardware is configured in debug
mode. That debug mode was enabled on early generations of the hardware, so
the problem was papered over.

On newer hardware with updated firmware the debug mode was disabled, so the
bits did not get cleared which causes the system to malfunction.

Remove the subtraction of RESERVED_IRQ_PER_MBIGEN_CHIP, so the correct
register is accessed.

[ tglx: Rewrote changelog ]

Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operation functions")
Signed-off-by: MaJun <majun258@huawei.com>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: linuxarm@huawei.com
Cc: Wei Yongjun <weiyongjun1@huawei.com>
Link: http://lkml.kernel.org/r/1494561328-39514-4-git-send-email-guohanjun@huawei.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 9459a04b6a5a09967eec94a1b66f0a74312819d9)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

mbigen 2017-05-23 20:15:16 UTC 2017-05-23
irqchip/mbigen: Fix the clear register offset calculation

Author: MaJun
Author Date: 2017-05-12 03:55:28 UTC

irqchip/mbigen: Fix the clear register offset calculation

BugLink: https://bugs.launchpad.net/bugs/1692783

The register array offset for clearing an interrupt is calculated by:

    offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / 32;

This is wrong because the clear register array includes the reserved
interrupts. So the clear operation ends up in the wrong register.

This went unnoticed so far, because the hardware clears the real bit
through a timeout mechanism when the hardware is configured in debug
mode. That debug mode was enabled on early generations of the hardware, so
the problem was papered over.

On newer hardware with updated firmware the debug mode was disabled, so the
bits did not get cleared which causes the system to malfunction.

Remove the subtraction of RESERVED_IRQ_PER_MBIGEN_CHIP, so the correct
register is accessed.

[ tglx: Rewrote changelog ]

Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operation functions")
Signed-off-by: MaJun <majun258@huawei.com>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: linuxarm@huawei.com
Cc: Wei Yongjun <weiyongjun1@huawei.com>
Link: http://lkml.kernel.org/r/1494561328-39514-4-git-send-email-guohanjun@huawei.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 9459a04b6a5a09967eec94a1b66f0a74312819d9)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

thunderx-ipmi-x 2017-05-19 15:17:07 UTC 2017-05-19
i2c: thunderx: Enable HWMON class probing

Author: Jan Glauber
Author Date: 2017-05-08 14:08:52 UTC

i2c: thunderx: Enable HWMON class probing

BugLink: https://bugs.launchpad.net/bugs/1688132

Set I2C_CLASS_HWMON to enable automatic probing of BMC devices
by the ipmi-ssif driver.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 889ef45cd4b64cc4fd6dbebecddb8ea4df8cc1e7)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

thunderx-ipmi-y 2017-05-19 15:13:23 UTC 2017-05-19
i2c: thunderx: Enable HWMON class probing

Author: Jan Glauber
Author Date: 2017-05-08 14:08:52 UTC

i2c: thunderx: Enable HWMON class probing

BugLink: https://bugs.launchpad.net/bugs/1688132

Set I2C_CLASS_HWMON to enable automatic probing of BMC devices
by the ipmi-ssif driver.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 889ef45cd4b64cc4fd6dbebecddb8ea4df8cc1e7)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-acpi-pmu 2017-05-10 16:52:59 UTC 2017-05-10
perf: qcom: Add L3 cache PMU driver

Author: Agustin Vega-Frias
Author Date: 2017-03-31 18:13:43 UTC

perf: qcom: Add L3 cache PMU driver

BugLink: https://bugs.launchpad.net/bugs/1689856

This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.

The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each individual PMU is provided even though all CPUs share all
the slices. User space needs to aggregate to individual counts to provide
a global picture.

The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
   perf stat -a -e l3cache_0_0/read-miss/
   perf stat -a -e l3cache_0_0/event=0x21/

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
[will: fixed sparse issues]
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 3071f13d75f627ed8648535815a0506d50cbc6ed)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

arm64-acpi-pmu+nmifix 2017-05-09 20:48:56 UTC 2017-05-09
iommu/dma: Plumb in the per-CPU IOVA caches

Author: Robin Murphy
Author Date: 2017-03-31 14:46:07 UTC

iommu/dma: Plumb in the per-CPU IOVA caches

With IOVA allocation suitably tidied up, we are finally free to opt in
to the per-CPU caching mechanism. The caching alone can provide a modest
improvement over walking the rbtree for weedier systems (iperf3 shows
~10% more ethernet throughput on an ARM Juno r1 constrained to a single
650MHz Cortex-A53), but the real gain will be in sidestepping the rbtree
lock contention which larger ARM-based systems with lots of parallel I/O
are starting to feel the pain of.

Reviewed-by: Nate Watterson <nwatters@codeaurora.org>
Tested-by: Nate Watterson <nwatters@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
(cherry picked from commit bb65a64c7285e7105c1a6c8a33b37770343a4e96)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lp1688132 2017-05-04 00:57:05 UTC 2017-05-04
i2c: thunderx: Enable HWMON class probing

Author: Jan Glauber
Author Date: 2017-04-21 14:43:55 UTC

i2c: thunderx: Enable HWMON class probing

BugLink: http://bugs.launchpad.net/bugs/1688132

Set I2C_CLASS_HWMON to enable automatic probing of BMC devices
by the ipmi-ssif driver.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 889ef45cd4b64cc4fd6dbebecddb8ea4df8cc1e7)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

gtdt 2017-05-03 21:18:13 UTC 2017-05-03
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver

Author: Fu Wei
Author Date: 2017-03-31 17:51:05 UTC

acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver

BugLink: http://bugs.launchpad.net/bugs/1688114

This driver adds support for parsing SBSA Generic Watchdog timer
in GTDT, parse all info in SBSA Generic Watchdog Structure in GTDT,
and creating a platform device with that information.

This allows the operating system to obtain device data from the
resource of platform device. The platform device named "sbsa-gwdt"
can be used by the ARM SBSA Generic Watchdog driver.

Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
(cherry picked from commit ca9ae5ec4ef0ed13833b03297ab319676965492c)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lpc-20170420 2017-04-20 21:20:19 UTC 2017-04-20
UBUNTU: SAUCE: LIBIO: Make the size of the acpi_resource buffer match it's le...

Author: dann frazier
Author Date: 2017-04-20 17:38:46 UTC

UBUNTU: SAUCE: LIBIO: Make the size of the acpi_resource buffer match it's length property

BugLink: http://bugs.launchpad.net/bugs/1677319

Add a byte to the allocated buffer so that buffer->length actually matches the
allocated length. While it's not obvious that the extra byte is needed, having
the actually length of the object be shorter than the length property seems
likely to lend itself to off-by-1 bugs.

This follows the pattern used in drivers/acpi/pci_link.c and
drivers/platform/x86/sony-laptop.c.

Suggested-by: Seth Forshee <seth.forshee@canonical.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

lpc 2017-03-29 21:33:44 UTC 2017-03-29
UBUNTU: SAUCE: PCI: Restore codepath for !CONFIG_LIBIO

Author: dann frazier
Author Date: 2017-03-28 20:42:36 UTC

UBUNTU: SAUCE: PCI: Restore codepath for !CONFIG_LIBIO

BugLink: http://bugs.launchpad.net/bugs/1677319

While LIBIO is needed on arm64, it is still new infrastructure that hasn't
had a lot of testing on other architectures. This specifically impacts
Ubuntu architecures that define PCI_IOBASE: armhf, arm64 and s390x.
Restore the pre-LIBIO infrastructure when CONFIG_LIBIO=n, which we'll use
for those builds.

= Verification of correctness =
 The files referred to in this test are:
  - pci.c: drivers/pci/pci.c with this series applied
  - pci.c.lpc: Same as pci.c, but without this patch.
  - pci.c.orig: Ubuntu's pci.c, prior to this patchset.

 Test #1: Architectures that will use LIBIO and define PCI_IOBASE
          (i.e. arm64) use the new LIBIO code:

   $ unifdef -DCONFIG_LIBIO -DPCI_IOBASE pci.c > a
   $ unifdef -DPCI_IOBASE pci.c.lpc > b
   $ diff -u a b
   --- a 2017-03-29 14:36:07.444552427 -0600
   +++ b 2017-03-29 14:36:16.652547367 -0600
   @@ -3241 +3240,0 @@
   -

   (i.e., whitespace only)

 Test #2: Architectures that will *not* use LIBIO and define PCI_IOBASE
          (i.e. armhf & s390x) should use pre-LIBIO code.

   $ unifdef -UCONFIG_LIBIO -DPCI_IOBASE pci.c > a
   $ unifdef -DPCI_IOBASE pci.c.orig > b
   $ diff -U0 a b
   --- a 2017-03-29 14:42:20.640348198 -0600
   +++ b 2017-03-29 14:43:02.204325557 -0600
   @@ -3254,2 +3254 @@
   -int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
   - resource_size_t size)
   +int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)

   (i.e., just the expected changes in prototype - new *fwnode param and
    removal of unnecessary "__weak" annotation).

 Test #3: Architectures that will neither use LIBIO nor define PCI_IOBASE
          (i.e. ppc64el & x86) should use pre-LIBIO code.

   $ unifdef -UPCI_IOBASE -UCONFIG_LIBIO pci.c > a
   $ unifdef -UPCI_IOBASE pci.c.orig > b
   $ diff -U0 a b
   --- a 2017-03-29 14:45:58.064229981 -0600
   +++ b 2017-03-29 14:46:11.392222753 -0600
   @@ -3246,2 +3246 @@
   -int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
   - resource_size_t size)
   +int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
   @@ -3266,0 +3266 @@
   +

   (Again, just the expected changes in prototype - new *fwnode param and
    removal of unnecessary "__weak" annotation).

Signed-off-by: dann frazier <dann.frazier@canonical.com>

lpc-v7-rework-ifdef-new 2017-03-28 23:40:53 UTC 2017-03-28
UBUNTU: Ubuntu-4.10.0-15.17+testlpc.2

Author: dann frazier
Author Date: 2017-03-28 23:40:53 UTC

UBUNTU: Ubuntu-4.10.0-15.17+testlpc.2

Signed-off-by: dann frazier <dann.frazier@canonical.com>

lpc-v7-rework 2017-03-28 18:54:10 UTC 2017-03-28
UBUNTU: SAUCE: OF: Add missing #include

Author: dann frazier
Author Date: 2017-03-28 16:41:12 UTC

UBUNTU: SAUCE: OF: Add missing #include

Signed-off-by: dann frazier <dann.frazier@canonical.com>

dannf-lpc 2017-03-27 19:25:14 UTC 2017-03-27
LPC: Add the ACPI LPC support

Author: zhichang.yuan
Author Date: 2017-03-13 02:42:43 UTC

LPC: Add the ACPI LPC support

The patch update the _CRS of LPC children based on the relevant LIBIO
interfaces. Then the ACPI platform device enumeration for LPC can apply the
right I/O resource to request the system I/O space from ioport_resource and
ensure the LPC peripherals work well.

Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>

arm_arch_timer-erratum 2017-03-24 19:59:23 UTC 2017-03-24
UBUNTU: SAUCE: arm64: arch_timer: Add check for unknown erratum

Author: dann frazier
Author Date: 2017-03-24 19:53:05 UTC

UBUNTU: SAUCE: arm64: arch_timer: Add check for unknown erratum

If an unknown erratum type is passed into arch_timer_check_ool_workaround(),
we would call arch_timer_iterate_errata with a NULL match_fn and trigger
an Oops. This does not look possible with the existing code (all types are
accounted for), but emit an error and return if it happens to come to pass
in the future.

Reported-by: Seth Forshee <seth.foreshee@canonical.com>
Signed-off-by: dann frazier <dann.frazier@canonical.com>

armserver-pmu-rework-v4-acpi-v1 2017-03-13 21:08:47 UTC 2017-03-13
arm64: pmuv3: use arm_pmu ACPI framework

Author: Mark Rutland
Author Date: 2017-03-10 11:04:51 UTC

arm64: pmuv3: use arm_pmu ACPI framework

Now that we have a framework to handle the ACPI bits, make the PMUv3
code use this. The framework is a little different to what was
originally envisaged, and we can drop some unused support code in the
process of moving over to it.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
[v1 submission]

armserver-lpc-v7 2017-03-13 21:08:34 UTC 2017-03-13
LPC: Add the ACPI LPC support

Author: zhichang.yuan
Author Date: 2017-03-13 02:42:43 UTC

LPC: Add the ACPI LPC support

The patch update the _CRS of LPC children based on the relevant LIBIO
interfaces. Then the ACPI platform device enumeration for LPC can apply the
right I/O resource to request the system I/O space from ioport_resource and
ensure the LPC peripherals work well.

Signed-off-by: zhichang.yuan <yuanzhichang@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>

for-zesty 2017-03-13 19:14:30 UTC 2017-03-13
irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065

Author: Shanker Donthineni
Author Date: 2017-03-07 14:20:38 UTC

irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065

BugLink: http://bugs.launchpad.net/bugs/1672486

On Qualcomm Datacenter Technologies QDF2400 SoCs, the ITS hardware
implementation uses 16Bytes for Interrupt Translation Entry (ITE),
but reports an incorrect value of 8Bytes in GITS_TYPER.ITTE_size.

It might cause kernel memory corruption depending on the number
of MSI(x) that are configured and the amount of memory that has
been allocated for ITEs in its_create_device().

This patch fixes the potential memory corruption by setting the
correct ITE size to 16Bytes.

Cc: stable@vger.kernel.org
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
(cherry picked from commit 90922a2d03d84de36bf8a9979d62580102f31a92)
Signed-off-by: dann frazier <dann.frazier@canonical.com>

acpi-platform-msi 2017-03-01 17:55:12 UTC 2017-03-01
UBUNTU: SAUCE: irqchip: mbigen: Add ACPI support

Author: hanjun.guo
Author Date: 2017-01-18 12:55:05 UTC

UBUNTU: SAUCE: irqchip: mbigen: Add ACPI support

With the preparation of platform msi support and interrupt producer
in DSDT, we can add mbigen ACPI support now.

We are using Interrupt resource type in _CRS methd to indicate number
of irq pins instead of num_pins in DT to avoid _DSD usage in this case.

For mbigen,
    Device(MBI0) {
          Name(_HID, "HISI0152")
          Name(_UID, Zero)
          Name(_CRS, ResourceTemplate() {
                  Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
    Interrupt(ResourceProducer,...) {12,14,....}
          })
    }

For devices,
   Device(COM0) {
          Name(_HID, "ACPIIDxx")
          Name(_UID, Zero)
          Name(_CRS, ResourceTemplate() {
                 Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
   Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12}
          })
    }

With the help of platform msi and interrupt producer, then devices
will get the virq from mbigen's irqdomain.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Ma Jun <majun258@huawei.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
[v8 submission from:
 https://www.spinics.net/lists/arm-kernel/msg555496.html ]
BugLink: http://bugs.launchpad.net/bugs/1669061
Signed-off-by: dann frazier <dann.frazier@canonical.com>

armserver-arm_arch_timer-erratum-v0 2017-02-26 18:22:49 UTC 2017-02-26
arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data

Author: Marc Zyngier
Author Date: 2017-02-21 15:04:27 UTC

arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data

In order to deal with ACPI enabled platforms suffering from the
HISILICON_ERRATUM_161010101, let's add the required OEM data that
allow the workaround to be enabled.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
(cherry-picked from commit 857eae645c7dd0cf6c7cd652dd87bbe8041a5d70
 in the timers/errata-rework branch of
 git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git)

armserver-ras-v10 2017-02-26 17:53:34 UTC 2017-02-26
arm/arm64: KVM: add guest SEA support

Author: Tyler Baicar
Author Date: 2017-02-15 19:51:22 UTC

arm/arm64: KVM: add guest SEA support

Currently external aborts are unsupported by the guest abort
handling. Add handling for SEAs so that the host kernel reports
SEAs which occur in the guest kernel.

Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org>
(v10 submittal)

armserver-mbigen-v8 2017-02-26 17:49:43 UTC 2017-02-26
irqchip: mbigen: Add ACPI support

Author: hanjun.guo
Author Date: 2017-01-18 12:55:05 UTC

irqchip: mbigen: Add ACPI support

With the preparation of platform msi support and interrupt producer
in DSDT, we can add mbigen ACPI support now.

We are using Interrupt resource type in _CRS methd to indicate number
of irq pins instead of num_pins in DT to avoid _DSD usage in this case.

For mbigen,
    Device(MBI0) {
          Name(_HID, "HISI0152")
          Name(_UID, Zero)
          Name(_CRS, ResourceTemplate() {
                  Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
    Interrupt(ResourceProducer,...) {12,14,....}
          })
    }

For devices,
   Device(COM0) {
          Name(_HID, "ACPIIDxx")
          Name(_UID, Zero)
          Name(_CRS, ResourceTemplate() {
                 Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
   Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12}
          })
    }

With the help of platform msi and interrupt producer, then devices
will get the virq from mbigen's irqdomain.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Ma Jun <majun258@huawei.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
[v8 submittal]

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