lp:~danilovesky/workcraft/trunk-verilog-export-translate

Created by Danil Sokolov and last modified
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Branch information

Owner:
Danil Sokolov
Project:
Workcraft
Status:
Merged

Recent revisions

668. By Danil Sokolov

On/off verbose log for tracing parsers.
Export of Verilog with zero-delay pragmas and initial state of signals.
Messages about gate and pin renaming on Verilog export.

667. By Danil Sokolov

Substitution of gate and port names in Verilog export.

666. By Danil Sokolov

Improvements to the component merging tools.

665. By Danil Sokolov

Merge proposal for pgminer-update is approved.

664. By Danil Sokolov

Merge proposal for blueprint cpog-encoding approved.

663. By Danil Sokolov

Merge proposal for blueprint stg-usability approved.

662. By Danil Sokolov

User documentation is updated from the workcraft.org website.

661. By Danil Sokolov

Merge proposal for blueprint circuit-zero-delay approved.

660. By Danil Sokolov

Merge proposal for blueprint pgminer-update approved.

659. By Danil Sokolov

Merge proposal for blueprint mpsat-refactor approved.

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Branch format 6
Repository format:
Bazaar pack repository format 1 with rich root (needs bzr 1.0)
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