Merge lp:~ams-codesourcery/gcc-linaro/merge-fsf-4.5-20110505 into lp:gcc-linaro/4.5

[Andrew Stubbs]

Merge from FSF GCC 4.5 branch.

[Linaro Toolchain Builder (cbuild)]

cbuild has taken a snapshot of this branch at r99506 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505
cbuild-ancestor: lp:gcc-linaro+bzr99505
cbuild-state: check

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on i686-lucid-cbuild114-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505/logs/i686-lucid-cbuild114-scorpius-i686r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99505:
 +PASS: gcc.c-torture/compile/pr48742.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -Os (test for excess errors)
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O0
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O1
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2 -flto
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2 -fwhopr
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O3 -fomit-frame-pointer
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O3 -g
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -Os
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O0
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O1
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O2
 ...and 13 more

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505/logs/i686-lucid-cbuild114-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild114-scorpius-i686r1

[Ramana Radhakrishnan (ramana)]

Andrew - Could you check the 13 more ?

Ramana

[Andrew Stubbs (ams-codesourcery)]

> Andrew - Could you check the 13 more ?

They're all PASSes.

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild114-ursa4-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505/logs/armv7l-maverick-cbuild114-ursa4-cortexa9r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99505:
 +PASS: gcc.c-torture/compile/pr48742.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/pr48742.c -Os (test for excess errors)
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O0
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O1
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2 -flto
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O2 -fwhopr
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O3 -fomit-frame-pointer
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -O3 -g
 +PASS: gcc.c-torture/execute/pr48809.c compilation, -Os
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O0
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O1
 +PASS: gcc.c-torture/execute/pr48809.c execution, -O2
 ...and 14 more

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99506~ams-codesourcery~merge-fsf-4.5-20110505/logs/armv7l-maverick-cbuild114-ursa4-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-maverick-cbuild114-ursa4-cortexa9r1

[Richard Sandiford (rsandifo)]

Not sure whether we're doing reviews for upstream merges,
but just in case: OK if you're happy with the elided results.

review: Approve

[Andrew Stubbs (ams-codesourcery)]

i686 and ARM test results are OK.

Still waiting for x86_64 .....

[Andrew Stubbs (ams-codesourcery)]

Ok, I'm bored of waiting, the x86_64 machine has been disrupted by UDS, and I want this merged before the very last minute. I'm going to merge it, and if there's a problem, I'll revert it later.

=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro	2011-05-04 09:21:34 +0000
+++ ChangeLog.linaro	2011-05-05 15:18:28 +0000
@@ -1,3 +1,7 @@
[phone]  Andrew Stubbs  <[e-mail]>
+
+	Merge from FSF 4.5 branch r173417 (pre 4.5.4).
+
 2011-04-28  Andrew Stubbs  <[e-mail]>
 
 	Merge from FSF 4.5 branch r173113 (4.5.3 release).
 
=== modified file 'gcc/BASE-VER'
--- gcc/BASE-VER	2010-12-16 14:34:03 +0000
+++ gcc/BASE-VER	2011-05-05 15:18:28 +0000
@@ -1,1 +1,1 @@
-4.5.3
+4.5.4
 
=== modified file 'gcc/ChangeLog'
--- gcc/ChangeLog	2011-04-28 14:11:53 +0000
+++ gcc/ChangeLog	2011-05-05 15:18:28 +0000
@@ -1,3 +1,120 @@
[phone]  Ira Rosen  <[e-mail]>
+
+	Backport from mainline:
+	2011-04-18  Ulrich Weigand  <[e-mail]>
+		    Ira Rosen  <[e-mail]>
+
+	PR target/48252
+	* config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments
+	to match neon_vzip/vuzp/vtrn_internal.
+	* config/arm/neon.md (neon_vtrn<mode>_internal): Make both
+	outputs explicitly dependent on both inputs.
+	(neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Likewise.
+
[phone]  Uros Bizjak  <[e-mail]>
+
+	Backport from mainline
+	2011-04-21  Uros Bizjak  <[e-mail]>
+
+	PR target/48708
+	* config/i386/i386.c (ix86_expand_vector_set) <V2DImode>: Generate
+	vec_extract and vec_concat for non-SSE4_1 targets.
+
[phone]  Uros Bizjak  <[e-mail]>
+
+	* config/i386/i386.md (*movdi_internal_rex64) <TYPE_SSEMOV>:
+	Use %v prefix in insn mnemonic to handle TARGET_AVX.
+	(*movdi_internal): Use "maybe_vex" instead of "vex" in "prefix"
+	attribute calculation.
+	(*movdf_internal): Output AVX mnemonics.  Add "prefix" attribute.
+	* config/i386/sse.md (*sse2_storeq_rex64): Do not emit %v prefix
+	for mov{q} mnemonic.
+	(*vec_extractv2di_1_rex64_avx): Ditto.
+	(*vec_concatv2di_rex64_sse4_1): Use %vmovd for reg<->xmm moves.
+	(*vec_concatv2di_rex64_sse): Use movd for reg<->xmm moves.
+	* config/i386/mmx.md (*mov<mode>_internal_rex64): Ditto.
+
[phone]  Uros Bizjak  <[e-mail]>
+	    Jakub Jelinek  <[e-mail]>
+
+	PR target/48774
+	* config/i386/i386.c (ix86_match_ccmode): For CC{A,C,O,S}mode
+	only succeed if req_mode is the same as set_mode.
+
[phone]  Jakub Jelinek  <[e-mail]>
+
+	Backport from mainline
+	2011-04-30  Jakub Jelinek  <[e-mail]>
+
+	PR tree-optimization/48809
+	* tree-switch-conversion.c (build_arrays): Compute tidx in unsigned
+	type.
+	(gen_inbound_check): Don't compute index_expr - range_min in utype
+	again, instead reuse SSA_NAME initialized in build_arrays.
+	Remove two useless gsi_for_stmt calls.
+
+	2011-04-28  Jakub Jelinek  <[e-mail]>
+
+	PR middle-end/48597
+	* final.c (final_scan_insn): Call dwarf2out_frame_debug even for
+	inline asm.
+
+	2011-04-27  Jakub Jelinek  <[e-mail]>
+
+	PR c/48742
+	* c-typeck.c (build_binary_op): Don't wrap arguments if
+	int_operands is true.
+
+	2011-04-23  Jakub Jelinek  <[e-mail]>
+
+	PR c/48685
+	* fold-const.c (fold_convert_loc): Add NOP_EXPR when casting
+	to VOID_TYPE even around MODIFY_EXPR.
+
[phone]  Ulrich Weigand  <[e-mail]>
+
+	PR middle-end/43085
+	Backport from mainline:
+
+	2010-04-29  Bernd Schmidt  <[e-mail]>
+
+	From Dominique d'Humieres <[e-mail]>
+	PR bootstrap/43858
+	* ifcvt.c (dead_or_predicable): Use df_simulate_find_defs to compute
+	test_set.
+
+	2010-04-26  Bernd Schmidt  <[e-mail]>
+
+	* df-problems.c (df_simulate_initialize_forwards): Set, don't clear,
+	bits for artificial defs at the top of the block.
+	* fwprop.c (single_def_use_enter_block): Don't call it.
+
+	2010-04-22  Bernd Schmidt  <[e-mail]>
+
+	* ifcvt.c (dead_or_predicable): Use df_simulate_find_defs and
+	df_simulate_find_noclobber_defs as appropriate.  Keep track of an
+	extra set merge_set_noclobber, and use it to relax the final test
+	slightly.
+	* df.h (df_simulate_find_noclobber_defs): Declare.
+	* df-problems.c (df_simulate_find_defs): Don't ignore partial or
+	conditional defs.
+	(df_simulate_find_noclobber_defs): New function.
+
[phone]  John David Anglin  <[e-mail]>
+
+	PR target/48288
+	* config/pa/predicates.md (ior_operand): Delete predicate.
+	(cint_ior_operand, reg_or_cint_ior_operand): New predicates.
+	* config/pa/pa.md (iordi3): Use reg_or_cint_ior_operand predicate in
+	expander.  Use cint_ior_operand in unnamed insn.
+	(iorsi3): Likewise.
+	* config/pa/pa-protos.h (ior_operand): Delete declarations.
+
[phone]  Richard Guenther  <[e-mail]>
+
+	* DEV-PHASE: Set back to prerelease.
+	* BASE-VER: Bump to 4.5.4.
+
 2011-04-28  Release Manager
 
 	* GCC 4.5.3 released.
 
=== modified file 'gcc/DATESTAMP'
--- gcc/DATESTAMP	2011-04-28 00:17:54 +0000
+++ gcc/DATESTAMP	2011-05-05 15:18:28 +0000
@@ -1,1 +1,1 @@
-20110428
[phone]
 
=== modified file 'gcc/DEV-PHASE'
--- gcc/DEV-PHASE	2011-04-28 16:13:24 +0000
+++ gcc/DEV-PHASE	2011-05-05 15:18:28 +0000
@@ -0,0 +1,1 @@
+prerelease
 
=== modified file 'gcc/c-typeck.c'
--- gcc/c-typeck.c	2011-02-22 11:38:56 +0000
+++ gcc/c-typeck.c	2011-05-05 15:18:28 +0000
@@ -9816,7 +9816,7 @@
 		warn_for_sign_compare (location, orig_op0_folded,
 				       orig_op1_folded, op0, op1,
 				       result_type, resultcode);
-	      if (!in_late_binary_op)
+	      if (!in_late_binary_op && !int_operands)
 		{
 		  if (!op0_maybe_const || TREE_CODE (op0) != INTEGER_CST)
 		    op0 = c_wrap_maybe_const (op0, !op0_maybe_const);
 
=== modified file 'gcc/config/arm/arm.c'
--- gcc/config/arm/arm.c	2011-04-20 10:10:50 +0000
+++ gcc/config/arm/arm.c	2011-05-05 15:18:28 +0000
@@ -19823,7 +19823,7 @@
   rtx tmp1 = gen_reg_rtx (mode);
   rtx tmp2 = gen_reg_rtx (mode);
 
-  emit_insn (intfn (tmp1, op1, tmp2, op2));
+  emit_insn (intfn (tmp1, op1, op2, tmp2));
 
   emit_move_insn (mem, tmp1);
   mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
 
=== modified file 'gcc/config/arm/neon.md'
--- gcc/config/arm/neon.md	2011-04-20 10:00:39 +0000
+++ gcc/config/arm/neon.md	2011-05-05 15:18:28 +0000
@@ -4397,13 +4397,14 @@
 
 (define_insn "neon_vtrn<mode>_internal"
   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-	(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
-		     UNSPEC_VTRN1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
-        (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-		     UNSPEC_VTRN2))]
+        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+                      (match_operand:VDQW 2 "s_register_operand" "w")]
+                     UNSPEC_VTRN1))
+   (set (match_operand:VDQW 3 "s_register_operand" "=2")
+         (unspec:VDQW [(match_dup 1) (match_dup 2)]
+                     UNSPEC_VTRN2))]
   "TARGET_NEON"
-  "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+  "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
   [(set (attr "neon_type")
       (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
                     (const_string "neon_bp_simple")
@@ -4423,13 +4424,14 @@
 
 (define_insn "neon_vzip<mode>_internal"
   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-	(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
-		     UNSPEC_VZIP1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
-        (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-		     UNSPEC_VZIP2))]
+        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+                      (match_operand:VDQW 2 "s_register_operand" "w")]
+                     UNSPEC_VZIP1))
+   (set (match_operand:VDQW 3 "s_register_operand" "=2")
+        (unspec:VDQW [(match_dup 1) (match_dup 2)]
+                     UNSPEC_VZIP2))]
   "TARGET_NEON"
-  "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+  "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
   [(set (attr "neon_type")
       (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
                     (const_string "neon_bp_simple")
@@ -4449,13 +4451,14 @@
 
 (define_insn "neon_vuzp<mode>_internal"
   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-	(unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
+        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+                      (match_operand:VDQW 2 "s_register_operand" "w")]
                      UNSPEC_VUZP1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
-        (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-		     UNSPEC_VUZP2))]
+   (set (match_operand:VDQW 3 "s_register_operand" "=2")
+        (unspec:VDQW [(match_dup 1) (match_dup 2)]
+                     UNSPEC_VUZP2))]
   "TARGET_NEON"
-  "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+  "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
   [(set (attr "neon_type")
       (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
                     (const_string "neon_bp_simple")
 
=== modified file 'gcc/config/i386/i386.c'
--- gcc/config/i386/i386.c	2011-02-22 11:38:56 +0000
+++ gcc/config/i386/i386.c	2011-05-05 15:18:28 +0000
@@ -14587,11 +14587,15 @@
       if (req_mode == CCZmode)
 	return 0;
       /* FALLTHRU */
+    case CCZmode:
+      break;
+
     case CCAmode:
     case CCCmode:
     case CCOmode:
     case CCSmode:
-    case CCZmode:
+      if (set_mode != req_mode)
+	return 0;
       break;
 
     default:
@@ -27691,10 +27695,19 @@
       break;
 
     case V2DImode:
-      use_vec_merge = TARGET_SSE4_1;
+      use_vec_merge = TARGET_SSE4_1 && TARGET_64BIT;
       if (use_vec_merge)
 	break;
 
+      tmp = gen_reg_rtx (GET_MODE_INNER (mode));
+      ix86_expand_vector_extract (false, tmp, target, 1 - elt);
+      if (elt == 0)
+	tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
+      else
+	tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
+      emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
+      return;
+
     case V2DFmode:
       {
 	rtx op0, op1;
 
=== modified file 'gcc/config/i386/i386.md'
--- gcc/config/i386/i386.md	2011-02-22 11:38:56 +0000
+++ gcc/config/i386/i386.md	2011-05-05 15:18:28 +0000
@@ -2429,7 +2429,7 @@
   [(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "5,6,7,8")
-       (const_string "vex")
+       (const_string "maybe_vex")
        (const_string "orig")))
    (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
 
@@ -2467,21 +2467,15 @@
 	return "movdq2q\t{%1, %0|%0, %1}";
 
     case TYPE_SSEMOV:
-      if (TARGET_AVX)
-	{
-	  if (get_attr_mode (insn) == MODE_TI)
-	    return "vmovdqa\t{%1, %0|%0, %1}";
-	  else
-	    return "vmovq\t{%1, %0|%0, %1}";
-	}
-
       if (get_attr_mode (insn) == MODE_TI)
-	return "movdqa\t{%1, %0|%0, %1}";
-      /* FALLTHRU */
+	return "%vmovdqa\t{%1, %0|%0, %1}";
+      /* Handle broken assemblers that require movd instead of movq.  */
+      if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
+	return "%vmovd\t{%1, %0|%0, %1}";
+      return "%vmovq\t{%1, %0|%0, %1}";
 
     case TYPE_MMXMOV:
-      /* Moves from and into integer register is done using movd
-	 opcode with REX prefix.  */
+      /* Handle broken assemblers that require movd instead of movq.  */
       if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
 	return "movd\t{%1, %0|%0, %1}";
       return "movq\t{%1, %0|%0, %1}";
@@ -2914,12 +2908,13 @@
 
     case 9: case 10: case 14: case 15:
       return "movd\t{%1, %0|%0, %1}";
+
+    case 11:
+      return "movq\t{%1, %0|%0, %1}";
+
     case 12: case 13:
       return "%vmovd\t{%1, %0|%0, %1}";
 
-    case 11:
-      return "movq\t{%1, %0|%0, %1}";
-
     default:
       gcc_unreachable ();
     }
@@ -3066,6 +3061,7 @@
     case 3:
     case 4:
       return "#";
+
     case 5:
       switch (get_attr_mode (insn))
 	{
@@ -3261,7 +3257,8 @@
 
     case 9:
     case 10:
-    return "%vmovd\t{%1, %0|%0, %1}";
+      /* Handle broken assemblers that require movd instead of movq.  */
+      return "%vmovd\t{%1, %0|%0, %1}";
 
     default:
       gcc_unreachable();
@@ -3360,11 +3357,11 @@
       switch (get_attr_mode (insn))
 	{
 	case MODE_V4SF:
-	  return "xorps\t%0, %0";
+	  return "%vxorps\t%0, %d0";
 	case MODE_V2DF:
-	  return "xorpd\t%0, %0";
+	  return "%vxorpd\t%0, %d0";
 	case MODE_TI:
-	  return "pxor\t%0, %0";
+	  return "%vpxor\t%0, %d0";
 	default:
 	  gcc_unreachable ();
 	}
@@ -3374,28 +3371,56 @@
       switch (get_attr_mode (insn))
 	{
 	case MODE_V4SF:
-	  return "movaps\t{%1, %0|%0, %1}";
+	  return "%vmovaps\t{%1, %0|%0, %1}";
 	case MODE_V2DF:
-	  return "movapd\t{%1, %0|%0, %1}";
+	  return "%vmovapd\t{%1, %0|%0, %1}";
 	case MODE_TI:
-	  return "movdqa\t{%1, %0|%0, %1}";
+	  return "%vmovdqa\t{%1, %0|%0, %1}";
 	case MODE_DI:
-	  return "movq\t{%1, %0|%0, %1}";
+	  return "%vmovq\t{%1, %0|%0, %1}";
 	case MODE_DF:
-	  return "movsd\t{%1, %0|%0, %1}";
+	  if (TARGET_AVX)
+	    {
+	      if (REG_P (operands[0]) && REG_P (operands[1]))
+		return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
+	      else
+		return "vmovsd\t{%1, %0|%0, %1}";
+	    }
+	  else
+	    return "movsd\t{%1, %0|%0, %1}";
 	case MODE_V1DF:
-	  return "movlpd\t{%1, %0|%0, %1}";
+	  if (TARGET_AVX)
+	    {
+	      if (REG_P (operands[0]))
+		return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
+	      else
+		return "vmovlpd\t{%1, %0|%0, %1}";
+	    }
+	  else
+	    return "movlpd\t{%1, %0|%0, %1}";
 	case MODE_V2SF:
-	  return "movlps\t{%1, %0|%0, %1}";
+	  if (TARGET_AVX)
+	    {
+	      if (REG_P (operands[0]))
+		return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
+	      else
+		return "vmovlps\t{%1, %0|%0, %1}";
+	    }
+	  else
+	    return "movlps\t{%1, %0|%0, %1}";
 	default:
 	  gcc_unreachable ();
 	}
 
     default:
-      gcc_unreachable();
+      gcc_unreachable ();
     }
 }
   [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "0,1,2,3,4")
+       (const_string "orig")
+       (const_string "maybe_vex")))
    (set (attr "prefix_data16")
      (if_then_else (eq_attr "mode" "V1DF")
        (const_string "1")
 
=== modified file 'gcc/config/i386/mmx.md'
--- gcc/config/i386/mmx.md	2009-12-30 11:07:12 +0000
+++ gcc/config/i386/mmx.md	2011-05-05 15:18:28 +0000
@@ -63,6 +63,7 @@
   DONE;
 })
 
+;; movd instead of movq is required to handle broken assemblers.
 (define_insn "*mov<mode>_internal_rex64"
   [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
 				"=rm,r,!?y,!?y ,m  ,!y,*Y2,x,x ,m,r,Yi")
@@ -81,8 +82,8 @@
     %vpxor\t%0, %d0
     %vmovq\t{%1, %0|%0, %1}
     %vmovq\t{%1, %0|%0, %1}
-    %vmovq\t{%1, %0|%0, %1}
-    %vmovq\t{%1, %0|%0, %1}"
+    %vmovd\t{%1, %0|%0, %1}
+    %vmovd\t{%1, %0|%0, %1}"
   [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
    (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
    (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
@@ -192,6 +193,7 @@
        (const_string "orig")))
    (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
 
+;; movd instead of movq is required to handle broken assemblers.
 (define_insn "*movv2sf_internal_rex64"
   [(set (match_operand:V2SF 0 "nonimmediate_operand"
 				"=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,Yi")
 
=== modified file 'gcc/config/i386/sse.md'
--- gcc/config/i386/sse.md	2011-04-16 07:53:39 +0000
+++ gcc/config/i386/sse.md	2011-05-05 15:18:28 +0000
@@ -7473,9 +7473,8 @@
   "@
    #
    #
-   %vmov{q}\t{%1, %0|%0, %1}"
+   mov{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "*,*,imov")
-   (set_attr "prefix" "*,*,maybe_vex")
    (set_attr "mode" "*,*,DI")])
 
 (define_insn "*sse2_storeq"
@@ -7513,11 +7512,11 @@
    vmovhps\t{%1, %0|%0, %1}
    vpsrldq\t{$8, %1, %0|%0, %1, 8}
    vmovq\t{%H1, %0|%0, %H1}
-   vmov{q}\t{%H1, %0|%0, %H1}"
+   mov{q}\t{%H1, %0|%0, %H1}"
   [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
    (set_attr "length_immediate" "*,1,*,*")
    (set_attr "memory" "*,none,*,*")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "vex,vex,vex,orig")
    (set_attr "mode" "V2SF,TI,TI,DI")])
 
 (define_insn "*vec_extractv2di_1_rex64"
@@ -7795,6 +7794,7 @@
        (const_string "vex")))
    (set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
 
+;; movd instead of movq is required to handle broken assemblers.
 (define_insn "*vec_concatv2di_rex64_sse4_1"
   [(set (match_operand:V2DI 0 "register_operand"     "=x ,x ,Yi,!x,x,x,x")
 	(vec_concat:V2DI
@@ -7804,7 +7804,7 @@
   "@
    pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
    movq\t{%1, %0|%0, %1}
-   movq\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}
    movq2dq\t{%1, %0|%0, %1}
    punpcklqdq\t{%2, %0|%0, %2}
    movlhps\t{%2, %0|%0, %2}
@@ -7815,6 +7815,7 @@
    (set_attr "length_immediate" "1,*,*,*,*,*,*")
    (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
 
+;; movd instead of movq is required to handle broken assemblers.
 (define_insn "*vec_concatv2di_rex64_sse"
   [(set (match_operand:V2DI 0 "register_operand"     "=Y2 ,Yi,!Y2,Y2,x,x")
 	(vec_concat:V2DI
@@ -7823,7 +7824,7 @@
   "TARGET_64BIT && TARGET_SSE"
   "@
    movq\t{%1, %0|%0, %1}
-   movq\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}
    movq2dq\t{%1, %0|%0, %1}
    punpcklqdq\t{%2, %0|%0, %2}
    movlhps\t{%2, %0|%0, %2}
 
=== modified file 'gcc/config/pa/pa-protos.h'
--- gcc/config/pa/pa-protos.h	2009-09-23 18:08:32 +0000
+++ gcc/config/pa/pa-protos.h	2011-05-05 15:18:28 +0000
@@ -79,7 +79,6 @@
 extern int prefetch_cc_operand (rtx, enum machine_mode);
 extern int prefetch_nocc_operand (rtx, enum machine_mode);
 extern int and_operand (rtx, enum machine_mode);
-extern int ior_operand (rtx, enum machine_mode);
 extern int arith32_operand (rtx, enum machine_mode);
 extern int uint32_operand (rtx, enum machine_mode);
 extern int reg_before_reload_operand (rtx, enum machine_mode);
@@ -94,7 +93,6 @@
 extern int fmpyaddoperands (rtx *);
 extern int fmpysuboperands (rtx *);
 extern int call_operand_address (rtx, enum machine_mode);
-extern int ior_operand (rtx, enum machine_mode);
 extern void emit_bcond_fp (rtx[]);
 extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
 extern int emit_hpdiv_const (rtx *, int);
 
=== modified file 'gcc/config/pa/pa.md'
--- gcc/config/pa/pa.md	2010-12-30 21:57:32 +0000
+++ gcc/config/pa/pa.md	2011-05-05 15:18:28 +0000
@@ -5686,7 +5686,7 @@
 (define_expand "iordi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(ior:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "ior_operand" "")))]
+		(match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
   ""
   "
 {
@@ -5707,7 +5707,7 @@
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(ior:DI (match_operand:DI 1 "register_operand" "0,0")
-		(match_operand:DI 2 "ior_operand" "M,i")))]
+		(match_operand:DI 2 "cint_ior_operand" "M,i")))]
   "TARGET_64BIT"
   "* return output_64bit_ior (operands); "
   [(set_attr "type" "binary,shift")
@@ -5726,19 +5726,14 @@
 (define_expand "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
+		(match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
   ""
-  "
-{
-  if (! (ior_operand (operands[2], SImode)
-         || register_operand (operands[2], SImode)))
-    operands[2] = force_reg (SImode, operands[2]);
-}")
+  "")
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(ior:SI (match_operand:SI 1 "register_operand" "0,0")
-		(match_operand:SI 2 "ior_operand" "M,i")))]
+		(match_operand:SI 2 "cint_ior_operand" "M,i")))]
   ""
   "* return output_ior (operands); "
   [(set_attr "type" "binary,shift")
 
=== modified file 'gcc/config/pa/predicates.md'
--- gcc/config/pa/predicates.md	2010-07-03 21:46:51 +0000
+++ gcc/config/pa/predicates.md	2011-05-05 15:18:28 +0000
@@ -411,11 +411,15 @@
 
 ;; True iff depi can be used to compute (reg | OP).
 
-(define_predicate "ior_operand"
-  (match_code "const_int")
-{
-  return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
-})
+(define_predicate "cint_ior_operand"
+  (and (match_code "const_int")
+       (match_test "ior_mask_p (INTVAL (op))")))
+
+;; True iff OP can be used to compute (reg | OP).
+
+(define_predicate "reg_or_cint_ior_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "cint_ior_operand")))
 
 ;; True iff OP is a CONST_INT of the forms 0...0xxxx or
 ;; 0...01...1xxxx. Such values can be the left hand side x in (x <<
 
=== modified file 'gcc/cp/ChangeLog'
--- gcc/cp/ChangeLog	2011-04-28 14:12:32 +0000
+++ gcc/cp/ChangeLog	2011-05-05 15:18:28 +0000
@@ -1,3 +1,9 @@
[phone]  Jason Merrill  <[e-mail]>
+
+	PR c++/48046
+	* parser.c (cp_parser_diagnose_invalid_type_name): Commit
+	to tentative parse sooner.
+
 2011-04-28  Release Manager
 
 	* GCC 4.5.3 released.
 
=== modified file 'gcc/cp/parser.c'
--- gcc/cp/parser.c	2011-04-27 05:20:46 +0000
+++ gcc/cp/parser.c	2011-05-05 15:18:28 +0000
@@ -2333,6 +2333,7 @@
 				      location_t location)
 {
   tree decl, old_scope;
+  cp_parser_commit_to_tentative_parse (parser);
   /* Try to lookup the identifier.  */
   old_scope = parser->scope;
   parser->scope = scope;
@@ -2423,7 +2424,6 @@
       else
 	gcc_unreachable ();
     }
-  cp_parser_commit_to_tentative_parse (parser);
 }
 
 /* Check for a common situation where a type-name should be present,
 
=== modified file 'gcc/df-problems.c'
--- gcc/df-problems.c	2011-02-08 12:07:29 +0000
+++ gcc/df-problems.c	2011-05-05 15:18:28 +0000
@@ -3916,13 +3916,9 @@
    the block, starting with the first one.
    ----------------------------------------------------------------------------*/
 
-/* Apply the artificial uses and defs at the top of BB in a forwards
-   direction.  ??? This is wrong; defs mark the point where a pseudo
-   becomes live when scanning forwards (unless a def is unused).  Since
-   there are no REG_UNUSED notes for artificial defs, passes that
-   require artificial defs probably should not call this function
-   unless (as is the case for fwprop) they are correct when liveness
-   bitmaps are *under*estimated.  */
+/* Initialize the LIVE bitmap, which should be copied from DF_LIVE_IN or
+   DF_LR_IN for basic block BB, for forward scanning by marking artificial
+   defs live.  */
 
 void
 df_simulate_initialize_forwards (basic_block bb, bitmap live)
 
=== modified file 'gcc/final.c'
--- gcc/final.c	2011-02-08 10:51:58 +0000
+++ gcc/final.c	2011-05-05 15:18:28 +0000
@@ -2241,6 +2241,11 @@
 	    location_t loc;
 	    expanded_location expanded;
 
+	    /* Make sure we flush any queued register saves in case this
+	       clobbers affected registers.  */
+	    if (dwarf2out_do_frame ())
+	      dwarf2out_frame_debug (insn, false);
+
 	    /* There's no telling what that did to the condition codes.  */
 	    CC_STATUS_INIT;
 
 
=== modified file 'gcc/fold-const.c'
--- gcc/fold-const.c	2011-04-28 16:13:24 +0000
+++ gcc/fold-const.c	2011-05-05 15:18:28 +0000
@@ -2784,8 +2784,6 @@
 
     case VOID_TYPE:
       tem = fold_ignored_result (arg);
-      if (TREE_CODE (tem) == MODIFY_EXPR)
-	goto fold_convert_exit;
       return fold_build1_loc (loc, NOP_EXPR, type, tem);
 
     default:
 
=== modified file 'gcc/ifcvt.c'
--- gcc/ifcvt.c	2011-02-08 12:07:29 +0000
+++ gcc/ifcvt.c	2011-05-05 15:18:28 +0000
@@ -4010,8 +4010,7 @@
 {
   basic_block new_dest = dest_edge->dest;
   rtx head, end, jump, earliest = NULL_RTX, old_dest;
-  bitmap merge_set = NULL;
-  bitmap merge_set_noclobber  = NULL;
+  bitmap merge_set = NULL, merge_set_noclobber = NULL;
   /* Number of pending changes.  */
   int n_validated_changes = 0;
   rtx new_dest_label;
@@ -4165,9 +4164,11 @@
 
       /* Collect:
 	   MERGE_SET = set of registers set in MERGE_BB
+	   MERGE_SET_NOCLOBBER = like MERGE_SET, but only includes registers
+	     that are really set, not just clobbered.
 	   TEST_LIVE = set of registers live at EARLIEST
-	   TEST_SET  = set of registers set between EARLIEST and the
-		       end of the block.  */
+	   TEST_SET = set of registers set between EARLIEST and the
+	     end of the block.  */
 
       merge_set = BITMAP_ALLOC (&reg_obstack);
       merge_set_noclobber = BITMAP_ALLOC (&reg_obstack);
@@ -4182,14 +4183,8 @@
 	{
 	  if (NONDEBUG_INSN_P (insn))
 	    {
-	      unsigned int uid = INSN_UID (insn);
-	      df_ref *def_rec;
-	      for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
-		{
-		  df_ref def = *def_rec;
-		  bitmap_set_bit (merge_set, DF_REF_REGNO (def));
-		}
-              df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
+	      df_simulate_find_defs (insn, merge_set);
+	      df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
 	    }
 	}
 
@@ -4231,7 +4226,9 @@
 	}
 
       /* We can perform the transformation if
-	   MERGE_SET & (TEST_SET | TEST_LIVE)
+	   MERGE_SET_NOCLOBBER & TEST_SET
+	 and
+	   MERGE_SET & TEST_LIVE
 	 and
 	   TEST_SET & DF_LIVE_IN (merge_bb)
 	 are empty.  */
@@ -4319,11 +4316,11 @@
 	  unsigned i;
 	  bitmap_iterator bi;
 
-	  EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi)
+	  EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi)
 	    remove_reg_equal_equiv_notes_for_regno (i);
 
 	  BITMAP_FREE (merge_set);
-          BITMAP_FREE (merge_set_noclobber);
+	  BITMAP_FREE (merge_set_noclobber);
 	}
 
       reorder_insns (head, end, PREV_INSN (earliest));
 
=== modified file 'gcc/testsuite/ChangeLog'
--- gcc/testsuite/ChangeLog	2011-04-28 14:11:59 +0000
+++ gcc/testsuite/ChangeLog	2011-05-05 15:18:28 +0000
@@ -1,3 +1,53 @@
[phone]  Ira Rosen  <[e-mail]>
+
+	Backport from mainline:
+	2011-04-18  Ulrich Weigand  <[e-mail]>
+		    Ira Rosen  <[e-mail]>
+
+	PR target/48252
+	* gcc.target/arm/pr48252.c: New test.
+
[phone]  Uros Bizjak  <[e-mail]>
+
+	Backport from mainline
+	2011-04-21  Uros Bizjak  <[e-mail]>
+
+	PR target/48708
+	* gcc.target/i386/pr48708.c: New test.
+
[phone]  Uros Bizjak  <[e-mail]>
+
+	Backport from mainline
+	2010-12-08  H.J. Lu  <[e-mail]>
+
+	* gcc.target/i386/sse2-init-v2di-2.c: Add "-dp" and update
+	expected scan.
+
[phone]  Jakub Jelinek  <[e-mail]>
+
+	PR target/48774
+	* gcc.dg/pr48774.c: New test.
+
+	Backport from mainline
+	2011-04-30  Jakub Jelinek  <[e-mail]>
+
+	PR tree-optimization/48809
+	* gcc.c-torture/execute/pr48809.c: New test.
+
+	2011-04-27  Jakub Jelinek  <[e-mail]>
+
+	PR c/48742
+	* gcc.c-torture/compile/pr48742.c: New test.
+
+	2011-04-23  Jakub Jelinek  <[e-mail]>
+
+	PR c/48685
+	* gcc.dg/pr48685.c: New test.
+
[phone]  Jason Merrill  <[e-mail]>
+
+	* g++.dg/parse/ambig6.C: New.
+
 2011-04-28  Release Manager
 
 	* GCC 4.5.3 released.
 
=== added file 'gcc/testsuite/g++.dg/parse/ambig6.C'
--- gcc/testsuite/g++.dg/parse/ambig6.C	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/g++.dg/parse/ambig6.C	2011-05-05 15:18:28 +0000
@@ -0,0 +1,12 @@
+// PR c++/48046
+
+namespace N1 { typedef int   T; } // { dg-error "" }
+namespace N2 { typedef float T; } // { dg-error "" }
+
+int main()
+{
+  using namespace N1;
+  using namespace N2;
+
+  static T t;			// { dg-error "" }
+}
 
=== added file 'gcc/testsuite/gcc.c-torture/compile/pr48742.c'
--- gcc/testsuite/gcc.c-torture/compile/pr48742.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.c-torture/compile/pr48742.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,15 @@
+/* PR c/48742 */
+
+void baz (int);
+
+int
+foo (void)
+{
+  return 1 / 0 > 0;
+}
+
+void
+bar (void)
+{
+  baz (1 <= 2 % (3 >> 1 > 5 / 6 == 3));
+}
 
=== added file 'gcc/testsuite/gcc.c-torture/execute/pr48809.c'
--- gcc/testsuite/gcc.c-torture/execute/pr48809.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.c-torture/execute/pr48809.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,60 @@
+/* PR tree-optimization/48809 */
+
+extern void abort (void);
+
+int
+foo (signed char x)
+{
+  int y = 0;
+  switch (x)
+    {
+    case 0: y = 1; break;
+    case 1: y = 7; break;
+    case 2: y = 2; break;
+    case 3: y = 19; break;
+    case 4: y = 5; break;
+    case 5: y = 17; break;
+    case 6: y = 31; break;
+    case 7: y = 8; break;
+    case 8: y = 28; break;
+    case 9: y = 16; break;
+    case 10: y = 31; break;
+    case 11: y = 12; break;
+    case 12: y = 15; break;
+    case 13: y = 111; break;
+    case 14: y = 17; break;
+    case 15: y = 10; break;
+    case 16: y = 31; break;
+    case 17: y = 7; break;
+    case 18: y = 2; break;
+    case 19: y = 19; break;
+    case 20: y = 5; break;
+    case 21: y = 107; break;
+    case 22: y = 31; break;
+    case 23: y = 8; break;
+    case 24: y = 28; break;
+    case 25: y = 106; break;
+    case 26: y = 31; break;
+    case 27: y = 102; break;
+    case 28: y = 105; break;
+    case 29: y = 111; break;
+    case 30: y = 17; break;
+    case 31: y = 10; break;
+    case 32: y = 31; break;
+    case 98: y = 18; break;
+    case -62: y = 19; break;
+    }
+  return y;
+}
+
+int
+main ()
+{
+  if (foo (98) != 18 || foo (97) != 0 || foo (99) != 0)
+    abort ();
+  if (foo (-62) != 19 || foo (-63) != 0 || foo (-61) != 0)
+    abort ();
+  if (foo (28) != 105 || foo (27) != 102 || foo (29) != 111)
+    abort ();
+  return 0;
+}
 
=== added file 'gcc/testsuite/gcc.dg/pr48685.c'
--- gcc/testsuite/gcc.dg/pr48685.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.dg/pr48685.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,11 @@
+/* PR c/48685 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+main ()
+{
+  int v = 1;
+  (void) (1 == 2 ? (void) 0 : (v = 0));
+  return v;
+}
 
=== added file 'gcc/testsuite/gcc.dg/pr48774.c'
--- gcc/testsuite/gcc.dg/pr48774.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.dg/pr48774.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,38 @@
+/* PR target/48774 */
+/* { dg-do run } */
+/* { dg-options "-O2 -funroll-loops" } */
+
+extern void abort (void);
+unsigned long int s[24]
+  = { 12, ~1, 12, ~2, 12, ~4, 12, ~8, 12, ~16, 12, ~32,
+      12, ~64, 12, ~128, 12, ~256, 12, ~512, 12, ~1024, 12, ~2048 };
+struct { int n; unsigned long *e[12]; } g
+  = { 12, { &s[0], &s[2], &s[4], &s[6], &s[8], &s[10], &s[12], &s[14],
+	    &s[16], &s[18], &s[20], &s[22] } };
+int c[12];
+
+__attribute__((noinline, noclone)) void
+foo (void)
+{
+  int i, j;
+  for (i = 0; i < g.n; i++)
+    for (j = 0; j < g.n; j++)
+      {
+	if (i == j && j < g.e[0][0] && (g.e[i][1] & (1UL << j)))
+	  abort ();
+	if (j < g.e[0][0] && (g.e[i][1] & (1UL << j)))
+	  c[i]++;
+      }
+}
+
+int
+main ()
+{
+  int i;
+  asm volatile ("" : "+m" (s), "+m" (g), "+m" (c));
+  foo ();
+  for (i = 0; i < 12; i++)
+    if (c[i] != 11)
+      abort ();
+  return 0;
+}
 
=== added file 'gcc/testsuite/gcc.target/arm/pr48252.c'
--- gcc/testsuite/gcc.target/arm/pr48252.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/pr48252.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main(void)
+{
+    uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1};
+    uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2};
+    uint8x8x2_t vd1, vd2;
+    union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
+    int i;
+
+    vd1 = vzip_u8(v1, vdup_n_u8(0));
+    vd2 = vzip_u8(v2, vdup_n_u8(0));
+
+    vst1_u8(d1.buf, vd1.val[0]);
+    vst1_u8(d2.buf, vd1.val[1]);
+    vst1_u8(d3.buf, vd2.val[0]);
+    vst1_u8(d4.buf, vd2.val[1]);
+
+    for (i = 0; i < 8; i++)
+      if ((i % 2 == 0 && d4.buf[i] != 2)
+          || (i % 2 == 1 && d4.buf[i] != 0))
+         abort ();
+
+    return 0;
+}
 
=== added file 'gcc/testsuite/gcc.target/i386/pr48708.c'
--- gcc/testsuite/gcc.target/i386/pr48708.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/i386/pr48708.c	2011-05-05 15:18:28 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+typedef long long T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+foo (long long *x, struct S *y, __m128i *z)
+{
+  struct S s = *y;
+  ((T *) &s.d)[0] = *x;
+  return _mm_cmpeq_epi16 (s.d, *z);
+}
 
=== modified file 'gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c'
--- gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c	2008-08-20 12:22:30 +0000
+++ gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c	2011-05-05 15:18:28 +0000
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse4 -march=core2" } */
+/* { dg-options "-O2 -msse4 -march=core2 -dp" } */
 
 #include <emmintrin.h>
 
@@ -10,4 +10,4 @@
   return _mm_cvtsi64_si128 (b); 
 }
 
-/* { dg-final { scan-assembler "movq" } } */
+/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64_sse4_1/3" 1 } } */
 
=== modified file 'gcc/tree-switch-conversion.c'
--- gcc/tree-switch-conversion.c	2010-09-02 13:05:30 +0000
+++ gcc/tree-switch-conversion.c	2011-05-05 15:18:28 +0000
@@ -549,7 +549,7 @@
 build_arrays (gimple swtch)
 {
   tree arr_index_type;
-  tree tidx, sub, tmp;
+  tree tidx, sub, tmp, utype;
   gimple stmt;
   gimple_stmt_iterator gsi;
   int i;
@@ -557,14 +557,20 @@
 
   gsi = gsi_for_stmt (swtch);
 
+  /* Make sure we do not generate arithmetics in a subrange.  */
+  utype = TREE_TYPE (info.index_expr);
+  if (TREE_TYPE (utype))
+    utype = lang_hooks.types.type_for_mode (TYPE_MODE (TREE_TYPE (utype)), 1);
+  else
+    utype = lang_hooks.types.type_for_mode (TYPE_MODE (utype), 1);
+
   arr_index_type = build_index_type (info.range_size);
-  tmp = create_tmp_var (TREE_TYPE (info.index_expr), "csti");
+  tmp = create_tmp_var (utype, "csui");
   add_referenced_var (tmp);
   tidx = make_ssa_name (tmp, NULL);
-  sub = fold_build2_loc (loc, MINUS_EXPR,
-		     TREE_TYPE (info.index_expr), info.index_expr,
-		     fold_convert_loc (loc, TREE_TYPE (info.index_expr),
-				       info.range_min));
+  sub = fold_build2_loc (loc, MINUS_EXPR, utype,
+			 fold_convert_loc (loc, utype, info.index_expr),
+			 fold_convert_loc (loc, utype, info.range_min));
   sub = force_gimple_operand_gsi (&gsi, sub,
 				  false, NULL, true, GSI_SAME_STMT);
   stmt = gimple_build_assign (tidx, sub);
@@ -673,12 +679,7 @@
   tree label_decl2 = create_artificial_label (UNKNOWN_LOCATION);
   tree label_decl3 = create_artificial_label (UNKNOWN_LOCATION);
   gimple label1, label2, label3;
-
-  tree utype;
-  tree tmp_u_1, tmp_u_2, tmp_u_var;
-  tree cast;
-  gimple cast_assign, minus_assign;
-  tree ulb, minus;
+  tree utype, tidx;
   tree bound;
 
   gimple cond_stmt;
@@ -692,49 +693,24 @@
   gcc_assert (info.default_values);
   bb0 = gimple_bb (swtch);
 
-  /* Make sure we do not generate arithmetics in a subrange.  */
-  if (TREE_TYPE (TREE_TYPE (info.index_expr)))
-    utype = lang_hooks.types.type_for_mode
-      (TYPE_MODE (TREE_TYPE (TREE_TYPE (info.index_expr))), 1);
-  else
-    utype = lang_hooks.types.type_for_mode
-      (TYPE_MODE (TREE_TYPE (info.index_expr)), 1);
+  tidx = gimple_assign_lhs (info.arr_ref_first);
+  utype = TREE_TYPE (tidx);
 
   /* (end of) block 0 */
   gsi = gsi_for_stmt (info.arr_ref_first);
-  tmp_u_var = create_tmp_var (utype, "csui");
-  add_referenced_var (tmp_u_var);
-  tmp_u_1 = make_ssa_name (tmp_u_var, NULL);
-
-  cast = fold_convert_loc (loc, utype, info.index_expr);
-  cast_assign = gimple_build_assign (tmp_u_1, cast);
-  SSA_NAME_DEF_STMT (tmp_u_1) = cast_assign;
-  gsi_insert_before (&gsi, cast_assign, GSI_SAME_STMT);
-  update_stmt (cast_assign);
-
-  ulb = fold_convert_loc (loc, utype, info.range_min);
-  minus = fold_build2_loc (loc, MINUS_EXPR, utype, tmp_u_1, ulb);
-  minus = force_gimple_operand_gsi (&gsi, minus, false, NULL, true,
-				    GSI_SAME_STMT);
-  tmp_u_2 = make_ssa_name (tmp_u_var, NULL);
-  minus_assign = gimple_build_assign (tmp_u_2, minus);
-  SSA_NAME_DEF_STMT (tmp_u_2) = minus_assign;
-  gsi_insert_before (&gsi, minus_assign, GSI_SAME_STMT);
-  update_stmt (minus_assign);
+  gsi_next (&gsi);
 
   bound = fold_convert_loc (loc, utype, info.range_size);
-  cond_stmt = gimple_build_cond (LE_EXPR, tmp_u_2, bound, NULL_TREE, NULL_TREE);
+  cond_stmt = gimple_build_cond (LE_EXPR, tidx, bound, NULL_TREE, NULL_TREE);
   gsi_insert_before (&gsi, cond_stmt, GSI_SAME_STMT);
   update_stmt (cond_stmt);
 
   /* block 2 */
-  gsi = gsi_for_stmt (info.arr_ref_first);
   label2 = gimple_build_label (label_decl2);
   gsi_insert_before (&gsi, label2, GSI_SAME_STMT);
   last_assign = gen_def_assigns (&gsi);
 
   /* block 1 */
-  gsi = gsi_for_stmt (info.arr_ref_first);
   label1 = gimple_build_label (label_decl1);
   gsi_insert_before (&gsi, label1, GSI_SAME_STMT);
 
 
=== modified file 'libffi/ChangeLog'
--- libffi/ChangeLog	2011-04-28 14:10:51 +0000
+++ libffi/ChangeLog	2011-05-05 15:18:28 +0000
@@ -1,3 +1,13 @@
[phone]  Rainer Orth  <[e-mail]>
+
+	Backport from mainline:
+	2011-04-29  Rainer Orth  <[e-mail]>
+
+	* src/alpha/osf.S (UA_SI, FDE_ENCODING, FDE_ENCODE, FDE_ARANGE):
+	Define.
+	Use them to handle ELF vs. ECOFF differences.
+	[__osf__] (_GLOBAL__F_ffi_call_osf): Define.
+
 2011-04-28  Release Manager
 
 	* GCC 4.5.3 released.
 
=== modified file 'libffi/src/alpha/osf.S'
--- libffi/src/alpha/osf.S	2009-06-04 14:43:03 +0000
+++ libffi/src/alpha/osf.S	2011-05-05 15:18:28 +0000
@@ -1,5 +1,5 @@
 /* -----------------------------------------------------------------------
-   osf.S - Copyright (c) 1998, 2001, 2007, 2008 Red Hat
+   osf.S - Copyright (c) 1998, 2001, 2007, 2008, 2011 Red Hat
    
    Alpha/OSF Foreign Function Interface 
 
@@ -299,33 +299,51 @@
 #endif
 
 #ifdef __ELF__
+# define UA_SI		.4byte
+# define FDE_ENCODING	0x1b	/* pcrel sdata4 */
+# define FDE_ENCODE(X)	.4byte X-.
+# define FDE_ARANGE(X)	.4byte X
+#elif defined __osf__
+# define UA_SI		.align 0; .long
+# define FDE_ENCODING	0x50	/* aligned absolute */
+# define FDE_ENCODE(X)	.align 3; .quad X
+# define FDE_ARANGE(X)	.align 0; .quad X
+#endif
+
+#ifdef __ELF__
 	.section	.eh_frame,EH_FRAME_FLAGS,@progbits
+#elif defined __osf__
+	.data
+	.align 3
+	.globl _GLOBAL__F_ffi_call_osf
+_GLOBAL__F_ffi_call_osf:
+#endif
 __FRAME_BEGIN__:
-	.4byte	$LECIE1-$LSCIE1	# Length of Common Information Entry
+	UA_SI	$LECIE1-$LSCIE1	# Length of Common Information Entry
 $LSCIE1:
-	.4byte	0x0		# CIE Identifier Tag
+	UA_SI	0x0		# CIE Identifier Tag
 	.byte	0x1		# CIE Version
 	.ascii "zR\0"		# CIE Augmentation
 	.byte	0x1		# uleb128 0x1; CIE Code Alignment Factor
 	.byte	0x78		# sleb128 -8; CIE Data Alignment Factor
 	.byte	26		# CIE RA Column
 	.byte	0x1		# uleb128 0x1; Augmentation size
-	.byte	0x1b		# FDE Encoding (pcrel sdata4)
+	.byte	FDE_ENCODING	# FDE Encoding
 	.byte	0xc		# DW_CFA_def_cfa
 	.byte	30		# uleb128 column 30
 	.byte	0		# uleb128 offset 0
 	.align 3
 $LECIE1:
 $LSFDE1:
-	.4byte	$LEFDE1-$LASFDE1		# FDE Length
+	UA_SI	$LEFDE1-$LASFDE1		# FDE Length
 $LASFDE1:
-	.4byte	$LASFDE1-__FRAME_BEGIN__	# FDE CIE offset
-	.4byte	$LFB1-.		# FDE initial location
-	.4byte	$LFE1-$LFB1	# FDE address range
+	UA_SI	$LASFDE1-__FRAME_BEGIN__	# FDE CIE offset
+	FDE_ENCODE($LFB1)			# FDE initial location
+	FDE_ARANGE($LFE1-$LFB1)			# FDE address range
 	.byte	0x0		# uleb128 0x0; Augmentation size
 
 	.byte	0x4		# DW_CFA_advance_loc4
-	.4byte	$LCFI1-$LFB1
+	UA_SI	$LCFI1-$LFB1
 	.byte	0x9a		# DW_CFA_offset, column 26
 	.byte	4		# uleb128 4*-8
 	.byte	0x8f		# DW_CFA_offset, column 15
@@ -335,32 +353,35 @@
 	.byte	32		# uleb128 offset 32
 
 	.byte	0x4		# DW_CFA_advance_loc4
-	.4byte	$LCFI2-$LCFI1
+	UA_SI	$LCFI2-$LCFI1
 	.byte	0xda		# DW_CFA_restore, column 26
 	.align 3
 $LEFDE1:
 
 $LSFDE3:
-	.4byte	$LEFDE3-$LASFDE3		# FDE Length
+	UA_SI	$LEFDE3-$LASFDE3		# FDE Length
 $LASFDE3:
-	.4byte	$LASFDE3-__FRAME_BEGIN__	# FDE CIE offset
-	.4byte	$LFB2-.		# FDE initial location
-	.4byte	$LFE2-$LFB2	# FDE address range
+	UA_SI	$LASFDE3-__FRAME_BEGIN__	# FDE CIE offset
+	FDE_ENCODE($LFB2)			# FDE initial location
+	FDE_ARANGE($LFE2-$LFB2)			# FDE address range
 	.byte	0x0		# uleb128 0x0; Augmentation size
 
 	.byte	0x4		# DW_CFA_advance_loc4
-	.4byte	$LCFI5-$LFB2
+	UA_SI	$LCFI5-$LFB2
 	.byte	0xe		# DW_CFA_def_cfa_offset
 	.byte	0x80,0x1	# uleb128 128
 
 	.byte	0x4		# DW_CFA_advance_loc4
-	.4byte	$LCFI6-$LCFI5
+	UA_SI	$LCFI6-$LCFI5
 	.byte	0x9a		# DW_CFA_offset, column 26
 	.byte	16		# uleb128 offset 16*-8
 	.align 3
 $LEFDE3:
+#if defined __osf__
+	.align 0
+	.long	0		# End of Table
+#endif
 
-#ifdef __linux__
+#if defined __ELF__ && defined __linux__
 	.section	.note.GNU-stack,"",@progbits
 #endif
-#endif