Merge lp:~ams-codesourcery/gcc-linaro/lp836401-4.6 into lp:gcc-linaro/4.6

[Andrew Stubbs]

Backport final fix from upstream. (Up until now, we've only had an interim fix.)

There's no need to rush this before the release - the interim fix will do just fine.

[Michael Hope (michaelh1)]

cbuild has taken a snapshot of this branch at r106823 and queued it for build.

The diff against the ancestor r106822 is available at:
 http://builds.linaro.org/toolchain/snapshots/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6.diff

and will be built on the following builders:
 a9-builder armv5-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6
cbuild-ancestor: lp:gcc-linaro+bzr106822
cbuild-state: check

[Michael Hope (michaelh1)]

cbuild successfully built this on i686-natty-cbuild196-oort2-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/i686-natty-cbuild196-oort2-i686r1

The testsuite results are the same as the branch point lp:gcc-linaro+bzr106822

The full diff is at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/i686-natty-cbuild196-oort2-i686r1/testsuite-diff.txt

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/i686-natty-cbuild196-oort2-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild196-oort2-i686r1

[Michael Hope (michaelh1)]

cbuild successfully built this on x86_64-natty-cbuild196-oort1-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/x86_64-natty-cbuild196-oort1-x86_64r1

The testsuite results are the same as the branch point lp:gcc-linaro+bzr106822

The full diff is at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/x86_64-natty-cbuild196-oort1-x86_64r1/testsuite-diff.txt

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/x86_64-natty-cbuild196-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild196-oort1-x86_64r1

[Michael Hope (michaelh1)]

cbuild successfully built this on armv7l-natty-cbuild193-tcpanda02-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild193-tcpanda02-cortexa9r1

+PASS: gcc.target/arm/shiftable.c (test for excess errors)
+PASS: gcc.target/arm/shiftable.c scan-assembler add.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler and.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler eor.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler mvn.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler orr.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler rsb.*[al]sl #6
+PASS: gcc.target/arm/shiftable.c scan-assembler sub.*[al]sl #6

The full diff is at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild193-tcpanda02-cortexa9r1/testsuite-diff.txt

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106823~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild193-tcpanda02-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild193-tcpanda02-cortexa9r1

[Ulrich Weigand (uweigand)]

This is OK.

review: Approve

=== modified file 'gcc/config/arm/predicates.md'
--- gcc/config/arm/predicates.md	2011-10-03 09:47:33 +0000
+++ gcc/config/arm/predicates.md	2011-10-10 11:55:29 +0000
@@ -129,11 +129,12 @@
   (ior (match_operand 0 "arm_rhs_operand")
        (match_operand 0 "memory_operand")))
 
+;; This doesn't have to do much because the constant is already checked
+;; in the shift_operator predicate.
 (define_predicate "shift_amount_operand"
   (ior (and (match_test "TARGET_ARM")
 	    (match_operand 0 "s_register_operand"))
-       (and (match_operand 0 "const_int_operand")
-	    (match_test "INTVAL (op) > 0"))))
+       (match_operand 0 "const_int_operand")))
 
 (define_predicate "arm_add_operand"
   (ior (match_operand 0 "arm_rhs_operand")
@@ -219,13 +220,20 @@
        (match_test "mode == GET_MODE (op)")))
 
 ;; True for shift operators.
+;; Notes:
+;;  * mult is only permitted with a constant shift amount
+;;  * patterns that permit register shift amounts only in ARM mode use
+;;    shift_amount_operand, patterns that always allow registers do not,
+;;    so we don't have to worry about that sort of thing here.
 (define_special_predicate "shift_operator"
   (and (ior (ior (and (match_code "mult")
 		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
 		 (and (match_code "rotate")
 		      (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
 				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
-	    (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
+	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+		 (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
+			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
        (match_test "mode == GET_MODE (op)")))
 
 ;; True for MULT, to identify which variant of shift_operator is in use.
 
=== added file 'gcc/testsuite/gcc.target/arm/shiftable.c'
--- gcc/testsuite/gcc.target/arm/shiftable.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/shiftable.c	2011-10-10 11:55:29 +0000
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+
+/* ARM has shift-and-alu insns.  Depending on the ALU op GCC represents some
+   of these as a left shift, others as a multiply.  Check that we match the
+    right one.  */
+
+int
+plus (int a, int b)
+{
+  return (a * 64) + b;
+}
+
+/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
+
+int
+minus (int a, int b)
+{
+  return a - (b * 64);
+}
+
+/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
+
+int
+ior (int a, int b)
+{
+  return (a * 64) | b;
+}
+
+/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
+
+int
+xor (int a, int b)
+{
+  return (a * 64) ^ b;
+}
+
+/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
+
+int
+and (int a, int b)
+{
+  return (a * 64) & b;
+}
+
+/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
+
+int
+rsb (int a, int b)
+{
+  return (a * 64) - b;
+}
+
+/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
+
+int
+mvn (int a, int b)
+{
+  return ~(a * 64);
+}
+
+/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */