Linaro GCC

Merge lp:~ams-codesourcery/gcc-linaro/lp663939 into lp:gcc-linaro/4.6

  1. lp663939
  2. Merge into 4.6
Proposed by Andrew Stubbs
Status: Superseded
Proposed branch: lp:~ams-codesourcery/gcc-linaro/lp663939
Merge into: lp:gcc-linaro/4.6
Diff against target: 917 lines (+491/-202)
9 files modified
ChangeLog.linaro (+15/-0)
gcc/config/arm/arm-protos.h (+1/-0)
gcc/config/arm/arm.c (+297/-192)
gcc/config/arm/arm.md (+13/-9)
gcc/config/arm/constraints.md (+13/-1)
gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c (+27/-0)
gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c (+75/-0)
gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c (+28/-0)
gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c (+22/-0)
To merge this branch: bzr merge lp:~ams-codesourcery/gcc-linaro/lp663939
Reviewer Review Type Date Requested Status
Richard Sandiford Approve
Linaro Toolchain Builder Pending
Review via email: mp+72895@code.launchpad.net

This proposal supersedes a proposal from 2011-07-11.

This proposal has been superseded by a proposal from 2011-09-06.

Description of the change

These patches improve support for Thumb replicated constants, add support for ADDW and SUBW, and ensure that the most efficient sense is used (inverted, negated, or normal).

This addresses the problems identified in LP:663939.

It has now been approved upstream in this new form.

Update: The testing found a bug. I think I fixed this now, and I've overwritten this branch with the fixed patch.

(Resubmitted with updated patches 2011-08-25)

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Revision history for this message
Loïc Minier (lool) wrote : Posted in a previous version of this proposal

Looks like we should ping upstream again here

Revision history for this message
Loïc Minier (lool) wrote : Posted in a previous version of this proposal

11:57 < lool> ams_cs: Is
https://code.launchpad.net/~ams-codesourcery/gcc-linaro/lp663939/+merge/45750
              still work in progress? It seems really old now
[...]
11:58 < ams_cs> lool: last activity 12th april
11:58 < ams_cs> lool: I have to do some reworking
11:58 < ams_cs> lool: I've also discussed this patch with Ramana quite a bit

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild has taken a snapshot of this branch at r106756 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106752
cbuild-state: check

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on i686-lucid-cbuild123-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106752.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild123-scorpius-i686r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild had trouble building this on armv7l-maverick-cbuild123-ursa4-cortexa9r1.
See the following failure logs:
 failed.txt gcc-build-failed.txt

under the build results at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/armv7l-maverick-cbuild123-ursa4-cortexa9r1

The test suite was not checked as this build has no .sum style test results

cbuild-checked: armv7l-maverick-cbuild123-ursa4-cortexa9r1

review: Needs Fixing
Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on x86_64-maverick-cbuild123-crucis-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-maverick-cbuild123-crucis-x86_64r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106752.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-maverick-cbuild123-crucis-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-maverick-cbuild123-crucis-x86_64r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild has taken a snapshot of this branch at r106756 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939.tar.xdelta3.xz

and will be built on the following builders:

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106752
cbuild-state: check

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on i686-lucid-cbuild123-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106752.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild123-scorpius-i686r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild has taken a snapshot of this branch at r106756 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder armv5-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106752
cbuild-state: check

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on i686-lucid-cbuild123-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106752.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-lucid-cbuild123-scorpius-i686r1/gcc-testsuite.txt

cbuild-checked: i686-lucid-cbuild123-scorpius-i686r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on x86_64-natty-cbuild151-oort1-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild151-oort1-x86_64r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro/4.6+bzr106752.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild151-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild151-oort1-x86_64r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote : Posted in a previous version of this proposal

cbuild successfully built this on armv7l-natty-cbuild152-ursa1-armv5r2.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild152-ursa1-armv5r2

The test suite was not checked as the branch point lp:gcc-linaro/4.6+bzr106752 has nothing to compare against.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild152-ursa1-armv5r2/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild152-ursa1-armv5r2

Revision history for this message
Michael Hope (michaelh1) wrote : Posted in a previous version of this proposal

I've nuked all previous builds and re-spawned them.

Revision history for this message
Michael Hope (michaelh1) wrote : Posted in a previous version of this proposal

cbuild successfully built this on x86_64-natty-cbuild158-oort3-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild158-oort3-x86_64r1

The testsuite results are the same as the branch point lp:gcc-linaro/4.6+bzr106752

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild158-oort3-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild158-oort3-x86_64r1

Revision history for this message
Michael Hope (michaelh1) wrote : Posted in a previous version of this proposal

cbuild successfully built this on i686-natty-cbuild158-oort2-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-natty-cbuild158-oort2-i686r1

The testsuite results are the same as the branch point lp:gcc-linaro/4.6+bzr106752

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106756~ams-codesourcery~lp663939/logs/i686-natty-cbuild158-oort2-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild158-oort2-i686r1

Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild has taken a snapshot of this branch at r106800 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder armv5-builder baremetal i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106796
cbuild-state: check

Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild successfully built this on i686-natty-cbuild172-oort2-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/i686-natty-cbuild172-oort2-i686r1

The testsuite results are the same as the branch point lp:gcc-linaro/4.6+bzr106796

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/i686-natty-cbuild172-oort2-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild172-oort2-i686r1

Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild successfully built this on armv7l-natty-cbuild172-ursa1-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1

+PASS: gcc.target/arm/thumb2-replicated-constant1.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler add.*#-16843010
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler and.*#13435085
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler sub.*#-1426019584
+PASS: gcc.target/arm/thumb2-replicated-constant2.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-2004318072
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-33489408
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-572662307
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-587145984
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#13056
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#17
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1717986918
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1996488704
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#2228258
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#285212672
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#285217024
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#3342387
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#4456516
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#65536
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler addw.*#546
+PASS: gcc.target/arm/thumb2-replicated-constant3.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler and.*#-1431655766
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler bic.*#1114129
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler bic.*#170
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler orn.*#255
+PASS: gcc.target/arm/thumb2-replicated-constant4.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#252706816
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#32505856
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#3600
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#480

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild172-ursa1-cortexa9r1

Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild successfully built this on x86_64-natty-cbuild172-oort1-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild172-oort1-x86_64r1

The testsuite results are the same as the branch point lp:gcc-linaro/4.6+bzr106796

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/x86_64-natty-cbuild172-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild172-oort1-x86_64r1

Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild successfully built this on armv7l-natty-cbuild172-ursa1-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1

+PASS: gcc.target/arm/thumb2-replicated-constant1.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler add.*#-16843010
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler and.*#13435085
+PASS: gcc.target/arm/thumb2-replicated-constant1.c scan-assembler sub.*#-1426019584
+PASS: gcc.target/arm/thumb2-replicated-constant2.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-2004318072
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-33489408
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-572662307
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#-587145984
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#13056
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#17
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1717986918
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#1996488704
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#2228258
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#285212672
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#285217024
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#3342387
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#4456516
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler add.*#65536
+PASS: gcc.target/arm/thumb2-replicated-constant2.c scan-assembler addw.*#546
+PASS: gcc.target/arm/thumb2-replicated-constant3.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler and.*#-1431655766
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler bic.*#1114129
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler bic.*#170
+PASS: gcc.target/arm/thumb2-replicated-constant3.c scan-assembler orn.*#255
+PASS: gcc.target/arm/thumb2-replicated-constant4.c (test for excess errors)
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#252706816
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#32505856
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#3600
+PASS: gcc.target/arm/thumb2-replicated-constant4.c scan-assembler add.*#480

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106800~ams-codesourcery~lp663939/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild172-ursa1-cortexa9r1

Revision history for this message
Richard Sandiford (rsandifo) wrote :

OK

review: Approve

Preview Diff

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=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro 2011-08-25 11:42:09 +0000
+++ ChangeLog.linaro 2011-08-25 13:44:32 +0000
@@ -2,6 +2,21 @@
22
3 Backport from FSF mainline:3 Backport from FSF mainline:
44
5 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.c (arm_gen_constant): Move movw support ....
9 (const_ok_for_op): ... to here.
10
11 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
12
13 gcc/
14 * config/arm/arm.c (arm_gen_constant): Remove redundant can_invert.
15
162011-08-25 Andrew Stubbs <ams@codesourcery.com>
17
18 Backport from FSF mainline:
19
5 2011-08-19 Andrew Stubbs <ams@codesourcery.com>20 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
621
7 gcc/22 gcc/
823
=== modified file 'gcc/config/arm/arm-protos.h'
--- gcc/config/arm/arm-protos.h 2011-07-04 14:03:49 +0000
+++ gcc/config/arm/arm-protos.h 2011-08-25 13:44:32 +0000
@@ -46,6 +46,7 @@
46extern bool arm_small_register_classes_for_mode_p (enum machine_mode);46extern bool arm_small_register_classes_for_mode_p (enum machine_mode);
47extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);47extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
48extern int const_ok_for_arm (HOST_WIDE_INT);48extern int const_ok_for_arm (HOST_WIDE_INT);
49extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
49extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,50extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
50 HOST_WIDE_INT, rtx, rtx, int);51 HOST_WIDE_INT, rtx, rtx, int);
51extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);52extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
5253
=== modified file 'gcc/config/arm/arm.c'
--- gcc/config/arm/arm.c 2011-08-24 17:35:16 +0000
+++ gcc/config/arm/arm.c 2011-08-25 13:44:32 +0000
@@ -63,6 +63,11 @@
6363
64void (*arm_lang_output_object_attributes_hook)(void);64void (*arm_lang_output_object_attributes_hook)(void);
6565
66struct four_ints
67{
68 int i[4];
69};
70
66/* Forward function declarations. */71/* Forward function declarations. */
67static bool arm_needs_doubleword_align (enum machine_mode, const_tree);72static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
68static int arm_compute_static_chain_stack_bytes (void);73static int arm_compute_static_chain_stack_bytes (void);
@@ -81,7 +86,6 @@
81static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);86static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
82static int thumb_far_jump_used_p (void);87static int thumb_far_jump_used_p (void);
83static bool thumb_force_lr_save (void);88static bool thumb_force_lr_save (void);
84static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
85static rtx emit_sfm (int, int);89static rtx emit_sfm (int, int);
86static unsigned arm_size_return_regs (void);90static unsigned arm_size_return_regs (void);
87static bool arm_assemble_integer (rtx, unsigned int, int);91static bool arm_assemble_integer (rtx, unsigned int, int);
@@ -129,7 +133,13 @@
129static int arm_comp_type_attributes (const_tree, const_tree);133static int arm_comp_type_attributes (const_tree, const_tree);
130static void arm_set_default_type_attributes (tree);134static void arm_set_default_type_attributes (tree);
131static int arm_adjust_cost (rtx, rtx, rtx, int);135static int arm_adjust_cost (rtx, rtx, rtx, int);
132static int count_insns_for_constant (HOST_WIDE_INT, int);136static int optimal_immediate_sequence (enum rtx_code code,
137 unsigned HOST_WIDE_INT val,
138 struct four_ints *return_sequence);
139static int optimal_immediate_sequence_1 (enum rtx_code code,
140 unsigned HOST_WIDE_INT val,
141 struct four_ints *return_sequence,
142 int i);
133static int arm_get_strip_length (int);143static int arm_get_strip_length (int);
134static bool arm_function_ok_for_sibcall (tree, tree);144static bool arm_function_ok_for_sibcall (tree, tree);
135static enum machine_mode arm_promote_function_mode (const_tree,145static enum machine_mode arm_promote_function_mode (const_tree,
@@ -2525,7 +2535,7 @@
2525}2535}
25262536
2527/* Return true if I is a valid constant for the operation CODE. */2537/* Return true if I is a valid constant for the operation CODE. */
2528static int2538int
2529const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)2539const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
2530{2540{
2531 if (const_ok_for_arm (i))2541 if (const_ok_for_arm (i))
@@ -2533,7 +2543,21 @@
25332543
2534 switch (code)2544 switch (code)
2535 {2545 {
2546 case SET:
2547 /* See if we can use movw. */
2548 if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
2549 return 1;
2550 else
2551 return 0;
2552
2536 case PLUS:2553 case PLUS:
2554 /* See if we can use addw or subw. */
2555 if (TARGET_THUMB2
2556 && ((i & 0xfffff000) == 0
2557 || ((-i) & 0xfffff000) == 0))
2558 return 1;
2559 /* else fall through. */
2560
2537 case COMPARE:2561 case COMPARE:
2538 case EQ:2562 case EQ:
2539 case NE:2563 case NE:
@@ -2649,68 +2673,41 @@
2649 1);2673 1);
2650}2674}
26512675
2652/* Return the number of instructions required to synthesize the given2676/* Return a sequence of integers, in RETURN_SEQUENCE that fit into
2653 constant, if we start emitting them from bit-position I. */2677 ARM/THUMB2 immediates, and add up to VAL.
2654static int2678 Thr function return value gives the number of insns required. */
2655count_insns_for_constant (HOST_WIDE_INT remainder, int i)2679static int
2656{2680optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
2657 HOST_WIDE_INT temp1;2681 struct four_ints *return_sequence)
2658 int step_size = TARGET_ARM ? 2 : 1;
2659 int num_insns = 0;
2660
2661 gcc_assert (TARGET_ARM || i == 0);
2662
2663 do
2664 {
2665 int end;
2666
2667 if (i <= 0)
2668 i += 32;
2669 if (remainder & (((1 << step_size) - 1) << (i - step_size)))
2670 {
2671 end = i - 8;
2672 if (end < 0)
2673 end += 32;
2674 temp1 = remainder & ((0x0ff << end)
2675 | ((i < end) ? (0xff >> (32 - end)) : 0));
2676 remainder &= ~temp1;
2677 num_insns++;
2678 i -= 8 - step_size;
2679 }
2680 i -= step_size;
2681 } while (remainder);
2682 return num_insns;
2683}
2684
2685static int
2686find_best_start (unsigned HOST_WIDE_INT remainder)
2687{2682{
2688 int best_consecutive_zeros = 0;2683 int best_consecutive_zeros = 0;
2689 int i;2684 int i;
2690 int best_start = 0;2685 int best_start = 0;
2686 int insns1, insns2;
2687 struct four_ints tmp_sequence;
26912688
2692 /* If we aren't targetting ARM, the best place to start is always at2689 /* If we aren't targetting ARM, the best place to start is always at
2693 the bottom. */2690 the bottom, otherwise look more closely. */
2694 if (! TARGET_ARM)2691 if (TARGET_ARM)
2695 return 0;
2696
2697 for (i = 0; i < 32; i += 2)
2698 {2692 {
2699 int consecutive_zeros = 0;2693 for (i = 0; i < 32; i += 2)
2700
2701 if (!(remainder & (3 << i)))
2702 {2694 {
2703 while ((i < 32) && !(remainder & (3 << i)))2695 int consecutive_zeros = 0;
2704 {2696
2705 consecutive_zeros += 2;2697 if (!(val & (3 << i)))
2706 i += 2;2698 {
2707 }2699 while ((i < 32) && !(val & (3 << i)))
2708 if (consecutive_zeros > best_consecutive_zeros)2700 {
2709 {2701 consecutive_zeros += 2;
2710 best_consecutive_zeros = consecutive_zeros;2702 i += 2;
2711 best_start = i - consecutive_zeros;2703 }
2712 }2704 if (consecutive_zeros > best_consecutive_zeros)
2713 i -= 2;2705 {
2706 best_consecutive_zeros = consecutive_zeros;
2707 best_start = i - consecutive_zeros;
2708 }
2709 i -= 2;
2710 }
2714 }2711 }
2715 }2712 }
27162713
@@ -2737,13 +2734,161 @@
2737 the constant starting from `best_start', and also starting from2734 the constant starting from `best_start', and also starting from
2738 zero (i.e. with bit 31 first to be output). If `best_start' doesn't2735 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2739 yield a shorter sequence, we may as well use zero. */2736 yield a shorter sequence, we may as well use zero. */
2737 insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
2740 if (best_start != 02738 if (best_start != 0
2741 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)2739 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
2742 && (count_insns_for_constant (remainder, 0) <=2740 {
2743 count_insns_for_constant (remainder, best_start)))2741 insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
2744 best_start = 0;2742 if (insns2 <= insns1)
27452743 {
2746 return best_start;2744 *return_sequence = tmp_sequence;
2745 insns1 = insns2;
2746 }
2747 }
2748
2749 return insns1;
2750}
2751
2752/* As for optimal_immediate_sequence, but starting at bit-position I. */
2753static int
2754optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
2755 struct four_ints *return_sequence, int i)
2756{
2757 int remainder = val & 0xffffffff;
2758 int insns = 0;
2759
2760 /* Try and find a way of doing the job in either two or three
2761 instructions.
2762
2763 In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
2764 location. We start at position I. This may be the MSB, or
2765 optimial_immediate_sequence may have positioned it at the largest block
2766 of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
2767 wrapping around to the top of the word when we drop off the bottom.
2768 In the worst case this code should produce no more than four insns.
2769
2770 In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
2771 constants, shifted to any arbitrary location. We should always start
2772 at the MSB. */
2773 do
2774 {
2775 int end;
2776 int b1, b2, b3, b4;
2777 unsigned HOST_WIDE_INT result;
2778 int loc;
2779
2780 gcc_assert (insns < 4);
2781
2782 if (i <= 0)
2783 i += 32;
2784
2785 /* First, find the next normal 12/8-bit shifted/rotated immediate. */
2786 if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
2787 {
2788 loc = i;
2789 if (i <= 12 && TARGET_THUMB2 && code == PLUS)
2790 /* We can use addw/subw for the last 12 bits. */
2791 result = remainder;
2792 else
2793 {
2794 /* Use an 8-bit shifted/rotated immediate. */
2795 end = i - 8;
2796 if (end < 0)
2797 end += 32;
2798 result = remainder & ((0x0ff << end)
2799 | ((i < end) ? (0xff >> (32 - end))
2800 : 0));
2801 i -= 8;
2802 }
2803 }
2804 else
2805 {
2806 /* Arm allows rotates by a multiple of two. Thumb-2 allows
2807 arbitrary shifts. */
2808 i -= TARGET_ARM ? 2 : 1;
2809 continue;
2810 }
2811
2812 /* Next, see if we can do a better job with a thumb2 replicated
2813 constant.
2814
2815 We do it this way around to catch the cases like 0x01F001E0 where
2816 two 8-bit immediates would work, but a replicated constant would
2817 make it worse.
2818
2819 TODO: 16-bit constants that don't clear all the bits, but still win.
2820 TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
2821 if (TARGET_THUMB2)
2822 {
2823 b1 = (remainder & 0xff000000) >> 24;
2824 b2 = (remainder & 0x00ff0000) >> 16;
2825 b3 = (remainder & 0x0000ff00) >> 8;
2826 b4 = remainder & 0xff;
2827
2828 if (loc > 24)
2829 {
2830 /* The 8-bit immediate already found clears b1 (and maybe b2),
2831 but must leave b3 and b4 alone. */
2832
2833 /* First try to find a 32-bit replicated constant that clears
2834 almost everything. We can assume that we can't do it in one,
2835 or else we wouldn't be here. */
2836 unsigned int tmp = b1 & b2 & b3 & b4;
2837 unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
2838 + (tmp << 24);
2839 unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
2840 + (tmp == b3) + (tmp == b4);
2841 if (tmp
2842 && (matching_bytes >= 3
2843 || (matching_bytes == 2
2844 && const_ok_for_op (remainder & ~tmp2, code))))
2845 {
2846 /* At least 3 of the bytes match, and the fourth has at
2847 least as many bits set, or two of the bytes match
2848 and it will only require one more insn to finish. */
2849 result = tmp2;
2850 i = tmp != b1 ? 32
2851 : tmp != b2 ? 24
2852 : tmp != b3 ? 16
2853 : 8;
2854 }
2855
2856 /* Second, try to find a 16-bit replicated constant that can
2857 leave three of the bytes clear. If b2 or b4 is already
2858 zero, then we can. If the 8-bit from above would not
2859 clear b2 anyway, then we still win. */
2860 else if (b1 == b3 && (!b2 || !b4
2861 || (remainder & 0x00ff0000 & ~result)))
2862 {
2863 result = remainder & 0xff00ff00;
2864 i = 24;
2865 }
2866 }
2867 else if (loc > 16)
2868 {
2869 /* The 8-bit immediate already found clears b2 (and maybe b3)
2870 and we don't get here unless b1 is alredy clear, but it will
2871 leave b4 unchanged. */
2872
2873 /* If we can clear b2 and b4 at once, then we win, since the
2874 8-bits couldn't possibly reach that far. */
2875 if (b2 == b4)
2876 {
2877 result = remainder & 0x00ff00ff;
2878 i = 16;
2879 }
2880 }
2881 }
2882
2883 return_sequence->i[insns++] = result;
2884 remainder &= ~result;
2885
2886 if (code == SET || code == MINUS)
2887 code = PLUS;
2888 }
2889 while (remainder);
2890
2891 return insns;
2747}2892}
27482893
2749/* Emit an instruction with the indicated PATTERN. If COND is2894/* Emit an instruction with the indicated PATTERN. If COND is
@@ -2760,7 +2905,6 @@
27602905
2761/* As above, but extra parameter GENERATE which, if clear, suppresses2906/* As above, but extra parameter GENERATE which, if clear, suppresses
2762 RTL generation. */2907 RTL generation. */
2763/* ??? This needs more work for thumb2. */
27642908
2765static int2909static int
2766arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,2910arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
@@ -2772,15 +2916,15 @@
2772 int final_invert = 0;2916 int final_invert = 0;
2773 int can_negate_initial = 0;2917 int can_negate_initial = 0;
2774 int i;2918 int i;
2775 int num_bits_set = 0;
2776 int set_sign_bit_copies = 0;2919 int set_sign_bit_copies = 0;
2777 int clear_sign_bit_copies = 0;2920 int clear_sign_bit_copies = 0;
2778 int clear_zero_bit_copies = 0;2921 int clear_zero_bit_copies = 0;
2779 int set_zero_bit_copies = 0;2922 int set_zero_bit_copies = 0;
2780 int insns = 0;2923 int insns = 0, neg_insns, inv_insns;
2781 unsigned HOST_WIDE_INT temp1, temp2;2924 unsigned HOST_WIDE_INT temp1, temp2;
2782 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;2925 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
2783 int step_size = TARGET_ARM ? 2 : 1;2926 struct four_ints *immediates;
2927 struct four_ints pos_immediates, neg_immediates, inv_immediates;
27842928
2785 /* Find out which operations are safe for a given CODE. Also do a quick2929 /* Find out which operations are safe for a given CODE. Also do a quick
2786 check for degenerate cases; these can occur when DImode operations2930 check for degenerate cases; these can occur when DImode operations
@@ -2789,7 +2933,6 @@
2789 {2933 {
2790 case SET:2934 case SET:
2791 can_invert = 1;2935 can_invert = 1;
2792 can_negate = 1;
2793 break;2936 break;
27942937
2795 case PLUS:2938 case PLUS:
@@ -2817,9 +2960,6 @@
2817 gen_rtx_SET (VOIDmode, target, source));2960 gen_rtx_SET (VOIDmode, target, source));
2818 return 1;2961 return 1;
2819 }2962 }
2820
2821 if (TARGET_THUMB2)
2822 can_invert = 1;
2823 break;2963 break;
28242964
2825 case AND:2965 case AND:
@@ -2861,6 +3001,7 @@
2861 gen_rtx_NOT (mode, source)));3001 gen_rtx_NOT (mode, source)));
2862 return 1;3002 return 1;
2863 }3003 }
3004 final_invert = 1;
2864 break;3005 break;
28653006
2866 case MINUS:3007 case MINUS:
@@ -2883,7 +3024,6 @@
2883 source)));3024 source)));
2884 return 1;3025 return 1;
2885 }3026 }
2886 can_negate = 1;
28873027
2888 break;3028 break;
28893029
@@ -2892,9 +3032,7 @@
2892 }3032 }
28933033
2894 /* If we can do it in one insn get out quickly. */3034 /* If we can do it in one insn get out quickly. */
2895 if (const_ok_for_arm (val)3035 if (const_ok_for_op (val, code))
2896 || (can_negate_initial && const_ok_for_arm (-val))
2897 || (can_invert && const_ok_for_arm (~val)))
2898 {3036 {
2899 if (generate)3037 if (generate)
2900 emit_constant_insn (cond,3038 emit_constant_insn (cond,
@@ -2947,15 +3085,6 @@
2947 switch (code)3085 switch (code)
2948 {3086 {
2949 case SET:3087 case SET:
2950 /* See if we can use movw. */
2951 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2952 {
2953 if (generate)
2954 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2955 GEN_INT (val)));
2956 return 1;
2957 }
2958
2959 /* See if we can do this by sign_extending a constant that is known3088 /* See if we can do this by sign_extending a constant that is known
2960 to be negative. This is a good, way of doing it, since the shift3089 to be negative. This is a good, way of doing it, since the shift
2961 may well merge into a subsequent insn. */3090 may well merge into a subsequent insn. */
@@ -3306,121 +3435,97 @@
3306 break;3435 break;
3307 }3436 }
33083437
3309 for (i = 0; i < 32; i++)3438 /* Calculate what the instruction sequences would be if we generated it
3310 if (remainder & (1 << i))3439 normally, negated, or inverted. */
3311 num_bits_set++;3440 if (code == AND)
33123441 /* AND cannot be split into multiple insns, so invert and use BIC. */
3313 if ((code == AND)3442 insns = 99;
3314 || (code != IOR && can_invert && num_bits_set > 16))3443 else
3315 remainder ^= 0xffffffff;3444 insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
3316 else if (code == PLUS && num_bits_set > 16)3445
3317 remainder = (-remainder) & 0xffffffff;3446 if (can_negate)
33183447 neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
3319 /* For XOR, if more than half the bits are set and there's a sequence3448 &neg_immediates);
3320 of more than 8 consecutive ones in the pattern then we can XOR by the3449 else
3321 inverted constant and then invert the final result; this may save an3450 neg_insns = 99;
3322 instruction and might also lead to the final mvn being merged with3451
3323 some other operation. */3452 if (can_invert || final_invert)
3324 else if (code == XOR && num_bits_set > 163453 inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
3325 && (count_insns_for_constant (remainder ^ 0xffffffff,3454 &inv_immediates);
3326 find_best_start3455 else
3327 (remainder ^ 0xffffffff))3456 inv_insns = 99;
3328 < count_insns_for_constant (remainder,3457
3329 find_best_start (remainder))))3458 immediates = &pos_immediates;
3330 {3459
3331 remainder ^= 0xffffffff;3460 /* Is the negated immediate sequence more efficient? */
3332 final_invert = 1;3461 if (neg_insns < insns && neg_insns <= inv_insns)
3462 {
3463 insns = neg_insns;
3464 immediates = &neg_immediates;
3465 }
3466 else
3467 can_negate = 0;
3468
3469 /* Is the inverted immediate sequence more efficient?
3470 We must allow for an extra NOT instruction for XOR operations, although
3471 there is some chance that the final 'mvn' will get optimized later. */
3472 if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
3473 {
3474 insns = inv_insns;
3475 immediates = &inv_immediates;
3333 }3476 }
3334 else3477 else
3335 {3478 {
3336 can_invert = 0;3479 can_invert = 0;
3337 can_negate = 0;3480 final_invert = 0;
3338 }3481 }
33393482
3340 /* Now try and find a way of doing the job in either two or three3483 /* Now output the chosen sequence as instructions. */
3341 instructions.3484 if (generate)
3342 We start by looking for the largest block of zeros that are aligned on3485 {
3343 a 2-bit boundary, we then fill up the temps, wrapping around to the3486 for (i = 0; i < insns; i++)
3344 top of the word when we drop off the bottom.3487 {
3345 In the worst case this code should produce no more than four insns.3488 rtx new_src, temp1_rtx;
3346 Thumb-2 constants are shifted, not rotated, so the MSB is always the3489
3347 best place to start. */3490 temp1 = immediates->i[i];
33483491
3349 /* ??? Use thumb2 replicated constants when the high and low halfwords are3492 if (code == SET || code == MINUS)
3350 the same. */3493 new_src = (subtargets ? gen_reg_rtx (mode) : target);
3351 {3494 else if ((final_invert || i < (insns - 1)) && subtargets)
3352 /* Now start emitting the insns. */3495 new_src = gen_reg_rtx (mode);
3353 i = find_best_start (remainder);3496 else
3354 do3497 new_src = target;
3355 {3498
3356 int end;3499 if (can_invert)
33573500 temp1 = ~temp1;
3358 if (i <= 0)3501 else if (can_negate)
3359 i += 32;3502 temp1 = -temp1;
3360 if (remainder & (3 << (i - 2)))3503
3361 {3504 temp1 = trunc_int_for_mode (temp1, mode);
3362 end = i - 8;3505 temp1_rtx = GEN_INT (temp1);
3363 if (end < 0)3506
3364 end += 32;3507 if (code == SET)
3365 temp1 = remainder & ((0x0ff << end)3508 ;
3366 | ((i < end) ? (0xff >> (32 - end)) : 0));3509 else if (code == MINUS)
3367 remainder &= ~temp1;3510 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
33683511 else
3369 if (generate)3512 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
3370 {3513
3371 rtx new_src, temp1_rtx;3514 emit_constant_insn (cond,
33723515 gen_rtx_SET (VOIDmode, new_src,
3373 if (code == SET || code == MINUS)3516 temp1_rtx));
3374 {3517 source = new_src;
3375 new_src = (subtargets ? gen_reg_rtx (mode) : target);3518
3376 if (can_invert && code != MINUS)3519 if (code == SET)
3377 temp1 = ~temp1;3520 {
3378 }3521 can_invert = 0;
3379 else3522 can_negate = 1;
3380 {
3381 if ((final_invert || remainder) && subtargets)
3382 new_src = gen_reg_rtx (mode);
3383 else
3384 new_src = target;
3385 if (can_invert)
3386 temp1 = ~temp1;
3387 else if (can_negate)
3388 temp1 = -temp1;
3389 }
3390
3391 temp1 = trunc_int_for_mode (temp1, mode);
3392 temp1_rtx = GEN_INT (temp1);
3393
3394 if (code == SET)
3395 ;
3396 else if (code == MINUS)
3397 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
3398 else
3399 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
3400
3401 emit_constant_insn (cond,
3402 gen_rtx_SET (VOIDmode, new_src,
3403 temp1_rtx));
3404 source = new_src;
3405 }
3406
3407 if (code == SET)
3408 {
3409 can_invert = 0;
3410 code = PLUS;
3411 }
3412 else if (code == MINUS)
3413 code = PLUS;3523 code = PLUS;
34143524 }
3415 insns++;3525 else if (code == MINUS)
3416 i -= 8 - step_size;3526 code = PLUS;
3417 }3527 }
3418 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary3528 }
3419 shifts. */
3420 i -= step_size;
3421 }
3422 while (remainder);
3423 }
34243529
3425 if (final_invert)3530 if (final_invert)
3426 {3531 {
34273532
=== modified file 'gcc/config/arm/arm.md'
--- gcc/config/arm/arm.md 2011-08-25 11:42:09 +0000
+++ gcc/config/arm/arm.md 2011-08-25 13:44:32 +0000
@@ -701,21 +701,24 @@
701;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will701;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
702;; put the duplicated register first, and not try the commutative version.702;; put the duplicated register first, and not try the commutative version.
703(define_insn_and_split "*arm_addsi3"703(define_insn_and_split "*arm_addsi3"
704 [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k,r")704 [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")
705 (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk")705 (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")
706 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))]706 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
707 "TARGET_32BIT"707 "TARGET_32BIT"
708 "@708 "@
709 add%?\\t%0, %1, %2709 add%?\\t%0, %1, %2
710 add%?\\t%0, %1, %2710 add%?\\t%0, %1, %2
711 add%?\\t%0, %2, %1711 add%?\\t%0, %2, %1
712 sub%?\\t%0, %1, #%n2712 addw%?\\t%0, %1, %2
713 sub%?\\t%0, %1, #%n2713 addw%?\\t%0, %1, %2
714 sub%?\\t%0, %1, #%n2
715 sub%?\\t%0, %1, #%n2
716 subw%?\\t%0, %1, #%n2
717 subw%?\\t%0, %1, #%n2
714 #"718 #"
715 "TARGET_32BIT719 "TARGET_32BIT
716 && GET_CODE (operands[2]) == CONST_INT720 && GET_CODE (operands[2]) == CONST_INT
717 && !(const_ok_for_arm (INTVAL (operands[2]))721 && !const_ok_for_op (INTVAL (operands[2]), PLUS)
718 || const_ok_for_arm (-INTVAL (operands[2])))
719 && (reload_completed || !arm_eliminable_register (operands[1]))"722 && (reload_completed || !arm_eliminable_register (operands[1]))"
720 [(clobber (const_int 0))]723 [(clobber (const_int 0))]
721 "724 "
@@ -724,8 +727,9 @@
724 operands[1], 0);727 operands[1], 0);
725 DONE;728 DONE;
726 "729 "
727 [(set_attr "length" "4,4,4,4,4,16")730 [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")
728 (set_attr "predicable" "yes")]731 (set_attr "predicable" "yes")
732 (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]
729)733)
730734
731(define_insn_and_split "*thumb1_addsi3"735(define_insn_and_split "*thumb1_addsi3"
732736
=== modified file 'gcc/config/arm/constraints.md'
--- gcc/config/arm/constraints.md 2011-01-03 20:52:22 +0000
+++ gcc/config/arm/constraints.md 2011-08-25 13:44:32 +0000
@@ -31,7 +31,7 @@
31;; The following multi-letter normal constraints have been used:31;; The following multi-letter normal constraints have been used:
32;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz32;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
33;; in Thumb-1 state: Pa, Pb, Pc, Pd33;; in Thumb-1 state: Pa, Pb, Pc, Pd
34;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px34;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
3535
36;; The following memory constraints have been used:36;; The following memory constraints have been used:
37;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us37;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
@@ -74,6 +74,18 @@
74 (and (match_code "const_int")74 (and (match_code "const_int")
75 (match_test "(ival & 0xffff0000) == 0")))))75 (match_test "(ival & 0xffff0000) == 0")))))
7676
77(define_constraint "Pj"
78 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
79 (and (match_code "const_int")
80 (and (match_test "TARGET_THUMB2")
81 (match_test "(ival & 0xfffff000) == 0"))))
82
83(define_constraint "PJ"
84 "@internal A constant that satisfies the Pj constrant if negated."
85 (and (match_code "const_int")
86 (and (match_test "TARGET_THUMB2")
87 (match_test "((-ival) & 0xfffff000) == 0"))))
88
77(define_register_constraint "k" "STACK_REG"89(define_register_constraint "k" "STACK_REG"
78 "@internal The stack register.")90 "@internal The stack register.")
7991
8092
=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c'
--- gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 2011-08-25 13:44:32 +0000
@@ -0,0 +1,27 @@
1/* Ensure simple replicated constant immediates work. */
2/* { dg-options "-mthumb -O2" } */
3/* { dg-require-effective-target arm_thumb2_ok } */
4
5int
6foo1 (int a)
7{
8 return a + 0xfefefefe;
9}
10
11/* { dg-final { scan-assembler "add.*#-16843010" } } */
12
13int
14foo2 (int a)
15{
16 return a - 0xab00ab00;
17}
18
19/* { dg-final { scan-assembler "sub.*#-1426019584" } } */
20
21int
22foo3 (int a)
23{
24 return a & 0x00cd00cd;
25}
26
27/* { dg-final { scan-assembler "and.*#13435085" } } */
028
=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c'
--- gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 2011-08-25 13:44:32 +0000
@@ -0,0 +1,75 @@
1/* Ensure split constants can use replicated patterns. */
2/* { dg-options "-mthumb -O2" } */
3/* { dg-require-effective-target arm_thumb2_ok } */
4
5int
6foo1 (int a)
7{
8 return a + 0xfe00fe01;
9}
10
11/* { dg-final { scan-assembler "add.*#-33489408" } } */
12/* { dg-final { scan-assembler "add.*#1" } } */
13
14int
15foo2 (int a)
16{
17 return a + 0xdd01dd00;
18}
19
20/* { dg-final { scan-assembler "add.*#-587145984" } } */
21/* { dg-final { scan-assembler "add.*#65536" } } */
22
23int
24foo3 (int a)
25{
26 return a + 0x00443344;
27}
28
29/* { dg-final { scan-assembler "add.*#4456516" } } */
30/* { dg-final { scan-assembler "add.*#13056" } } */
31
32int
33foo4 (int a)
34{
35 return a + 0x77330033;
36}
37
38/* { dg-final { scan-assembler "add.*#1996488704" } } */
39/* { dg-final { scan-assembler "add.*#3342387" } } */
40
41int
42foo5 (int a)
43{
44 return a + 0x11221122;
45}
46
47/* { dg-final { scan-assembler "add.*#285217024" } } */
48/* { dg-final { scan-assembler "add.*#2228258" } } */
49
50int
51foo6 (int a)
52{
53 return a + 0x66666677;
54}
55
56/* { dg-final { scan-assembler "add.*#1717986918" } } */
57/* { dg-final { scan-assembler "add.*#17" } } */
58
59int
60foo7 (int a)
61{
62 return a + 0x99888888;
63}
64
65/* { dg-final { scan-assembler "add.*#-2004318072" } } */
66/* { dg-final { scan-assembler "add.*#285212672" } } */
67
68int
69foo8 (int a)
70{
71 return a + 0xdddddfff;
72}
73
74/* { dg-final { scan-assembler "add.*#-572662307" } } */
75/* { dg-final { scan-assembler "addw.*#546" } } */
076
=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c'
--- gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 2011-08-25 13:44:32 +0000
@@ -0,0 +1,28 @@
1/* Ensure negated/inverted replicated constant immediates work. */
2/* { dg-options "-mthumb -O2" } */
3/* { dg-require-effective-target arm_thumb2_ok } */
4
5int
6foo1 (int a)
7{
8 return a | 0xffffff00;
9}
10
11/* { dg-final { scan-assembler "orn.*#255" } } */
12
13int
14foo2 (int a)
15{
16 return a & 0xffeeffee;
17}
18
19/* { dg-final { scan-assembler "bic.*#1114129" } } */
20
21int
22foo3 (int a)
23{
24 return a & 0xaaaaaa00;
25}
26
27/* { dg-final { scan-assembler "and.*#-1431655766" } } */
28/* { dg-final { scan-assembler "bic.*#170" } } */
029
=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c'
--- gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 2011-08-25 13:44:32 +0000
@@ -0,0 +1,22 @@
1/* Ensure replicated constants don't make things worse. */
2/* { dg-options "-mthumb -O2" } */
3/* { dg-require-effective-target arm_thumb2_ok } */
4
5int
6foo1 (int a)
7{
8 /* It might be tempting to use 0x01000100, but it wouldn't help. */
9 return a + 0x01f001e0;
10}
11
12/* { dg-final { scan-assembler "add.*#32505856" } } */
13/* { dg-final { scan-assembler "add.*#480" } } */
14
15int
16foo2 (int a)
17{
18 return a + 0x0f100e10;
19}
20
21/* { dg-final { scan-assembler "add.*#252706816" } } */
22/* { dg-final { scan-assembler "add.*#3600" } } */

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