Merge lp:~ams-codesourcery/gcc-linaro/cs-merge-20110413 into lp:gcc-linaro/4.5

[Andrew Stubbs]

Latest batch of merges from Sourcery G++.

[Ira Rosen (irar)]

I am out of the office until 17/04/2011.

Note: This is an automated response to your message "[Merge]
lp:~ams-codesourcery/gcc-linaro/cs-merge-20110413 into lp:gcc-linaro"
sent on 13/4/2011 16:28:34.

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[Linaro Toolchain Builder (cbuild)]

cbuild has taken a snapshot of this branch at r99502 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413.tar.xdelta3.xz

and will be built on the following builders:
 a8-builder a9-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413
cbuild-ancestor: lp:gcc-linaro+bzr99492
cbuild-state: check

[Ramana Radhakrishnan (ramana)]

Since this is a large feature branch review is a bit harder in this case.

99493 - OK
99494 - OK
99495 - OK - has gone upstream .

99496 - OK - could go upstream into FSF 4.5 branch if possible.
99497 - OK
99498 - OK
99499 - OK

  OK if no regressions.

99500 - OK - Looks sensible but would like to do a round of benchmarking but can go in for sure.

99501 - Not fully reviewed. A first cut review - I *think* this is a sensible approach given that we can't just blanket remove SLOW_UNALIGNED_ACCESS .Should we take this at the start of the next release, so that it gets baked for 3 weeks more than just a week before the release ?

99502 - Ambivalent - Not fully reviewed . A comment is we probably want some testcases for this and it looks overall like a nice improvement.Should we take this at the start of the next release, so that it gets baked for 3 weeks more than just a week before the release ?

cheers
Ramana

[Ramana Radhakrishnan (ramana)]

As long as we can get bzr to individually commit these so that any performance archaelogy has a chance to individually benchmark each of these patches I think these are ok.

99493 - OK
99494 - OK
99495 - OK - has gone upstream .

99496 - OK - could go upstream into FSF 4.5 branch if possible.
99497 - OK
99498 - OK

Can we commit 99500, 99501 , 99502 as individual patches and do the merge just after the April release ?

Could we link 99499 only to the bug fix rather than one commit into gcc-linaro/4.5 which is the bug fix ?

Sorry I just think we should then end up having a merge request per feature or a merge request for a bug fix rather than one gigantic merge. I'm still not a power user of bzr so not totally sure if we can do all that's needed here.

Ramana

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on i686-lucid-cbuild109-scorpius-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413/logs/i686-lucid-cbuild109-scorpius-i686r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99492:
 +PASS: gcc.c-torture/compile/20110322-1.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-loops (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -Os (test for excess errors)
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg2 == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg3 == 3
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg2 == 2
 +...

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on x86_64-maverick-cbuild109-crucis-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413/logs/x86_64-maverick-cbuild109-crucis-x86_64r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99492:
 +PASS: gcc.c-torture/compile/20110322-1.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-loops (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -Os (test for excess errors)
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg2 == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg3 == 3
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 ar...

[Michael Hope (michaelh1)]

I'm happy with merging all of the correctness fixes. Please leave the new features such as unaligned memcpy() out until after this release. I want to have time to try them with Python, SPEC, and EEMBC and have time to correct any problems.

[Andrew Stubbs (ams-codesourcery)]

> Sorry I just think we should then end up having a merge request per feature or
> a merge request for a bug fix rather than one gigantic merge. I'm still not a
> power user of bzr so not totally sure if we can do all that's needed here.

In the past we've treated CS patches as pre-reviewed (which they are), and committed them directly to lp:gcc-linaro. I've only really changed this as a means to get the extra testing before I check in (I'm going to have to check the gcc.dg/guality/pr43077-1.c failures).

That said, extra review is always valuable. :)

I deliberately chose to submit them as a batch, because if I had submitted them individually I doubt we'd have had all the test results in time, and anyway some depend on others, at least textually. I did/do intend to do a rebase and push, rather than a merge, so as not to flatten the history. I can leave out some revisions if they're broken, or reviewers don't like them.

[Loïc Minier (lool)]

In any case, the history wont be flattened if you do a merge; it will be shown as a merge in the bzr history and all the individual original revisions will still be accessible; see bzr log -n0 or --include-merges to see them (or use bzr vis).

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild109-ursa3-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413/logs/armv7l-maverick-cbuild109-ursa3-cortexa9r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99492:
 +PASS: gcc.c-torture/compile/20110322-1.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-loops (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -Os (test for excess errors)
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg2 == 2
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg3 == 3
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 ...

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-maverick-cbuild109-ursa4-cortexa8r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99502~ams-codesourcery~cs-merge-20110413/logs/armv7l-maverick-cbuild109-ursa4-cortexa8r1

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99492:
 +PASS: gcc.c-torture/compile/20110322-1.c -O0 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O1 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -flto (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 -fwhopr (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O2 (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer -funroll-loops (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -fomit-frame-pointer (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/20110322-1.c -Os (test for excess errors)
 -FAIL: gcc.c-torture/compile/limits-fndefn.c -O3 -g (test for excess errors)
 +PASS: gcc.c-torture/compile/limits-fndefn.c -O3 -g (test for excess errors)
 -UNRESOLVED: gcc.dg/graphite/block-4.c compilation failed to produce executable
 +PASS: gcc.dg/graphite/block-4.c execution test
 -FAIL: gcc.dg/graphite/block-4.c (test for excess errors)
 +PASS: gcc.dg/graphite/block-4.c (test for excess errors)
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg1 == 1
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg2 == 2
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg3 == 3
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg4 == 4
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg5 == 5
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg6 == 6
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 arg7 == 30
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 *x == (char) 25
 +UNSUPPORTED: gcc.dg/guality/pr36728-1.c -O2 -flto line 14 y == 2
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg1 == 1
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg2 == 2
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg3 == 3
 -FAIL: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg4 == 4
 -PASS: gcc.dg/guality/pr36728-1.c -O2 -fwhopr line 14 arg5 == 5
 -...

[Michael Hope (michaelh1)]

I'd prefer to keep the new features for the next release. It's not far away and it'll give us some more breathing room.

[Michael Hope (michaelh1)]

Does not fix LP: #730860. Does fix LP: #736439.

[Andrew Stubbs (ams-codesourcery)]

This is now merged as far as 99498.

I'll resubmit the rest later.

review: Needs Resubmitting

[Michael Hope (michaelh1)]

For reference, I've gone through the patches and seen what's where. See:
 https://spreadsheets.google.com/spreadsheet/ccc?key=0Ap7fWLePADFVdEhKd0xrNEpjZ2NCVXE1dVFVSHlLUFE&hl=en_US

or in text:

======== ========= ======== ========== ========== =====================
Revision Bug In trunk In our 4.5 In our 4.6 Notes
======== ========= ======== ========== ========== =====================
   99493 PR45052 162528 Y (twice) Y
   99494 175641 99498 N ABI conformance
   99495 PR47763 170422 N N Dhrystone improvement
   99496 PR47427 169226 N Y ICE
   99497 171304 B N Bug
   99498 N N N Bad debug info
   99499 LP:736439 171840 N N Shrinkwrap
   99500 N N N Needs benchmarking
   99501 Unaligned; obsolete
   99502 Unaligned; obsolete
======== ========= ======== ========== ========== =====================

Based on this we should backport 99493, 99494, 99495, 99496, 99497, 99499, and 99500.

[Michael Hope (michaelh1)]

(well, except 99493 and 99496 which are already in our 4.6...)

[Michael Hope (michaelh1)]

99495 was picked up via the 4.6 release branch.

[Michael Hope (michaelh1)]

I've created merge requests for 99494, 99497, 99499 (4.6 + 4.5), and 99500.

Unmerged revisions

99502. By Andrew Stubbs on 2011-04-13

Add unaligned support for built-in memcpy.

Merged from Sourcery G++

99501. By Andrew Stubbs on 2011-04-12

Add support for unaligned loads/stores.

Merged from Sourcery G++

99500. By Andrew Stubbs on 2011-04-12

Fix performance regression when using NEON.

Merged from Sourcery G++

99499. By Andrew Stubbs on 2011-04-11

Fix shrink wrapping bug.

LP:736439

Merged from Sourcery G++

99498. By Andrew Stubbs on 2011-04-11

Fix a bug that generated bad debug info.

Merged from Sourcery G++

99497. By Andrew Stubbs on 2011-04-11

Fix bug in__builtin_isgreaterequal.

Merged from Sourcery G++

(Backport from FSF)

99496. By Andrew Stubbs on 2011-04-11

Fix internal compiler errors.

GCC Bugzilla #47427 & #47428.

Merged from Sourcery G++

(Backport from FSF)

99495. By Andrew Stubbs on 2011-04-08

Fix a performance regression in Dhrystone.

Merged from Sourcery SG++.

99494. By Andrew Stubbs on 2011-04-08

Fix an ABI conformance issue that affected armcc interoperability.

Merged from Sourcery G++.

99493. By Andrew Stubbs on 2011-04-08

Fix a bug in which "volatile" keyword could be ignored.

Merged from Sourcery G++.

(Backport from FSF)

=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro	2011-04-11 09:52:39 +0000
+++ ChangeLog.linaro	2011-04-13 13:28:18 +0000
@@ -1,3 +1,128 @@
[phone]  Julian Brown  <[e-mail]>
+
+	Issue #4220
+
+	gcc/
+	* config/arm/arm.c (arm_block_move_unaligned_straight)
+	(arm_adjust_block_mem, arm_block_move_unaligned_loop)
+	(arm_movmemqi_unaligned): New.
+	(arm_gen_movmemqi): Support unaligned block copies.
+
[phone]  Julian Brown  <[e-mail]>
+
+	Issue #4220
+
+	gcc/
+	* config/arm/arm.c (arm_override_options): Add unaligned_access
+	support.
+	* config/arm/arm.md (UNSPEC_UNALIGNED_LOAD)
+	(UNSPEC_UNALIGNED_STORE): Add constants for unspecs.
+	(insv, extzv): Add unaligned-access support.
+	(extv): Change to expander. Likewise.
+	(unaligned_loadsi, unaligned_loadhis, unaligned_loadhiu)
+	(unaligned_storesi, unaligned_storehi): New.
+	(*extv_reg): New (previous extv implementation).
+	* config/arm/arm.opt (munaligned_access): Add option.
+	* expmed.c (store_bit_field_1): Don't tweak bitfield numbering for
+	memory locations if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN.
+	(extract_bit_field_1): Likewise.
+
[phone]  Julian Brown  <[e-mail]>
+
+	Issue #6223
+
+	gcc/
+	* config/arm/arm.c (arm_vector_alignment_reachable): Don't use
+	peeling for alignment for NEON.
+
+	gcc/testsuite/
+	* lib/target-supports.exp
+	(check_effective_target_vector_alignment_reachable): Not true for
+	ARM NEON.
+
[phone]  Bernd Schmidt  <[e-mail]>
+
+	gcc/
+	* ifcvt.c (cond_exec_process_insns): Don't convert the function
+	prologue.
+
+	gcc/testsuite/
+	* gcc.c-torture/compile/20110322-1.c: New test.
+
[phone]  Paul Brook  <[e-mail]>
+	Daniel Jacobowitz  <[e-mail]>
+ 
+	Issue #3772
+	gcc/
+	* final.c (notice_source_line): Ignore zero length instructions.
+
[phone]  Sandra Loosemore  <[e-mail]>
+
+	Issue #10483
+
+	gcc/
+	Backport from mainline:
+
+	2011-03-22  Eric Botcazou  <[e-mail]>
+
+        * combine.c (simplify_set): Try harder to find the best CC mode when
+        simplifying a nested COMPARE on the RHS.
+
[phone]  Janis Johnson  <[e-mail]>
+
+	Backport from FSF mainline:
+	2011-01-25  Jakub Jelinek  <[e-mail]>
+
+	PR tree-optimization/47427
+	PR tree-optimization/47428
+	* tree-ssa-copyrename.c (copy_rename_partition_coalesce): Don't
+	coalesce if the new root var would be TREE_READONLY.
+
[phone]  Jie Zhang  <[e-mail]>
+
+	Issue #10134
+
+	Backport from mainline
+
+	gcc/
+	2011-02-23  Jie Zhang  <[e-mail]>
+
+	PR rtl-optimization/47763
+	* web.c (web_main): Ignore naked clobber when replacing register.
+
+	gcc/testsuite/
+	2011-02-23  Jie Zhang  <[e-mail]>
+
+	PR rtl-optimization/47763
+	* gcc.dg/pr47763.c: New test.
+
[phone]  Nathan Sidwell  <[e-mail]>
+
+	Issue #10439
+	gcc/
+	* config/arm/unwind-arm.c (enum __cxa_type_match_result): New.
+	(cxa_type_match): Correct declaration.
+	(__gnu_unwind_pr_common): Reconstruct
+	additional indirection when __cxa_type_match returns
+	succeeded_with_ptr_to_base.
+
+	libstdc++/
+	* libsupc++/eh_arm.c (__cxa_type_match): Construct address of
+	thrown object here.  Return succeded_with_ptr_to_base for all
+	pointer cases.
+
[phone]  Kwok Cheung Yeung  <[e-mail]>
+
+	Issue #10417
+
+	Backport from mainline
+	
+	gcc/
+	2010-07-31  Richard Guenther  <[e-mail]>
+ 
+	PR tree-optimization/45052
+	* ipa-pure-const.c (check_stmt): Check volatileness.
+
 2011-04-10  Michael Hope  <[e-mail]>
 
 	gcc/
 
=== modified file 'gcc/combine.c'
--- gcc/combine.c	2011-01-06 11:02:44 +0000
+++ gcc/combine.c	2011-04-13 13:28:18 +0000
@@ -5966,10 +5966,18 @@
       enum rtx_code new_code;
       rtx op0, op1, tmp;
       int other_changed = 0;
+      rtx inner_compare = NULL_RTX;
       enum machine_mode compare_mode = GET_MODE (dest);
 
       if (GET_CODE (src) == COMPARE)
-	op0 = XEXP (src, 0), op1 = XEXP (src, 1);
+	{
+	  op0 = XEXP (src, 0), op1 = XEXP (src, 1);
+	  if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
+	    {
+	      inner_compare = op0;
+	      op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
+	    }
+	}
       else
 	op0 = src, op1 = CONST0_RTX (GET_MODE (src));
 
@@ -6011,6 +6019,12 @@
 	 need to use a different CC mode here.  */
       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
 	compare_mode = GET_MODE (op0);
+      else if (inner_compare
+	       && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
+	       && new_code == old_code
+	       && op0 == XEXP (inner_compare, 0)
+	       && op1 == XEXP (inner_compare, 1))
+	compare_mode = GET_MODE (inner_compare);
       else
 	compare_mode = SELECT_CC_MODE (new_code, op0, op1);
 
 
=== modified file 'gcc/config/arm/arm.c'
--- gcc/config/arm/arm.c	2011-03-02 11:29:06 +0000
+++ gcc/config/arm/arm.c	2011-04-13 13:28:18 +0000
@@ -1896,6 +1896,22 @@
   if (arm_selected_tune->core == cortexm4)
     flag_schedule_interblock = 0;
 
+  /* Enable -munaligned-access by default for
+     - all ARMv6 architecture-based processors
+     - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
+
+     Disable -munaligned-access by default for
+     - all pre-ARMv6 architecture-based processors
+     - ARMv6-M architecture-based processors.  */
+
+  if (unaligned_access == 2)
+    {
+      if (arm_arch6 && (arm_arch_notm || arm_arch7))
+	unaligned_access = 1;
+      else
+	unaligned_access = 0;
+    }
+
   if (TARGET_THUMB1 && flag_schedule_insns)
     {
       /* Don't warn since it's on by default in -O2.  */
@@ -10505,6 +10521,333 @@
   return true;
 }
 
+/* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
+   unaligned copies on processors which support unaligned semantics for those
+   instructions.  INTERLEAVE_FACTOR can be used to attempt to hide load latency
+   (using more registers) by doing e.g. load/load/store/store for a factor of 2.
+   An interleave factor of 1 (the minimum) will perform no interleaving. 
+   Load/store multiple are used for aligned addresses where possible.  */
+
+static void
+arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
+				   HOST_WIDE_INT length,
+				   unsigned int interleave_factor)
+{
+  rtx *regs = XALLOCAVEC (rtx, interleave_factor);
+  HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
+  HOST_WIDE_INT i, j;
+  HOST_WIDE_INT remaining = length, words;
+  rtx halfword_tmp = NULL, byte_tmp = NULL;
+  rtx dst, src;
+  bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
+  bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
+  HOST_WIDE_INT srcoffset, dstoffset;
+  HOST_WIDE_INT src_autoinc, dst_autoinc;
+  rtx mem, addr;
+  
+  gcc_assert (1 <= interleave_factor && interleave_factor <= 4);
+  
+  /* Use hard registers if we have aligned source or destination so we can use
+     load/store multiple with contiguous registers.  */
+  if (dst_aligned || src_aligned)
+    for (i = 0; i < interleave_factor; i++)
+      regs[i] = gen_rtx_REG (SImode, i);
+  else
+    for (i = 0; i < interleave_factor; i++)
+      regs[i] = gen_reg_rtx (SImode);
+
+  dst = copy_addr_to_reg (XEXP (dstbase, 0));
+  src = copy_addr_to_reg (XEXP (srcbase, 0));
+
+  srcoffset = dstoffset = 0;
+  
+  /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
+     For copying the last bytes we want to subtract this offset again.  */
+  src_autoinc = dst_autoinc = 0;
+
+  /* Copy BLOCK_SIZE_BYTES chunks.  */
+
+  for (i = 0; i + block_size_bytes <= length; i += block_size_bytes)
+    {
+      /* Load words.  */
+      if (src_aligned && interleave_factor > 1)
+        {
+	  emit_insn (arm_gen_load_multiple (arm_regs_in_sequence,
+					    interleave_factor, src, TRUE,
+					    srcbase, &srcoffset));
+	  src_autoinc += UNITS_PER_WORD * interleave_factor;
+	}
+      else
+        {
+	  for (j = 0; j < interleave_factor; j++)
+	    {
+	      addr = plus_constant (src, srcoffset + j * UNITS_PER_WORD
+					 - src_autoinc);
+	      mem = adjust_automodify_address (srcbase, SImode, addr,
+					       srcoffset + j * UNITS_PER_WORD);
+	      emit_insn (gen_unaligned_loadsi (regs[j], mem));
+	    }
+	  srcoffset += block_size_bytes;
+	}
+
+      /* Store words.  */
+      if (dst_aligned && interleave_factor > 1)
+        {
+          emit_insn (arm_gen_store_multiple (arm_regs_in_sequence,
+					     interleave_factor, dst, TRUE,
+					     dstbase, &dstoffset));
+	  dst_autoinc += UNITS_PER_WORD * interleave_factor;
+	}
+      else
+        {
+	  for (j = 0; j < interleave_factor; j++)
+	    {
+	      addr = plus_constant (dst, dstoffset + j * UNITS_PER_WORD
+					 - dst_autoinc);
+	      mem = adjust_automodify_address (dstbase, SImode, addr,
+					       dstoffset + j * UNITS_PER_WORD);
+	      emit_insn (gen_unaligned_storesi (mem, regs[j]));
+	    }
+	  dstoffset += block_size_bytes;
+	}
+
+      remaining -= block_size_bytes;
+    }
+  
+  /* Copy any whole words left (note these aren't interleaved with any
+     subsequent halfword/byte load/stores in the interests of simplicity).  */
+  
+  words = remaining / UNITS_PER_WORD;
+
+  gcc_assert (words < interleave_factor);
+  
+  if (src_aligned && words > 1)
+    {
+      emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, words, src,
+					TRUE, srcbase, &srcoffset));
+      src_autoinc += UNITS_PER_WORD * words;
+    }
+  else
+    {
+      for (j = 0; j < words; j++)
+        {
+	  addr = plus_constant (src,
+				srcoffset + j * UNITS_PER_WORD - src_autoinc);
+	  mem = adjust_automodify_address (srcbase, SImode, addr,
+					   srcoffset + j * UNITS_PER_WORD);
+	  emit_insn (gen_unaligned_loadsi (regs[j], mem));
+	}
+      srcoffset += words * UNITS_PER_WORD;
+    }
+
+  if (dst_aligned && words > 1)
+    {
+      emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, words, dst,
+					 TRUE, dstbase, &dstoffset));
+      dst_autoinc += words * UNITS_PER_WORD;
+    }
+  else
+    {
+      for (j = 0; j < words; j++)
+        {
+	  addr = plus_constant (dst,
+				dstoffset + j * UNITS_PER_WORD - dst_autoinc);
+	  mem = adjust_automodify_address (dstbase, SImode, addr,
+					   dstoffset + j * UNITS_PER_WORD);
+	  emit_insn (gen_unaligned_storesi (mem, regs[j]));
+	}
+      dstoffset += words * UNITS_PER_WORD;
+    }
+
+  remaining -= words * UNITS_PER_WORD;
+  
+  gcc_assert (remaining < 4);
+  
+  /* Copy a halfword if necessary.  */
+  
+  if (remaining >= 2)
+    {
+      halfword_tmp = gen_reg_rtx (SImode);
+
+      addr = plus_constant (src, srcoffset - src_autoinc);
+      mem = adjust_automodify_address (srcbase, HImode, addr, srcoffset);
+      emit_insn (gen_unaligned_loadhiu (halfword_tmp, mem));
+
+      /* Either write out immediately, or delay until we've loaded the last
+	 byte, depending on interleave factor.  */
+      if (interleave_factor == 1)
+        {
+	  addr = plus_constant (dst, dstoffset - dst_autoinc);
+	  mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
+	  emit_insn (gen_unaligned_storehi (mem,
+		       gen_lowpart (HImode, halfword_tmp)));
+	  halfword_tmp = NULL;
+	  dstoffset += 2;
+	}
+
+      remaining -= 2;
+      srcoffset += 2;
+    }
+  
+  gcc_assert (remaining < 2);
+  
+  /* Copy last byte.  */
+  
+  if ((remaining & 1) != 0)
+    {
+      byte_tmp = gen_reg_rtx (SImode);
+
+      addr = plus_constant (src, srcoffset - src_autoinc);
+      mem = adjust_automodify_address (srcbase, QImode, addr, srcoffset);
+      emit_move_insn (gen_lowpart (QImode, byte_tmp), mem);
+
+      if (interleave_factor == 1)
+        {
+	  addr = plus_constant (dst, dstoffset - dst_autoinc);
+	  mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
+	  emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
+	  byte_tmp = NULL;
+	  dstoffset++;
+	}
+
+      remaining--;
+      srcoffset++;
+    }
+  
+  /* Store last halfword if we haven't done so already.  */
+  
+  if (halfword_tmp)
+    {
+      addr = plus_constant (dst, dstoffset - dst_autoinc);
+      mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
+      emit_insn (gen_unaligned_storehi (mem,
+		   gen_lowpart (HImode, halfword_tmp)));
+      dstoffset += 2;
+    }
+
+  /* Likewise for last byte.  */
+
+  if (byte_tmp)
+    {
+      addr = plus_constant (dst, dstoffset - dst_autoinc);
+      mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
+      emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
+      dstoffset++;
+    }
+  
+  gcc_assert (remaining == 0 && srcoffset == dstoffset);
+}
+
+/* From mips_adjust_block_mem:
+
+   Helper function for doing a loop-based block operation on memory
+   reference MEM.  Each iteration of the loop will operate on LENGTH
+   bytes of MEM.
+
+   Create a new base register for use within the loop and point it to
+   the start of MEM.  Create a new memory reference that uses this
+   register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
+
+static void
+arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg,
+		      rtx *loop_mem)
+{
+  *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
+  
+  /* Although the new mem does not refer to a known location,
+     it does keep up to LENGTH bytes of alignment.  */
+  *loop_mem = change_address (mem, BLKmode, *loop_reg);
+  set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
+}
+
+/* From mips_block_move_loop:
+
+   Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
+   bytes at a time.  LENGTH must be at least BYTES_PER_ITER.  Assume that
+   the memory regions do not overlap.  */
+
+static void
+arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length,
+			       unsigned int interleave_factor,
+			       HOST_WIDE_INT bytes_per_iter)
+{
+  rtx label, src_reg, dest_reg, final_src, test;
+  HOST_WIDE_INT leftover;
+  
+  leftover = length % bytes_per_iter;
+  length -= leftover;
+  
+  /* Create registers and memory references for use within the loop.  */
+  arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
+  arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
+  
+  /* Calculate the value that SRC_REG should have after the last iteration of
+     the loop.  */
+  final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
+				   0, 0, OPTAB_WIDEN);
+
+  /* Emit the start of the loop.  */
+  label = gen_label_rtx ();
+  emit_label (label);
+  
+  /* Emit the loop body.  */
+  arm_block_move_unaligned_straight (dest, src, bytes_per_iter,
+				     interleave_factor);
+
+  /* Move on to the next block.  */
+  emit_move_insn (src_reg, plus_constant (src_reg, bytes_per_iter));
+  emit_move_insn (dest_reg, plus_constant (dest_reg, bytes_per_iter));
+  
+  /* Emit the loop condition.  */
+  test = gen_rtx_NE (VOIDmode, src_reg, final_src);
+  emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
+  
+  /* Mop up any left-over bytes.  */
+  if (leftover)
+    arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor);
+}
+
+/* Emit a block move when either the source or destination is unaligned (not
+   aligned to a four-byte boundary).  This may need further tuning depending on
+   core type, optimize_size setting, alignment of source/destination, etc.  */
+
+static int
+arm_movmemqi_unaligned (rtx *operands)
+{
+  HOST_WIDE_INT length = INTVAL (operands[2]);
+  
+  if (optimize_size)
+    {
+      bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD;
+      bool dst_aligned = MEM_ALIGN (operands[0]) >= BITS_PER_WORD;
+      /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
+         size of code if optimizing for size.  We'll use ldm/stm if src_aligned
+	 or dst_aligned though: allow more interleaving in those cases since the
+	 resulting code can be smaller.  */
+      unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1;
+      HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4;
+      
+      if (length > 12)
+	arm_block_move_unaligned_loop (operands[0], operands[1], length,
+				       interleave_factor, bytes_per_iter);
+      else
+	arm_block_move_unaligned_straight (operands[0], operands[1], length,
+					   interleave_factor);
+    }
+  else
+    {
+      /* Note that the loop created by arm_block_move_unaligned_loop may be
+         subject to loop unrolling, which makes tuning this condition a little
+	 awkward.  */
+      if (length > 32)
+	arm_block_move_unaligned_loop (operands[0], operands[1], length, 4, 16);
+      else
+	arm_block_move_unaligned_straight (operands[0], operands[1], length, 4);
+    }
+  
+  return 1;
+}
+
 int
 arm_gen_movmemqi (rtx *operands)
 {
@@ -10517,8 +10860,13 @@
 
   if (GET_CODE (operands[2]) != CONST_INT
       || GET_CODE (operands[3]) != CONST_INT
-      || INTVAL (operands[2]) > 64
-      || INTVAL (operands[3]) & 3)
+      || INTVAL (operands[2]) > 64)
+    return 0;
+
+  if (unaligned_access && (INTVAL (operands[3]) & 3) != 0)
+    return arm_movmemqi_unaligned (operands);
+
+  if (INTVAL (operands[3]) & 3)
     return 0;
 
   dstbase = operands[0];
@@ -23095,10 +23443,13 @@
 static bool
 arm_vector_alignment_reachable (const_tree type, bool is_packed)
 {
-  /* Vectors which aren't in packed structures will not be less aligned than
-     the natural alignment of their element type, so this is safe.  */
+  /* NOTE: returning true here will unconditionally peel loop iterations so
+     that aligned accesses can be used.  This is undesirable when misaligned
+     accesses are available, particularly for small loop iteration counts,
+     since the overhead for dispatching to multiple versions of the loop is
+     quite high.  */
   if (TARGET_NEON && !BYTES_BIG_ENDIAN)
-    return !is_packed;
+    return false;
 
   return default_builtin_vector_alignment_reachable (type, is_packed);
 }
 
=== modified file 'gcc/config/arm/arm.md'
--- gcc/config/arm/arm.md	2011-03-11 14:26:34 +0000
+++ gcc/config/arm/arm.md	2011-04-13 13:28:18 +0000
@@ -104,6 +104,8 @@
    (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
                              ; another symbolic address.
    (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
+   (UNSPEC_UNALIGNED_LOAD 29)
+   (UNSPEC_UNALIGNED_STORE 30)
   ]
 )
 
@@ -2372,7 +2374,7 @@
 ;;; this insv pattern, so this pattern needs to be reevalutated.
 
 (define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "")
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
                          (match_operand:SI 1 "general_operand" "")
                          (match_operand:SI 2 "general_operand" ""))
         (match_operand:SI 3 "reg_or_int_operand" ""))]
@@ -2386,35 +2388,66 @@
 
     if (arm_arch_thumb2)
       {
-	bool use_bfi = TRUE;
-
-	if (GET_CODE (operands[3]) == CONST_INT)
-	  {
-	    HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
-
-	    if (val == 0)
-	      {
-		emit_insn (gen_insv_zero (operands[0], operands[1],
-					  operands[2]));
+        if (unaligned_access && MEM_P (operands[0])
+	    && s_register_operand (operands[3], GET_MODE (operands[3]))
+	    && (width == 16 || width == 32) && (start_bit % BITS_PER_UNIT) == 0)
+	  {
+	    rtx base_addr;
+	    
+	    if (width == 32)
+	      {
+	        base_addr = adjust_address (operands[0], SImode,
+					    start_bit / BITS_PER_UNIT);
+		emit_insn (gen_unaligned_storesi (base_addr, operands[3]));
+	      }
+	    else
+	      {
+	        rtx tmp = gen_reg_rtx (HImode);
+
+	        base_addr = adjust_address (operands[0], HImode,
+					    start_bit / BITS_PER_UNIT);
+		emit_move_insn (tmp, gen_lowpart (HImode, operands[3]));
+		emit_insn (gen_unaligned_storehi (base_addr, tmp));
+	      }
+	    DONE;
+	  }
+	else if (s_register_operand (operands[0], GET_MODE (operands[0])))
+	  {
+	    bool use_bfi = TRUE;
+
+	    if (GET_CODE (operands[3]) == CONST_INT)
+	      {
+		HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
+
+		if (val == 0)
+		  {
+		    emit_insn (gen_insv_zero (operands[0], operands[1],
+					      operands[2]));
+		    DONE;
+		  }
+
+		/* See if the set can be done with a single orr instruction.  */
+		if (val == mask && const_ok_for_arm (val << start_bit))
+		  use_bfi = FALSE;
+	      }
+
+	    if (use_bfi)
+	      {
+		if (GET_CODE (operands[3]) != REG)
+		  operands[3] = force_reg (SImode, operands[3]);
+
+		emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
+					operands[3]));
 		DONE;
 	      }
-
-	    /* See if the set can be done with a single orr instruction.  */
-	    if (val == mask && const_ok_for_arm (val << start_bit))
-	      use_bfi = FALSE;
-	  }
-	  
-	if (use_bfi)
-	  {
-	    if (GET_CODE (operands[3]) != REG)
-	      operands[3] = force_reg (SImode, operands[3]);
-
-	    emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
-				    operands[3]));
-	    DONE;
-	  }
+	  }
+	else
+	  FAIL;
       }
 
+    if (!s_register_operand (operands[0], GET_MODE (operands[0])))
+      FAIL;
+
     target = copy_rtx (operands[0]);
     /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical 
        subreg as the final target.  */
@@ -3604,7 +3637,7 @@
 
 (define_expand "extzv"
   [(set (match_dup 4)
-	(ashift:SI (match_operand:SI   1 "register_operand" "")
+	(ashift:SI (match_operand:SI   1 "nonimmediate_operand" "")
 		   (match_operand:SI   2 "const_int_operand" "")))
    (set (match_operand:SI              0 "register_operand" "")
 	(lshiftrt:SI (match_dup 4)
@@ -3617,10 +3650,53 @@
     
     if (arm_arch_thumb2)
       {
-	emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
-				 operands[3]));
-	DONE;
+	HOST_WIDE_INT width = INTVAL (operands[2]);
+	HOST_WIDE_INT bitpos = INTVAL (operands[3]);
+
+	if (unaligned_access && MEM_P (operands[1])
+	    && (width == 16 || width == 32) && (bitpos % BITS_PER_UNIT) == 0)
+	  {
+	    rtx base_addr;
+
+	    if (width == 32)
+              {
+		base_addr = adjust_address (operands[1], SImode,
+					    bitpos / BITS_PER_UNIT);
+		emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
+              }
+	    else
+              {
+		rtx dest = operands[0];
+		rtx tmp = gen_reg_rtx (SImode);
+
+		/* We may get a paradoxical subreg here.  Strip it off.  */
+		if (GET_CODE (dest) == SUBREG
+		    && GET_MODE (dest) == SImode
+		    && GET_MODE (SUBREG_REG (dest)) == HImode)
+		  dest = SUBREG_REG (dest);
+
+		if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
+		  FAIL;
+
+		base_addr = adjust_address (operands[1], HImode,
+					    bitpos / BITS_PER_UNIT);
+		emit_insn (gen_unaligned_loadhiu (tmp, base_addr));
+		emit_move_insn (gen_lowpart (SImode, dest), tmp);
+	      }
+	    DONE;
+	  }
+	else if (s_register_operand (operands[1], GET_MODE (operands[1])))
+	  {
+	    emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
+				     operands[3]));
+	    DONE;
+	  }
+	else
+	  FAIL;
       }
+    
+    if (!s_register_operand (operands[1], GET_MODE (operands[1])))
+      FAIL;
 
     operands[3] = GEN_INT (rshift);
     
@@ -3635,7 +3711,103 @@
   }"
 )
 
-(define_insn "extv"
+(define_expand "extv"
+  [(set (match_operand 0 "s_register_operand" "")
+	(sign_extract (match_operand 1 "nonimmediate_operand" "")
+		      (match_operand 2 "const_int_operand" "")
+		      (match_operand 3 "const_int_operand" "")))]
+  "arm_arch_thumb2"
+{
+  HOST_WIDE_INT width = INTVAL (operands[2]);
+  HOST_WIDE_INT bitpos = INTVAL (operands[3]);
+
+  if (unaligned_access && MEM_P (operands[1]) && (width == 16 || width == 32)
+      && (bitpos % BITS_PER_UNIT) == 0)
+    {
+      rtx base_addr;
+      
+      if (width == 32)
+        {
+	  base_addr = adjust_address (operands[1], SImode,
+				      bitpos / BITS_PER_UNIT);
+	  emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
+        }
+      else
+        {
+	  rtx dest = operands[0];
+	  rtx tmp = gen_reg_rtx (SImode);
+	  
+	  /* We may get a paradoxical subreg here.  Strip it off.  */
+	  if (GET_CODE (dest) == SUBREG
+	      && GET_MODE (dest) == SImode
+	      && GET_MODE (SUBREG_REG (dest)) == HImode)
+	    dest = SUBREG_REG (dest);
+	  
+	  if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
+	    FAIL;
+	  
+	  base_addr = adjust_address (operands[1], HImode,
+				      bitpos / BITS_PER_UNIT);
+	  emit_insn (gen_unaligned_loadhis (tmp, base_addr));
+	  emit_move_insn (gen_lowpart (SImode, dest), tmp);
+	}
+
+      DONE;
+    }
+  else if (s_register_operand (operands[1], GET_MODE (operands[1])))
+    DONE;
+  else
+    FAIL;
+})
+
+; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
+
+(define_insn "unaligned_loadsi"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "memory_operand" "m")]
+		   UNSPEC_UNALIGNED_LOAD))]
+  "unaligned_access"
+  "ldr%?\t%0, %1\t@ unaligned"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "load1")])
+
+(define_insn "unaligned_loadhis"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(sign_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "m")]
+				   UNSPEC_UNALIGNED_LOAD)))]
+  "unaligned_access"
+  "ldr%(sh%)\t%0, %1\t@ unaligned"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "load_byte")])
+
+(define_insn "unaligned_loadhiu"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(zero_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "m")]
+				   UNSPEC_UNALIGNED_LOAD)))]
+  "unaligned_access"
+  "ldr%(h%)\t%0, %1\t@ unaligned"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "load_byte")])
+
+(define_insn "unaligned_storesi"
+  [(set (match_operand:SI 0 "memory_operand" "=m")
+	(unspec:SI [(match_operand:SI 1 "s_register_operand" "r")]
+		   UNSPEC_UNALIGNED_STORE))]
+  "unaligned_access"
+  "str%?\t%1, %0\t@ unaligned"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "store1")])
+
+(define_insn "unaligned_storehi"
+  [(set (match_operand:HI 0 "memory_operand" "=m")
+	(unspec:HI [(match_operand:HI 1 "s_register_operand" "r")]
+		   UNSPEC_UNALIGNED_STORE))]
+  "unaligned_access"
+  "str%(h%)\t%1, %0\t@ unaligned"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "store1")])
+
+(define_insn "*extv_reg"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
                          (match_operand:SI 2 "const_int_operand" "M")
 
=== modified file 'gcc/config/arm/arm.opt'
--- gcc/config/arm/arm.opt	2010-08-05 15:20:54 +0000
+++ gcc/config/arm/arm.opt	2011-04-13 13:28:18 +0000
@@ -173,3 +173,7 @@
 Target Report Var(fix_cm3_ldrd) Init(2)
 Avoid overlapping destination and address registers on LDRD instructions
 that may trigger Cortex-M3 errata.
+
+munaligned-access
+Target Report Var(unaligned_access) Init(2)
+Enable unaligned word and halfword accesses to packed data.
 
=== modified file 'gcc/config/arm/unwind-arm.c'
--- gcc/config/arm/unwind-arm.c	2010-08-12 12:39:35 +0000
+++ gcc/config/arm/unwind-arm.c	2011-04-13 13:28:18 +0000
@@ -32,13 +32,18 @@
 typedef unsigned char bool;
 
 typedef struct _ZSt9type_info type_info; /* This names C++ type_info type */
+enum __cxa_type_match_result
+  {
+    ctm_failed = 0,
+    ctm_succeeded = 1,
+    ctm_succeeded_with_ptr_to_base = 2
+  };
 
 void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp);
 bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp);
-bool __attribute__((weak)) __cxa_type_match(_Unwind_Control_Block *ucbp,
-					    const type_info *rttip,
-					    bool is_reference,
-					    void **matched_object);
+enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match
+  (_Unwind_Control_Block *ucbp, const type_info *rttip,
+   bool is_reference, void **matched_object);
 
 _Unwind_Ptr __attribute__((weak))
 __gnu_Unwind_Find_exidx (_Unwind_Ptr, int *);
@@ -1107,6 +1112,7 @@
 		      _uw rtti;
 		      bool is_reference = (data[0] & uint32_highbit) != 0;
 		      void *matched;
+		      enum __cxa_type_match_result match_type;
 
 		      /* Check for no-throw areas.  */
 		      if (data[1] == (_uw) -2)
@@ -1118,17 +1124,31 @@
 			{
 			  /* Match a catch specification.  */
 			  rtti = _Unwind_decode_target2 ((_uw) &data[1]);
-			  if (!__cxa_type_match (ucbp, (type_info *) rtti,
-						 is_reference,
-						 &matched))
-			    matched = (void *)0;
+			  match_type = __cxa_type_match (ucbp,
+							 (type_info *) rtti,
+							 is_reference,
+							 &matched);
 			}
+		      else
+			match_type = ctm_succeeded;
 
-		      if (matched)
+		      if (match_type)
 			{
 			  ucbp->barrier_cache.sp =
 			    _Unwind_GetGR (context, R_SP);
-			  ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
+			  // ctm_succeeded_with_ptr_to_base really
+			  // means _c_t_m indirected the pointer
+			  // object.  We have to reconstruct the
+			  // additional pointer layer by using a temporary.
+			  if (match_type == ctm_succeeded_with_ptr_to_base)
+			    {
+			      ucbp->barrier_cache.bitpattern[2]
+				= (_uw) matched;
+			      ucbp->barrier_cache.bitpattern[0]
+				= (_uw) &ucbp->barrier_cache.bitpattern[2];
+			    }
+			  else
+			    ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
 			  ucbp->barrier_cache.bitpattern[1] = (_uw) data;
 			  return _URC_HANDLER_FOUND;
 			}
 
=== modified file 'gcc/expmed.c'
--- gcc/expmed.c	2011-01-18 19:06:14 +0000
+++ gcc/expmed.c	2011-04-13 13:28:18 +0000
@@ -720,7 +720,7 @@
       /* On big-endian machines, we count bits from the most significant.
 	 If the bit field insn does not, we must invert.  */
 
-      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN && !MEM_P (xop0))
 	xbitpos = unit - bitsize - xbitpos;
 
       /* We have been counting XBITPOS within UNIT.
@@ -1564,7 +1564,7 @@
 
       /* On big-endian machines, we count bits from the most significant.
 	 If the bit field insn does not, we must invert.  */
-      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
+      if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN && !MEM_P (xop0))
 	xbitpos = unit - bitsize - xbitpos;
 
       /* Now convert from counting within UNIT to counting in EXT_MODE.  */
 
=== modified file 'gcc/final.c'
--- gcc/final.c	2011-02-08 10:51:58 +0000
+++ gcc/final.c	2011-04-13 13:28:18 +0000
@@ -2751,6 +2751,12 @@
   if (filename == NULL)
     return false;
 
+#ifdef HAVE_ATTR_length
+  /* Prevent duplicate line markers at the same location.  */
+  if (get_attr_length (insn) == 0)
+    return false;
+#endif
+
   if (force_source_line
       || filename != last_filename
       || last_linenum != linenum)
 
=== modified file 'gcc/ifcvt.c'
--- gcc/ifcvt.c	2011-02-08 12:07:29 +0000
+++ gcc/ifcvt.c	2011-04-13 13:28:18 +0000
@@ -311,6 +311,10 @@
 
   for (insn = start; ; insn = NEXT_INSN (insn))
     {
+      /* dwarf2out can't cope with conditional prologues.  */
+      if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
+	return FALSE;
+
       if (NOTE_P (insn) || DEBUG_INSN_P (insn))
 	goto insn_done;
 
 
=== modified file 'gcc/ipa-pure-const.c'
--- gcc/ipa-pure-const.c	2010-11-15 22:27:24 +0000
+++ gcc/ipa-pure-const.c	2011-04-13 13:28:18 +0000
@@ -422,7 +422,14 @@
       if (dump_file)
 	fprintf (dump_file, "    Volatile stmt is not const/pure\n");
     }
-
+  
+  if (gimple_has_volatile_ops (stmt))
+    {
+      local->pure_const_state = IPA_NEITHER;
+      if (dump_file)
+	fprintf (dump_file, "    Volatile stmt is not const/pure\n");
+    }
+  
   /* Look for loads and stores.  */
   walk_stmt_load_store_ops (stmt, local, check_load, check_store);
 
 
=== added file 'gcc/testsuite/gcc.c-torture/compile/20110322-1.c'
--- gcc/testsuite/gcc.c-torture/compile/20110322-1.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.c-torture/compile/20110322-1.c	2011-04-13 13:28:18 +0000
@@ -0,0 +1,22 @@
+void asn1_length_der (unsigned long int len, unsigned char *ans, int *ans_len)
+{
+    int k;
+    unsigned char temp[4];
+    if (len < 128) {
+	if (ans != ((void *) 0))
+	    ans[0] = (unsigned char) len;
+	*ans_len = 1;
+    } else {
+	k = 0;
+	while (len) {
+	    temp[k++] = len & 0xFF;
+	    len = len >> 8;
+	}
+	*ans_len = k + 1;
+	if (ans != ((void *) 0)) {
+	    ans[0] = ((unsigned char) k & 0x7F) + 128;
+	    while (k--)
+		ans[*ans_len - 1 - k] = temp[k];
+	}
+    }
+}
 
=== added file 'gcc/testsuite/gcc.dg/pr47763.c'
--- gcc/testsuite/gcc.dg/pr47763.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.dg/pr47763.c	2011-04-13 13:28:18 +0000
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -funroll-loops -fdump-rtl-web" } */
+
+foo()
+{
+}
+
+/* { dg-final { scan-rtl-dump-not "Web oldreg" "web" } } */
+/* { dg-final { cleanup-rtl-dump "web" } } */
 
=== modified file 'gcc/testsuite/lib/target-supports.exp'
--- gcc/testsuite/lib/target-supports.exp	2011-02-22 11:38:56 +0000
+++ gcc/testsuite/lib/target-supports.exp	2011-04-13 13:28:18 +0000
@@ -2722,8 +2722,9 @@
     if [info exists et_vector_alignment_reachable_saved] {
         verbose "check_effective_target_vector_alignment_reachable: using cached result" 2
     } else {
-        if { [check_effective_target_vect_aligned_arrays]
-             || [check_effective_target_natural_alignment_32] } {
+        if { ([check_effective_target_vect_aligned_arrays]
+              || [check_effective_target_natural_alignment_32])
+	     && !([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
             set et_vector_alignment_reachable_saved 1
         } else {
             set et_vector_alignment_reachable_saved 0
 
=== modified file 'gcc/tree-ssa-copyrename.c'
--- gcc/tree-ssa-copyrename.c	2011-01-20 10:36:29 +0000
+++ gcc/tree-ssa-copyrename.c	2011-04-13 13:28:18 +0000
@@ -225,6 +225,18 @@
       ign2 = false;
     }
 
+  /* Don't coalesce if the new chosen root variable would be read-only.
+     If both ign1 && ign2, then the root var of the larger partition
+     wins, so reject in that case if any of the root vars is TREE_READONLY.
+     Otherwise reject only if the root var, on which replace_ssa_name_symbol
+     will be called below, is readonly.  */
+  if ((TREE_READONLY (root1) && ign2) || (TREE_READONLY (root2) && ign1))
+    {
+      if (debug)
+	fprintf (debug, " : Readonly variable.  No coalesce.\n");
+      return false;
+    }
+
   /* Don't coalesce if the two variables aren't type compatible .  */
   if (!types_compatible_p (TREE_TYPE (root1), TREE_TYPE (root2))
       /* There is a disconnect between the middle-end type-system and
 
=== modified file 'gcc/web.c'
--- gcc/web.c	2010-01-26 16:27:34 +0000
+++ gcc/web.c	2011-04-13 13:28:18 +0000
@@ -350,7 +350,17 @@
     FOR_BB_INSNS (bb, insn)
     {
       unsigned int uid = INSN_UID (insn);
-      if (NONDEBUG_INSN_P (insn))
+
+      if (NONDEBUG_INSN_P (insn)
+	  /* Ignore naked clobber.  For example, reg 134 in the second insn
+	     of the following sequence will not be replaced.
+
+	       (insn (clobber (reg:SI 134)))
+
+	       (insn (set (reg:SI 0 r0) (reg:SI 134)))
+
+	     Thus the later passes can optimize them away.  */
+	  && GET_CODE (PATTERN (insn)) != CLOBBER)
 	{
 	  df_ref *use_rec;
 	  df_ref *def_rec;
 
=== modified file 'libstdc++-v3/libsupc++/eh_arm.cc'
--- libstdc++-v3/libsupc++/eh_arm.cc	2009-04-09 14:00:19 +0000
+++ libstdc++-v3/libsupc++/eh_arm.cc	2011-04-13 13:28:18 +0000
@@ -30,10 +30,11 @@
 using namespace __cxxabiv1;
 
 
-// Given the thrown type THROW_TYPE, pointer to a variable containing a
-// pointer to the exception object THROWN_PTR_P and a type CATCH_TYPE to
-// compare against, return whether or not there is a match and if so,
-// update *THROWN_PTR_P.
+// Given the thrown type THROW_TYPE, exception object UE_HEADER and a
+// type CATCH_TYPE to compare against, return whether or not there is
+// a match and if so, update *THROWN_PTR_P to point to either the
+// type-matched object, or in the case of a pointer type, the object
+// pointed to by the pointer.
 
 extern "C" __cxa_type_match_result
 __cxa_type_match(_Unwind_Exception* ue_header,
@@ -41,51 +42,51 @@
 		 bool is_reference __attribute__((__unused__)),
 		 void** thrown_ptr_p)
 {
-  bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class);
-  bool foreign_exception = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
-  bool dependent_exception =
-    __is_dependent_exception(ue_header->exception_class);
+  bool forced_unwind
+    = __is_gxx_forced_unwind_class(ue_header->exception_class);
+  bool foreign_exception
+    = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
+  bool dependent_exception
+    = __is_dependent_exception(ue_header->exception_class);
   __cxa_exception* xh = __get_exception_header_from_ue(ue_header);
   __cxa_dependent_exception *dx = __get_dependent_exception_from_ue(ue_header);
   const std::type_info* throw_type;
+  void *thrown_ptr = 0;
 
   if (forced_unwind)
     throw_type = &typeid(abi::__forced_unwind);
   else if (foreign_exception)
     throw_type = &typeid(abi::__foreign_exception);
-  else if (dependent_exception)
-    throw_type = __get_exception_header_from_obj
-      (dx->primaryException)->exceptionType;
   else
-    throw_type = xh->exceptionType;
-
-  void* thrown_ptr = *thrown_ptr_p;
+    {
+      if (dependent_exception)
+	xh = __get_exception_header_from_obj (dx->primaryException);
+      throw_type = xh->exceptionType;
+      // We used to require the caller set the target of thrown_ptr_p,
+      // but that's incorrect -- the EHABI makes no such requirement
+      // -- and not all callers will set it.  Fortunately callers that
+      // do initialize will always pass us the value we calculate
+      // here, so there's no backwards compatibility problem.
+      thrown_ptr = __get_object_from_ue (ue_header);
+    }
+  
+  __cxa_type_match_result result = ctm_succeeded;
 
   // Pointer types need to adjust the actual pointer, not
   // the pointer to pointer that is the exception object.
   // This also has the effect of passing pointer types
   // "by value" through the __cxa_begin_catch return value.
   if (throw_type->__is_pointer_p())
-    thrown_ptr = *(void**) thrown_ptr;
+    {
+      thrown_ptr = *(void**) thrown_ptr;
+      // We need to indicate the indirection to our caller.
+      result = ctm_succeeded_with_ptr_to_base;
+    }
 
   if (catch_type->__do_catch(throw_type, &thrown_ptr, 1))
     {
       *thrown_ptr_p = thrown_ptr;
-
-      if (typeid(*catch_type) == typeid (typeid(void*)))
-	{
-	  const __pointer_type_info *catch_pointer_type =
-	    static_cast<const __pointer_type_info *> (catch_type);
-	  const __pointer_type_info *throw_pointer_type =
-	    static_cast<const __pointer_type_info *> (throw_type);
-
-	  if (typeid (*catch_pointer_type->__pointee) != typeid (void)
-	      && (*catch_pointer_type->__pointee != 
-		  *throw_pointer_type->__pointee))
-	    return ctm_succeeded_with_ptr_to_base;
-	}
-
-      return ctm_succeeded;
+      return result;
     }
 
   return ctm_failed;