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Branches

Name Last Modified Last Commit
ops/dwil/tmp_bisect_3 2021-08-05 22:46:27 UTC
CYAN_8R: temporary fix for initialization failing

Author: Doug W
Author Date: 2021-08-05 16:48:24 UTC

CYAN_8R: temporary fix for initialization failing

When initializing the device, uhd will try to use tx hooks that
shouldn't exist for 8r. The temporary fix is to have the number of
transmit and receive channel match. The long term solution is to make
the part of the code that tries to access the tx stuff not run number of
tx channels = 0

ops/dwil/tmp_bisect_2 2021-08-05 22:44:11 UTC
CYAN_8R: temporary fix for initialization failing

Author: Doug W
Author Date: 2021-08-05 16:48:24 UTC

CYAN_8R: temporary fix for initialization failing

When initializing the device, uhd will try to use tx hooks that
shouldn't exist for 8r. The temporary fix is to have the number of
transmit and receive channel match. The long term solution is to make
the part of the code that tries to access the tx stuff not run number of
tx channels = 0

ops/dwil/tmp_bisect_1 2021-08-05 22:40:04 UTC
DEBUG: figuring out where link_addr missing appears

Author: Doug W
Author Date: 2021-08-05 22:40:04 UTC

DEBUG: figuring out where link_addr missing appears

ops/dwil/cyfcr4r4t_6 2021-08-05 19:11:06 UTC
RX_STREAM_INIT: improved help message

Author: Doug W
Author Date: 2021-08-05 19:10:32 UTC

RX_STREAM_INIT: improved help message

ops/dwil/tmp_3 2021-08-05 18:12:26 UTC
RX_STREAM_INIT: changed help message to avoid error

Author: Doug W
Author Date: 2021-08-05 18:08:19 UTC

RX_STREAM_INIT: changed help message to avoid error

THe usr must specify a exec file starting with ./ ~/, or / for the exec,
just stating the file won't work

ops/dwil/tmp_2 2021-08-05 18:08:19 UTC
RX_STREAM_INIT: changed help message to avoid error

Author: Doug W
Author Date: 2021-08-05 18:08:19 UTC

RX_STREAM_INIT: changed help message to avoid error

THe usr must specify a exec file starting with ./ ~/, or / for the exec,
just stating the file won't work

ops/dwil/tmp_1 2021-08-05 16:19:01 UTC
DEBUG: tracing where program failed

Author: Doug W
Author Date: 2021-08-05 16:19:01 UTC

DEBUG: tracing where program failed

ops/dwil/cyfcr_4r4t_5 2021-08-04 21:54:05 UTC
CYAN_4R4T: fixing mapping for rf gain

Author: Doug W
Author Date: 2021-08-04 21:54:05 UTC

CYAN_4R4T: fixing mapping for rf gain

ops/dwil/8rf4r4t_4 2021-08-04 18:59:56 UTC
CYAN_4R4T: removed gain setting logic from multi_usrp

Author: Doug W
Author Date: 2021-08-04 18:59:56 UTC

CYAN_4R4T: removed gain setting logic from multi_usrp

Note this will affect every that uses multi_usrp, not just this unit
Meld the previous commits into this while cleaning

ops/dwil/port-cyan/8rf4r4t_5 2021-08-04 16:14:39 UTC
CYAN_4R4T: removed commented out code that is no longer useful

Author: Doug W
Author Date: 2021-08-04 16:14:39 UTC

CYAN_4R4T: removed commented out code that is no longer useful

ops/dwil/8rf4r4t_3 2021-07-27 21:31:24 UTC
RX_STREAM_INIT: troubleshooting

Author: Doug W
Author Date: 2021-07-27 21:31:24 UTC

RX_STREAM_INIT: troubleshooting

ops/dwil/8rf4r4t_2 2021-07-27 19:29:07 UTC
RX_STREAM_INIT: implemented post exec

Author: Doug W
Author Date: 2021-07-27 19:29:07 UTC

RX_STREAM_INIT: implemented post exec

ops/dwil/8rf4r4t 2021-07-26 18:50:54 UTC
RX_STREAM_INIT: renames setup_time to secs (start delay)

Author: Doug W
Author Date: 2021-07-26 18:50:54 UTC

RX_STREAM_INIT: renames setup_time to secs (start delay)

ops/dwil/cyfcr_4r4t_3 2021-07-23 18:33:06 UTC
CYAN_4R4T: removed debug messages

Author: Doug W
Author Date: 2021-07-23 18:33:06 UTC

CYAN_4R4T: removed debug messages

ops/dwil/cyfcr_4r4t_2 2021-07-23 17:38:29 UTC
DBUG: adding debug messages

Author: Doug W
Author Date: 2021-07-23 17:38:29 UTC

DBUG: adding debug messages

ops/dwil/jesd_trouble 2021-07-21 22:21:28 UTC
CYAN_4R4T: changed set time to cur time

Author: Doug W
Author Date: 2021-07-21 22:21:28 UTC

CYAN_4R4T: changed set time to cur time

ops/dwil/cyfcr_4r4t_1 2021-07-19 21:00:57 UTC
EXAMPLE: fixing help message, squash this

Author: Doug W
Author Date: 2021-07-19 21:00:57 UTC

EXAMPLE: fixing help message, squash this

ops/dwil/cyfcr_4r4t 2021-07-16 18:25:05 UTC
CYAN_4R4T: improved program flow

Author: Doug W
Author Date: 2021-07-16 18:25:05 UTC

CYAN_4R4T: improved program flow

ops/dwil/timeout_fixing 2021-07-06 18:53:36 UTC
DEBUG: removed the crash used to test where number of samples sent was tracked

Author: Doug W
Author Date: 2021-07-06 18:53:36 UTC

DEBUG: removed the crash used to test where number of samples sent was tracked

ops/dwil/port-cyan4r4t 2021-06-25 16:46:21 UTC
CYAN_4R4T: stopped 4R4T from turning off at the end of runs

Author: Doug W
Author Date: 2021-06-25 16:46:21 UTC

CYAN_4R4T: stopped 4R4T from turning off at the end of runs

ops/dwil/pc8r-vvv 2021-06-23 20:34:24 UTC
EXAMPLES: made test_set_get_path_value not require synchronization

Author: Doug W
Author Date: 2021-06-23 20:34:24 UTC

EXAMPLES: made test_set_get_path_value not require synchronization

ops/dwil/examining 2021-06-22 17:32:42 UTC
DEBUG: abort to check what the register values are

Author: Doug W
Author Date: 2021-06-22 17:32:42 UTC

DEBUG: abort to check what the register values are

ops/dwil/port-cyan8t 2021-06-21 15:46:28 UTC
CYAN_8t: partially fixed the spec description

Author: Doug W
Author Date: 2021-06-21 15:46:28 UTC

CYAN_8t: partially fixed the spec description

ops/dwil/port-cyan8r-32t-troubleshooting 2021-06-17 21:10:20 UTC
DEBUG: print messages

Author: Doug W
Author Date: 2021-06-17 21:10:20 UTC

DEBUG: print messages

ops/dwil/port-cyan8r-32t 2021-06-16 19:48:24 UTC
CYAN_8R: Fixing clocking and DSP frequencies.

Author: Doug Wilson
Author Date: 2021-06-16 16:24:47 UTC

CYAN_8R: Fixing clocking and DSP frequencies.

ops/dwil/port-cyan8r 2021-06-16 16:24:47 UTC
CYAN_8R: Fixing clocking and DSP frequencies.

Author: Jade (testbench)
Author Date: 2021-06-16 16:24:47 UTC

CYAN_8R: Fixing clocking and DSP frequencies.

ops/dwil/port-cyan32t 2021-06-11 18:51:16 UTC
Cyan_p1hdr32t: added it to tests

Author: Jade (testbench)
Author Date: 2021-06-11 18:51:16 UTC

Cyan_p1hdr32t: added it to tests
The tests have not been verified to be working

rdb-maser-porting-cyan_8t 2021-05-28 15:00:11 UTC
UHD: More printfs

Author: Renaud Di Bernardo
Author Date: 2021-05-28 15:00:11 UTC

UHD: More printfs

uhd-rdb-master-testing 2021-05-28 15:00:11 UTC
UHD: More printfs

Author: Renaud Di Bernardo
Author Date: 2021-05-28 15:00:11 UTC

UHD: More printfs

ops/jpol/cyan-test 2021-03-02 19:49:24 UTC
CYAN_P1HDR32T: update name of the device

Author: John Polak
Author Date: 2021-03-02 19:49:24 UTC

CYAN_P1HDR32T: update name of the device

ops/ven/issue-6589/phase-coherency 2021-01-06 17:36:20 UTC
fix typo

Author: Vikram Venkataranan
Author Date: 2021-01-06 17:36:20 UTC

fix typo

ops/ven/bug6616/versioning-script 2020-12-11 16:35:39 UTC
fix field names

Author: Vikram Venkataramanan
Author Date: 2020-12-11 16:35:39 UTC

fix field names

test/single-uhd 2020-10-29 21:30:51 UTC
EXAMPLES: add channel mapping note to tx_waveforms for cyan

Author: John Polak
Author Date: 2020-10-29 21:30:51 UTC

EXAMPLES: add channel mapping note to tx_waveforms for cyan

master-rtm1-testing 2020-09-08 16:35:13 UTC
BUFFERSIZE: Fixed buffer size to use DDR.

Author: Renaud Di Bernardo
Author Date: 2020-09-08 16:35:13 UTC

BUFFERSIZE: Fixed buffer size to use DDR.

Changed the buffer size to it's actual size, and multiplied the level reported
by FPGA by 32 so it actually indicated the sample level.

test/vvv/su-tng 2020-09-02 18:44:39 UTC
tests: cyan_64t: cyan_64t tests passing

Author: Christopher Friedt
Author Date: 2020-09-02 18:44:39 UTC

tests: cyan_64t: cyan_64t tests passing

cyan_64t_test passing. With this, crimson_tng_test, and cyan_16t_test,
we can guarantee (to the extent that tests are covering) that there will
be no regressions.

Fixes #14

Signed-off-by: Christopher Friedt <chris.f@pervices.com>

test/ci 2020-08-27 02:26:31 UTC
crimson_tng: fix crash in when mboard_eeprom["serial"] property does not exist

Author: Christopher Friedt
Author Date: 2020-08-26 21:51:36 UTC

crimson_tng: fix crash in when mboard_eeprom["serial"] property does not exist

This change populates the mboard_eeprom["serial"] property and therefore
prevents multi_usrp->get_rx_info() from throwing a runtime error when the
property does not exist.

Fixes #9

Signed-off-by: Christopher Friedt <chris.f@pervices.com>

cfriedtpv-cyan-16t 2020-08-18 14:43:02 UTC
cyan_16t: platform is stable

Author: Christopher Friedt
Author Date: 2020-08-18 14:43:02 UTC

cyan_16t: platform is stable

Previously, the master branch was being used as a product branch for crimson_tng.
ops/vvv/master-testing was being used as a product branch for cyan_16t.

Since we do not intend to use product branches and would like master to support
all of our products, we would like to convert this to a feature branch and
then merge with master.

The same will be done for master-testing, which was being used as a
product branch for cyan_64t. The master-testing branch should nominally be used
as staging (i.e. for 'soak' testing), and that will be corrected in a
subsequent PR, as cyan_64t is now stable.

Signed-off-by: Christopher Friedt <chris.f@pervices.com>

cfriedtpv-cyan-64t 2020-08-14 15:50:01 UTC
Merge branch 'master' into cyan-64t

Author: Christopher Friedt
Author Date: 2020-08-14 15:50:01 UTC

Merge branch 'master' into cyan-64t

ops/abav/master-testing 2020-04-21 00:45:44 UTC
UHD: define a parameter for flow control set point

Author: Amir Ghanbari Bavarsad
Author Date: 2020-04-21 00:45:44 UTC

UHD: define a parameter for flow control set point

ops/vvv/master-testing 2020-04-13 20:24:43 UTC
Revert "TATE: Add aggregate SampRate consideration"

Author: Amir Ghanbari Bavarsad
Author Date: 2020-04-13 20:24:43 UTC

Revert "TATE: Add aggregate SampRate consideration"

Mistakenly committed to the wrong branch
This reverts commit abccde8202c4cd20a01401b16e9985e183cf46a2.
This reverts commit 915ffad94bdba344946673951dbfbb77a22dcaa9.

test/fix-freq-dsp 2020-03-11 22:24:36 UTC
UHD: This addresses an incorrect doubling of freq.

Author: SFEN
Author Date: 2020-03-11 22:24:36 UTC

UHD: This addresses an incorrect doubling of freq.

ops/vvv/test-fulltx-fc 2020-03-11 16:29:09 UTC
Merge branch 'master' of github.com:/pervices/uhd into ops/vvv/test-fulltx-fc

Author: Victor W
Author Date: 2020-03-11 16:29:09 UTC

Merge branch 'master' of github.com:/pervices/uhd into ops/vvv/test-fulltx-fc

master-rtm1 2020-01-21 16:55:47 UTC
TATE VAUNT: Critical BugFix send packet size

Author: Amir Ghanbari Bavarsad
Author Date: 2020-01-21 16:55:47 UTC

TATE VAUNT: Critical BugFix send packet size

Prior to this fix, the size of buffers were calculated incorrectly,
which caused the sendmmsg to pick up random bytes and add them to the
end of the buffer, causing distortions/images in the final signal.

test/master-testing-onlySFPa 2019-08-19 18:53:42 UTC
TEST: Use only qSFP+ A for all channels.

Author: Victor W
Author Date: 2019-08-19 18:53:42 UTC

TEST: Use only qSFP+ A for all channels.

master-fulltx 2019-08-14 19:03:20 UTC
UHD: Add additional TATE Tx end points.

Author: Victor W
Author Date: 2019-08-14 19:03:20 UTC

UHD: Add additional TATE Tx end points.

ops/gshe/ci 2019-06-27 20:24:36 UTC
UHD CI: Added CI script for building UHD on the CI host computer

Author: Gabe Sher
Author Date: 2019-06-27 20:24:17 UTC

UHD CI: Added CI script for building UHD on the CI host computer

rb/full-tx 2018-10-06 18:25:28 UTC
PIDC: Removing debug flag.

Author: Victor W
Author Date: 2018-10-06 18:25:28 UTC

PIDC: Removing debug flag.

test/port 2018-08-20 20:45:32 UTC
Merge branch 'master' of github.com:/pervices/uhd into test/port

Author: Victor W
Author Date: 2018-08-20 20:45:32 UTC

Merge branch 'master' of github.com:/pervices/uhd into test/port

dev/dmcl 2018-05-03 17:27:09 UTC
Dont send end of packet packets

Author: Daniel McLean
Author Date: 2018-05-03 17:27:09 UTC

Dont send end of packet packets

master-old 2018-03-13 16:06:19 UTC
Merge pull request #109 from cfriedtpv/fix-bandwidth-issue

Author: DanielMcLean
Author Date: 2018-03-13 16:06:19 UTC

Merge pull request #109 from cfriedtpv/fix-bandwidth-issue

fix bandwidth issue

legacy/v1.6 2018-03-13 16:06:19 UTC
Merge pull request #109 from cfriedtpv/fix-bandwidth-issue

Author: DanielMcLean
Author Date: 2018-03-13 16:06:19 UTC

Merge pull request #109 from cfriedtpv/fix-bandwidth-issue

fix bandwidth issue

test/full-tx-rate 2017-11-21 17:29:23 UTC
Merge branch 'master' of github.com:/pervices/uhd into test/full-tx-rate

Author: Victor W
Author Date: 2017-11-21 17:29:23 UTC

Merge branch 'master' of github.com:/pervices/uhd into test/full-tx-rate

test/grc-loopback 2017-10-30 16:31:24 UTC
Send will now properly send 0 sample packet for start of burst if asked too

Author: DanielMcLean
Author Date: 2017-10-30 16:31:24 UTC

Send will now properly send 0 sample packet for start of burst if asked too

kb/4201/Choppy-TX-send 2017-10-20 14:06:34 UTC
Further fixing instances where we only look at has_time_stamp. Fixing vita he...

Author: Daniel McLean
Author Date: 2017-10-20 14:06:34 UTC

Further fixing instances where we only look at has_time_stamp. Fixing vita header

test/backpressure 2017-10-19 18:16:33 UTC
FC nonlinear print out bl, sr, dt

Author: Daniel McLean
Author Date: 2017-10-19 18:16:33 UTC

 FC nonlinear print out bl, sr, dt

test/10g-set-time 2017-10-19 14:31:33 UTC
Setting time now adjusts expected offset so PID doesnt go crazy

Author: DanielMcLean
Author Date: 2017-10-19 14:31:33 UTC

Setting time now adjusts expected offset so PID doesnt go crazy

test/tx-send 2017-08-31 14:20:35 UTC
Merge pull request #78 from cfriedtpv/kb/4070/uhd-ensure-only-one-buffer-mana...

Author: DanielMcLean
Author Date: 2017-08-31 14:20:35 UTC

Merge pull request #78 from cfriedtpv/kb/4070/uhd-ensure-only-one-buffer-management-thread-is-running-per-process

Kb/4070/uhd ensure only one buffer management thread is running per process

ops/dwil/old_compiling/rev130 2017-08-22 20:25:23 UTC
UHD: Now correctl using offset and doing trylock for fifo updatE

Author: Daniel McLean
Author Date: 2017-08-22 20:25:23 UTC

UHD: Now correctl using offset and doing trylock for fifo updatE

test/rx-burst 2017-08-22 20:25:23 UTC
UHD: Now correctl using offset and doing trylock for fifo updatE

Author: Daniel McLean
Author Date: 2017-08-22 20:25:23 UTC

UHD: Now correctl using offset and doing trylock for fifo updatE

test/tx-send-debug 2017-06-22 15:04:00 UTC
Adding debug messages

Author: Daniel McLean
Author Date: 2017-06-22 15:04:00 UTC

Adding debug messages

cfriedtpv-kb/4022/uhd-use-pulse-train-for-flow-control 2017-06-15 22:23:29 UTC
Merge branch 'kb/4022/uhd-use-pulse-train-for-flow-control' of https://github...

Author: Victor W
Author Date: 2017-06-15 22:23:29 UTC

Merge branch 'kb/4022/uhd-use-pulse-train-for-flow-control' of https://github.com/cfriedtpv/uhd into cfriedtpv-kb/4022/uhd-use-pulse-train-for-flow-control

test/tx-send-vvv 2017-05-31 17:59:37 UTC
Merge pull request #52 from cfriedtpv/kb/3985/uhd-bug-reduce-delays-in-send

Author: DanielMcLean
Author Date: 2017-05-31 17:59:37 UTC

Merge pull request #52 from cfriedtpv/kb/3985/uhd-bug-reduce-delays-in-send

Kb/3985/uhd bug reduce delays in send

test/flowcontrol 2017-05-19 13:02:12 UTC
Merge pull request #42 from cfriedtpv/kb/3983/uhd-bug-set-sample-rate

Author: DanielMcLean
Author Date: 2017-05-19 13:02:12 UTC

Merge pull request #42 from cfriedtpv/kb/3983/uhd-bug-set-sample-rate

Kb/3983/uhd fix bug in set sample rate

master-classic-testing 2016-10-18 16:09:46 UTC
Vita Changes for master-classic-testing FPGA Image

Author: Namburi Raghuram
Author Date: 2016-10-18 16:09:46 UTC

Vita Changes for master-classic-testing FPGA Image

ops-ramfc 2016-10-17 17:14:58 UTC
Updating Crimson TNG device root name to differente from classic

Author: Namburi Raghuram
Author Date: 2016-10-17 17:14:58 UTC

Updating Crimson TNG device root name to differente from classic

Necessity for OpenBTS

master-rtm4-testing 2016-10-17 17:14:58 UTC
Updating Crimson TNG device root name to differente from classic

Author: Namburi Raghuram
Author Date: 2016-10-17 17:14:58 UTC

Updating Crimson TNG device root name to differente from classic

Necessity for OpenBTS

ops-ram 2016-10-14 19:39:03 UTC
Merge pull request #2 from pervices/ops-ram

Author: vrnambur
Author Date: 2016-10-14 19:39:03 UTC

Merge pull request #2 from pervices/ops-ram

merging into pervices/uhd, master branch

master-classic 2016-10-14 19:39:03 UTC
Merge pull request #2 from pervices/ops-ram

Author: vrnambur
Author Date: 2016-10-14 19:39:03 UTC

Merge pull request #2 from pervices/ops-ram

merging into pervices/uhd, master branch

master-classic-vita 2016-10-05 16:45:29 UTC
VITA bytes swapped for new FPGA image for crimson-classic

Author: Cole Development Machine
Author Date: 2016-10-05 16:45:29 UTC

VITA bytes swapped for new FPGA image for crimson-classic

ops-ramobts 2016-09-29 16:23:51 UTC
OBTS: Latest openBTS with no flow control and disable stream hooks

Author: Cole Development Machine
Author Date: 2016-09-29 16:23:51 UTC

OBTS: Latest openBTS with no flow control and disable stream hooks

Used with master branch OpenBTS.
Slow Messages, and some messages being dropped.

ops-obtsdev 2016-08-09 22:45:35 UTC
OBTS: Stream hook file tree path correction

Author: Namburi Raghuram
Author Date: 2016-08-09 22:45:35 UTC

OBTS: Stream hook file tree path correction

pv-flowcntrl 2016-06-30 22:05:07 UTC
FLOWCONTROL: Fine-tuning Over/Under flow response

Author: Namburi Raghuram
Author Date: 2016-06-30 22:05:07 UTC

FLOWCONTROL: Fine-tuning Over/Under flow response

Underflow flags are now set to true on init
Overflows are now addressed even if a packet
needs to be sent immediately

rfnoc-devel 2014-11-07 14:29:10 UTC
x300/rfnoc: Adjusted buffers on tx side

Author: Martin
Author Date: 2014-11-07 14:29:10 UTC

x300/rfnoc: Adjusted buffers on tx side

maint 2014-11-04 14:17:43 UTC
x300: Fixed typo in io_impl

Author: Martin
Author Date: 2014-11-04 14:17:43 UTC

x300: Fixed typo in io_impl

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