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Branches

Name Last Modified Last Commit
ops/dwil/master 2024-06-28 19:22:54 UTC
TEST_TX_TRIGGER: remove setting thread priority

Author: Doug W
Author Date: 2024-06-28 19:22:52 UTC

TEST_TX_TRIGGER: remove setting thread priority

Performance does not matter in trigger mode, all this did was trigger a
warning when not run as root

ops/dwil/gp 2024-06-28 19:22:54 UTC
TEST_TX_TRIGGER: remove setting thread priority

Author: Doug W
Author Date: 2024-06-28 19:22:52 UTC

TEST_TX_TRIGGER: remove setting thread priority

Performance does not matter in trigger mode, all this did was trigger a
warning when not run as root

ops/amac/phase-testing-jesd-sync 2024-06-27 19:58:52 UTC
Reapply "UHD,CRIMSON_TNG: Reset to systemtime streamer to ensure phase cohere...

Author: Amelia MacLatchy
Author Date: 2024-06-27 19:58:52 UTC

Reapply "UHD,CRIMSON_TNG: Reset to systemtime streamer to ensure phase coherency."

This reverts commit 32d9b3b0f770a5eae9efcdd7f8af49cfbcbf3abc.

master 2024-06-27 18:27:04 UTC
Updating changelog

Author: Doug W
Author Date: 2024-06-27 18:24:37 UTC

Updating changelog

ops/amac/test 2024-06-26 15:17:48 UTC
Updating changelog

Author: Doug W
Author Date: 2024-06-26 15:17:48 UTC

Updating changelog

ops/dwil/bind_error 2024-06-24 17:06:50 UTC
RECV: auto change dst port if it is already in use

Author: Doug W
Author Date: 2024-06-21 18:43:39 UTC

RECV: auto change dst port if it is already in use

Previously destructing and constructing streamers to close together
could cause bind to fail since the OS hadn't marked the closed socket's
port as no longer in use

ops/dwil/mallopt 2024-06-21 22:46:00 UTC
re-enable M_MXFAST

Author: Doug W
Author Date: 2024-06-21 22:45:40 UTC

re-enable M_MXFAST

ops/dwil/liburing 2024-06-19 21:21:13 UTC
adding error checking and updating msg_len

Author: Doug W
Author Date: 2024-06-19 21:16:55 UTC

adding error checking and updating msg_len

ops/dwil/tmp 2024-06-18 21:02:44 UTC
DEBUG: adjust ring buffer size

Author: Doug W
Author Date: 2024-06-18 21:02:44 UTC

DEBUG: adjust ring buffer size

ops/dwil/buffer_level_in_send_thread 2024-06-17 18:59:22 UTC
debug msg

Author: Doug W
Author Date: 2024-06-17 18:59:22 UTC

debug msg

ops/dwil/pps_monitoring 2024-06-05 20:07:22 UTC
WIP: CYAN: implementing error handling for missing server property

Author: Doug W
Author Date: 2024-06-05 20:07:20 UTC

WIP: CYAN: implementing error handling for missing server property

Previous missing property would always return 0

ops/dwil/pwr_timeout 2024-06-03 18:09:08 UTC
CYAN: increasing timeout for management port commands

Author: Doug W
Author Date: 2024-06-03 18:09:08 UTC

CYAN: increasing timeout for management port commands

ops/dwil/overflow 2024-05-30 15:49:14 UTC
TEST: force overflows on tx

Author: Doug W
Author Date: 2024-05-30 15:49:14 UTC

TEST: force overflows on tx

ops/amac/9363dd9c 2024-05-16 16:03:12 UTC
Updating changelog

Author: Doug W
Author Date: 2024-05-16 15:20:10 UTC

Updating changelog

ops/vvv/10951-jesdresetcheck 2024-05-16 15:39:00 UTC
CRIMSON_TNG: Reset JESD every run. (diagnostic for #10951)

Author: Victor W
Author Date: 2024-05-16 15:39:00 UTC

CRIMSON_TNG: Reset JESD every run. (diagnostic for #10951)

ops/cjin/10951-mul-16 2024-05-14 15:21:21 UTC
chagned the mul to 16

Author: Chen Jin
Author Date: 2024-05-14 15:21:21 UTC

chagned the mul to 16

ops/cjin/10951-mul-4 2024-05-14 15:20:43 UTC
chagned the mul to 4

Author: Chen Jin
Author Date: 2024-05-14 15:20:43 UTC

chagned the mul to 4

ops/dwil/no_tx_min_delay 2024-05-13 20:40:16 UTC
removing min crimson tx delay

Author: Doug W
Author Date: 2024-05-13 20:40:16 UTC

removing min crimson tx delay

ops/jpol/test 2024-04-18 22:43:00 UTC
CRIMSON,TEST: reset the JESD

Author: John Polak
Author Date: 2024-04-18 22:43:00 UTC

CRIMSON,TEST: reset the JESD

ops/dwil/otw 2024-04-09 16:00:23 UTC
CYAN: implementing the ability to set otw format

Author: Doug W
Author Date: 2024-04-08 22:07:15 UTC

CYAN: implementing the ability to set otw format

ops/jpol/any_wire_fmt 2024-03-28 18:59:18 UTC
CYAN: Also allow unexpected wire format for TX

Author: John Polak
Author Date: 2024-03-28 18:59:18 UTC

CYAN: Also allow unexpected wire format for TX

ops/dwil/other 2024-03-26 20:51:18 UTC
RX_MULTI_RATES_TO_FILE: removing setting the data buffer to all 0

Author: Doug W
Author Date: 2024-03-26 20:51:18 UTC

RX_MULTI_RATES_TO_FILE: removing setting the data buffer to all 0

Should have no impact and has a significant impact on performance

ops/jpol/master 2024-03-26 15:05:47 UTC
Merge branch 'ops/amac/task11882_test_tx_trig' into ops/dwil/master

Author: Doug W
Author Date: 2024-03-26 15:05:47 UTC

Merge branch 'ops/amac/task11882_test_tx_trig' into ops/dwil/master

ops/dwil/ubuntu_slowdowns 2024-03-25 20:58:46 UTC
DEBUG: adding luring to specific file

Author: Doug W
Author Date: 2024-03-25 20:58:46 UTC

DEBUG: adding luring to specific file

ops/jpol/old_uhd 2024-03-25 17:31:47 UTC
CYAN_4R4T_3G, TEST: allow unexpected wire format

Author: John Polak
Author Date: 2024-03-25 17:31:47 UTC

CYAN_4R4T_3G, TEST: allow unexpected wire format

ops/dwil/old_uhd 2024-03-25 16:32:59 UTC
WIP: Adding cstdint to headers, supporting gcc-13.

Author: Victor W
Author Date: 2023-05-09 20:14:01 UTC

WIP: Adding cstdint to headers, supporting gcc-13.

ops/packaging/master 2024-03-14 01:45:23 UTC
Script: Adding ppa repo varible to the build script

Author: SFEN
Author Date: 2024-03-14 01:45:23 UTC

Script: Adding ppa repo varible to the build script

ops/dwil/auto_packet_length 2024-03-11 19:23:35 UTC
CYAN: get packet length from server

Author: Doug W
Author Date: 2024-03-11 19:23:35 UTC

CYAN: get packet length from server

ops/packaging/test2 2024-02-29 00:39:39 UTC
Packaging: Adding initial build files

Author: SFEN
Author Date: 2024-02-01 17:36:31 UTC

Packaging: Adding initial build files

ops/cjin/11668-trigger-backoff 2024-02-26 22:39:58 UTC
make backoff less

Author: Chen Jin
Author Date: 2024-02-26 22:39:58 UTC

make backoff less

ops/packaging/test3 2024-02-24 19:00:19 UTC
Test: Testing gcc13

Author: SFEN
Author Date: 2024-02-24 19:00:19 UTC

Test: Testing gcc13

ops/dwil/burst_loopback 2024-02-15 17:21:54 UTC
Merge branch 'master' of github.com:pervices/uhd into ops/dwil/burst_loopback

Author: Doug W
Author Date: 2024-02-15 17:21:54 UTC

Merge branch 'master' of github.com:pervices/uhd into ops/dwil/burst_loopback

ops/dwil/timespec_floating_point 2024-02-15 16:15:22 UTC
TIMESPEC: begining to make changes to avoid floating point errors

Author: Doug W
Author Date: 2024-02-13 22:24:52 UTC

TIMESPEC: begining to make changes to avoid floating point errors

ops/packaging/test 2024-02-03 02:53:16 UTC
Control: Adding git as a build requirement

Author: SFEN
Author Date: 2024-02-03 02:53:16 UTC

Control: Adding git as a build requirement

ops/cjin/11668-trigger-dev0 2024-02-02 16:45:46 UTC
disable vita

Author: Chen Jin
Author Date: 2024-02-02 16:45:46 UTC

disable vita

ops/vvv/pc-3 2024-01-23 23:16:45 UTC
Reapply "UHD,CRIMSON_TNG: Reset to systemtime streamer to ensure phase cohere...

Author: Victor W
Author Date: 2024-01-23 23:16:45 UTC

Reapply "UHD,CRIMSON_TNG: Reset to systemtime streamer to ensure phase coherency."

This reverts commit 32d9b3b0f770a5eae9efcdd7f8af49cfbcbf3abc.

ops/dwil/300msps 2024-01-23 20:38:50 UTC
CRIMSON: begining to dynamically handle different sample rates

Author: Doug W
Author Date: 2024-01-23 20:07:16 UTC

CRIMSON: begining to dynamically handle different sample rates

This should be able to handle existing 325MHz code. There are unknown
issues with 300MHz

ops/vvv/pt-2 2024-01-22 23:57:43 UTC
UHD,CRIMSON: Reset systemtime on initialization.

Author: Victor W
Author Date: 2024-01-22 23:57:43 UTC

UHD,CRIMSON: Reset systemtime on initialization.

ops/vvv/pt-1 2024-01-22 23:56:06 UTC
UHD,CRIMSON: Remove reset on boot.

Author: Victor W
Author Date: 2024-01-22 23:56:06 UTC

UHD,CRIMSON: Remove reset on boot.

ops/dwil/300Msps_hard_coded 2024-01-22 16:29:16 UTC
DEBUG: hard coding 300Msps clock rate

Author: Doug W
Author Date: 2024-01-22 16:29:16 UTC

DEBUG: hard coding 300Msps clock rate

ops/vvv/master 2024-01-19 20:27:09 UTC
Fixing waiting for clock sync

Author: Doug W
Author Date: 2024-01-19 17:02:58 UTC

Fixing waiting for clock sync

Previously it skip waiting for clock sync once a time diff resynce
request was acknowledged

Also added a way for getting time without bm_thread running

ops/dwil/ouflow_querry 2024-01-16 16:39:26 UTC
Merge branch 'ops/dwil/master' into ops/dwil/ouflow_querry

Author: Doug W
Author Date: 2024-01-16 16:39:26 UTC

Merge branch 'ops/dwil/master' into ops/dwil/ouflow_querry

ops/isho/blinky 2024-01-08 21:46:15 UTC
Merge remote-tracking branch 'refs/remotes/origin/ops/isho/blinky' into ops/i...

Author: Isaac Ho
Author Date: 2024-01-08 21:46:15 UTC

Merge remote-tracking branch 'refs/remotes/origin/ops/isho/blinky' into ops/isho/blinky

ops/cjin/11668-trigger 2023-12-07 21:20:12 UTC
only turn on vita, and time disable

Author: Chen Jin
Author Date: 2023-12-07 21:20:12 UTC

only turn on vita, and time disable

ops/cjin/11405-pps-detection-rc2 2023-12-07 19:04:08 UTC
PPS DETECTION: added thread to periodically scan if pps edge is detected in t...

Author: Chen Jin
Author Date: 2023-12-07 19:04:08 UTC

PPS DETECTION: added thread to periodically scan if pps edge is detected in the past second

ops/cjin/11405-pps-detection-rc1 2023-12-07 18:58:09 UTC
change back from debug test

Author: Chen Jin
Author Date: 2023-12-07 18:58:09 UTC

change back from debug test

ops/cjin/11405-pps_detection 2023-11-27 21:56:11 UTC
finallized code

Author: Chen Jin
Author Date: 2023-11-27 21:56:11 UTC

finallized code

ops/dwil/realtime 2023-11-17 22:14:25 UTC
Debugging

Author: Doug W
Author Date: 2023-11-17 22:14:25 UTC

Debugging

ops/dwil/debug/no_tx_timestamps 2023-11-15 21:48:07 UTC
fixup

Author: Doug W
Author Date: 2023-11-15 21:46:13 UTC

fixup

ops/dwil/tx_timestamps_only_first_packet 2023-11-15 21:41:48 UTC
fixup

Author: Doug W
Author Date: 2023-11-15 21:41:48 UTC

fixup

ops/cjin/dump-values 2023-11-09 17:13:54 UTC
changed to print leaf node only

Author: Chen Jin
Author Date: 2023-11-09 17:13:54 UTC

changed to print leaf node only

ops/cjin/11328-list_all_property_path_by_default-rc1 2023-09-28 17:32:09 UTC
UHDGET, UHD: modified the uhd_manual_get function so it has a dumpall functio...

Author: pvlt22
Author Date: 2023-09-28 17:32:09 UTC

UHDGET, UHD: modified the uhd_manual_get function so it has a dumpall function for dump all the paths

ops/cjin/11328-list_all_property_path_by_default 2023-09-28 17:26:59 UTC
UHDGET, UHD: modified the uhd_manual_get function so it has a dumpall functio...

Author: pvlt22
Author Date: 2023-09-28 17:26:59 UTC

UHDGET, UHD: modified the uhd_manual_get function so it has a dumpall function for dump all the paths

UHD-11328-list_all_property_path_by_default 2023-09-28 15:32:14 UTC
UHD, DUMPALL: added dump all function for uhd_manual_get

Author: pvlt22
Author Date: 2023-09-28 15:32:14 UTC

UHD, DUMPALL: added dump all function for uhd_manual_get

ops/cjin/master 2023-09-11 22:08:32 UTC
Rewriting MTU check to use IOCTL

Author: Doug W
Author Date: 2023-09-11 18:10:24 UTC

Rewriting MTU check to use IOCTL

Previously the MTU check relied on system(...) which may run into
portability issues. This fixes that.

Also moved the check to when creating the streamers since the MTU size
only matters if the interface is being used

ops/dwil/performance 2023-08-22 18:21:50 UTC
debug msg

Author: Doug W
Author Date: 2023-08-22 18:04:44 UTC

debug msg

ops/dwil/atlantic_troubleshooting 2023-08-17 16:10:22 UTC
debug msg

Author: Doug W
Author Date: 2023-08-17 16:10:22 UTC

debug msg

ops/dwil/performance_using_upstream 2023-08-03 15:52:47 UTC
Adding ifdefs so Cyan compiles without DPDK

Author: Doug W
Author Date: 2023-08-03 15:50:49 UTC

Adding ifdefs so Cyan compiles without DPDK

ops/dwil/multi_threaded_recv 2023-06-22 19:17:27 UTC
fixing

Author: Doug W
Author Date: 2023-06-22 19:10:27 UTC

fixing

master-testing 2023-05-25 21:23:12 UTC
SEND_REWRITE: fixing tx trigger

Author: Doug W
Author Date: 2023-05-25 19:24:46 UTC

SEND_REWRITE: fixing tx trigger

ops/srov/blinky 2023-05-17 15:06:23 UTC
Added Property in State Tree

Author: Stella Rovazzi
Author Date: 2023-05-17 15:06:23 UTC

Added Property in State Tree

Added a uhd state tree property that can control the blinker

Future: Run this with get and set (locally)

ops/apau/uhd_test 2023-05-16 17:58:15 UTC
Added path to access the led blink property

Author: Aleena Paul
Author Date: 2023-05-16 17:58:15 UTC

Added path to access the led blink property

ops/dwil/usrp_info 2023-02-27 18:10:30 UTC
UHD_USRP_INFO: adding options for what to show

Author: Doug W
Author Date: 2023-02-27 17:48:40 UTC

UHD_USRP_INFO: adding options for what to show

ops/dwil/old_time_packets 2023-02-13 19:25:42 UTC
CRIMSON_TNG: returning to old style of time diff packets

Author: Doug W
Author Date: 2023-02-13 19:25:42 UTC

CRIMSON_TNG: returning to old style of time diff packets

ops/dwil/old_compiling/rev250 2023-02-08 19:12:49 UTC
Copying file from latest to fix compilation error for older version

Author: Doug W
Author Date: 2023-02-08 19:12:49 UTC

Copying file from latest to fix compilation error for older version

master-cyan-rtm2.1 2023-02-03 17:57:04 UTC
Fixing typo from merge.

Author: Victor W
Author Date: 2023-02-03 17:57:04 UTC

Fixing typo from merge.

ops/dwil/dev/self_cal 2022-12-14 20:57:01 UTC
debug msg

Author: Doug W
Author Date: 2022-12-14 20:57:01 UTC

debug msg

ops/dwil/multi 2022-11-04 21:28:34 UTC
RXTX_INTER_DEVICE_STREAM: catching error + displaying if an error occured whe...

Author: Doug W
Author Date: 2022-11-04 21:27:44 UTC

RXTX_INTER_DEVICE_STREAM: catching error + displaying if an error occured when starting force stream

ops/dwil/tests/eob_only 2022-10-31 15:23:22 UTC
TESTING ONLY: provides a way to send EOB packet only

Author: Doug W
Author Date: 2022-10-21 20:23:32 UTC

TESTING ONLY: provides a way to send EOB packet only

Use: ./tx_waveforms --freq 0 --wave-type SINE --wave-freq 2000000 --rate 15000000 --gain 20 --channels "0" --first 10 --last 10 --nsamps 0 --args bypass_clock_sync=true

ops/dwil/bypass_conversion 2022-07-20 17:11:42 UTC
TEMPORARY PERFORMANCE TEST: always skip conversion

Author: Doug W
Author Date: 2022-07-20 17:11:42 UTC

TEMPORARY PERFORMANCE TEST: always skip conversion

ops/dwil/series_get_buffer_level 2022-06-23 20:47:38 UTC
fixup

Author: Doug W
Author Date: 2022-06-23 20:47:38 UTC

fixup

ops/jamb/uhd 2022-06-15 20:46:43 UTC
testing adding setting tree value

Author: John Ambrad
Author Date: 2022-06-15 20:46:43 UTC

testing adding setting tree value

ops/dwil/packet_timestamps 2022-06-09 18:28:59 UTC
CYAN_4R4T: begining to adding timestamps to all send packets

Author: Doug W
Author Date: 2022-06-09 17:21:42 UTC

CYAN_4R4T: begining to adding timestamps to all send packets

ops/dwil/setting_time_when_set_bl 2022-05-17 20:29:23 UTC
switching time diff to atmoic

Author: Doug W
Author Date: 2022-05-17 15:28:25 UTC

switching time diff to atmoic

ops/bmch/gp 2022-05-05 20:36:41 UTC
RX_to_TX_LOOPBACK: adding ability to select rx and tx channels

Author: Brendon McHugh
Author Date: 2022-05-05 19:09:44 UTC

RX_to_TX_LOOPBACK: adding ability to select rx and tx channels

ops/dwil/rx_to_tx_loopback 2022-05-03 21:22:36 UTC
Making both tx and rx threads set their own priority

Author: Doug W
Author Date: 2022-05-03 21:22:36 UTC

Making both tx and rx threads set their own priority

ops/dwil/troubleshooting_gnu_radio 2022-04-27 18:48:16 UTC
debug msg

Author: Doug W
Author Date: 2022-04-27 18:48:16 UTC

debug msg

ops/dwil/archi/1 2022-04-06 22:09:59 UTC
TXRX_TRIGGER_LOOPBACK: fixing rx trigger cleanip order

Author: Doug W
Author Date: 2022-04-06 22:09:23 UTC

TXRX_TRIGGER_LOOPBACK: fixing rx trigger cleanip order

ops/dwil/implementing_async_pwr 2022-04-05 17:40:35 UTC
fixup

Author: Doug W
Author Date: 2022-04-05 17:40:35 UTC

fixup

ops/dwil/no_packets_recv 2022-03-29 17:03:06 UTC
debug msg

Author: Doug W
Author Date: 2022-03-29 17:03:06 UTC

debug msg

ops/dwil/test_tx_trigger_no_sync 2022-03-28 19:15:19 UTC
TEST_TX_TRIGGER: exempting from clock synchronization for cyan_4r4t_3g

Author: Doug W
Author Date: 2022-03-28 18:33:25 UTC

TEST_TX_TRIGGER: exempting from clock synchronization for cyan_4r4t_3g

ops/dwil/updating_api 2022-03-04 20:42:50 UTC
Soft coding tx trigger test get_level

Author: Doug W
Author Date: 2022-03-04 19:35:31 UTC

Soft coding tx trigger test get_level

This version should work with both Crimson and Cyan

ops/dwil/updating_api_clean 2022-02-16 22:29:38 UTC
Merge branch 'ops/dwil/gp' into ops/dwil/updating_api

Author: Doug W
Author Date: 2022-02-16 22:02:22 UTC

Merge branch 'ops/dwil/gp' into ops/dwil/updating_api

updating_api is the branch used for merging with Ettus
This merge is to bring in changes made to the main branch while the
merge with Ettus was in progress

ops/bmch/master 2022-02-01 20:05:48 UTC
changes benchmark_rate so that it works properly

Author: Brendon McHugh
Author Date: 2022-02-01 20:01:06 UTC

changes benchmark_rate so that it works properly

INIT_DELAY was added to Rx so that Tx and Rx start at the same time as
well as increasing teh amount of time the program waits to account for
init delay

ops/dwil/archi/0 2022-01-31 22:35:59 UTC
fixup

Author: Doug W
Author Date: 2022-01-31 22:35:59 UTC

fixup

ops/dwil/benchmark_rate_fix 2022-01-28 20:17:42 UTC
debug msg

Author: Doug W
Author Date: 2022-01-28 20:17:42 UTC

debug msg

ops/dwil/updating_api_exists_crash 2022-01-27 18:25:15 UTC
debug msg

Author: Doug W
Author Date: 2022-01-27 18:25:15 UTC

debug msg

ops/dwil/1g_sample_half_working 2021-11-15 21:08:51 UTC
cleaning debug and comment

Author: Doug W
Author Date: 2021-11-15 21:08:51 UTC

cleaning debug and comment

ops/dwil/band_selection_manual 2021-11-15 18:47:13 UTC
debug msg

Author: Doug W
Author Date: 2021-11-15 18:47:13 UTC

debug msg

ops/dwil/improving_comments 2021-08-31 16:46:55 UTC
RX_START: adding channel number to message when setting freq

Author: Doug W
Author Date: 2021-08-31 16:46:55 UTC

RX_START: adding channel number to message when setting freq

ops/dwil/ip_fixing 2021-08-19 19:19:04 UTC
debug test

Author: Doug W
Author Date: 2021-08-19 19:19:04 UTC

debug test

ops/dwil/gp-cyan 2021-08-17 16:15:39 UTC
RX_STOP: fixing channel detection

Author: Doug W
Author Date: 2021-08-17 16:15:39 UTC

RX_STOP: fixing channel detection

ops/dwil/4r4t_1 2021-08-17 16:15:39 UTC
RX_STOP: fixing channel detection

Author: Doug W
Author Date: 2021-08-17 16:15:39 UTC

RX_STOP: fixing channel detection

ops/dwil/master-staging 2021-08-17 16:15:39 UTC
RX_STOP: fixing channel detection

Author: Doug W
Author Date: 2021-08-17 16:15:39 UTC

RX_STOP: fixing channel detection

ops/dwil/enabling_no_sfp_ip 2021-08-13 18:21:44 UTC
CYAN_8R: allows program to continue if rx IP binding fails

Author: Doug W
Author Date: 2021-08-13 18:21:44 UTC

CYAN_8R: allows program to continue if rx IP binding fails

ops/dwil/force_no_sfp 2021-08-12 22:18:51 UTC
debug

Author: Doug W
Author Date: 2021-08-12 22:18:51 UTC

debug

ops/dwil/rx_init_1 2021-08-06 19:20:55 UTC
RX_STOP: added force stream stop, only compatible with 8r

Author: Doug W
Author Date: 2021-08-06 19:20:55 UTC

RX_STOP: added force stream stop, only compatible with 8r

ops/dwil/tmp_staging_1 2021-08-05 23:14:29 UTC
CYAN_8R: changed number of tx channels to 4

Author: Doug W
Author Date: 2021-08-05 23:06:11 UTC

CYAN_8R: changed number of tx channels to 4

For some reason having 4 tx channels works, even though other versions
need the same number of tx and rx channels. This is a temporary fix to
the problem. The long term solution still needs to be foun

ops/dwil/splitting_rx_init 2021-08-05 23:06:11 UTC
CYAN_8R: changed number of tx channels to 4

Author: Doug W
Author Date: 2021-08-05 23:06:11 UTC

CYAN_8R: changed number of tx channels to 4

For some reason having 4 tx channels works, even though other versions
need the same number of tx and rx channels. This is a temporary fix to
the problem. The long term solution still needs to be foun

ops/dwil/tmp_bisect_4 2021-08-05 22:57:24 UTC
DEBUG: checking if the change in number of rx channels or tx channels causes ...

Author: Doug W
Author Date: 2021-08-05 22:57:24 UTC

DEBUG: checking if the change in number of rx channels or tx channels causes the error

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