Commit 616badd2fb49 ("powerpc/powernv: Use OPAL call for TCE kill on
NVLink2") forced all TCE kills to go via the OPAL call for
NVLink2. However the PHB3 implementation of TCE kill was still being
called directly from some functions which in some circumstances caused
a machine check.
This patch adds an equivalent IODA2 version of the function which uses
the correct invalidation method depending on PHB model and changes all
external callers to use it instead.
Fixes: 616badd2fb49 ("powerpc/powernv: Use OPAL call for TCE kill on NVLink2")
Cc: <email address hidden> # v4.11+
Signed-off-by: Alistair Popple <email address hidden>
Signed-off-by: Michael Ellerman <email address hidden>
(cherry picked from commit 6b3d12a948d27977816a15eb48409a298902a548)
Signed-off-by: Breno Leitao <email address hidden>
Acked-by: Seth Forshee <email address hidden>
Acked-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
30a0536...
by
Amey Telawane <email address hidden>
tracing: Use strlcpy() instead of strcpy() in __trace_find_cmdline()
Strcpy is inherently not safe, and strlcpy() should be used instead.
__trace_find_cmdline() uses strcpy() because the comms saved must have a
terminating nul character, but it doesn't hurt to add the extra protection
of using strlcpy() instead of strcpy().
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each individual PMU is provided even though all CPUs share all
the slices. User space needs to aggregate to individual counts to provide
a global picture.
The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
perf stat -a -e l3cache_0_0/read-miss/
perf stat -a -e l3cache_0_0/event=0x21/
Acked-by: Mark Rutland <email address hidden>
Signed-off-by: Agustin Vega-Frias <email address hidden>
[will: fixed sparse issues]
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit 3071f13d75f627ed8648535815a0506d50cbc6ed)
Signed-off-by: dann frazier <email address hidden>
Acked-by: Seth Forshee <email address hidden>
Acked-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
Now that we have a framework to handle the ACPI bits, make the PMUv3
code use this. The framework is a little different to what was
originally envisaged, and we can drop some unused support code in the
process of moving over to it.
Signed-off-by: Mark Rutland <email address hidden>
Tested-by: Jeremy Linton <email address hidden>
[will: make armv8_pmu_driver_init static]
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit f00fa5f4163b40c3ec8590d9a7bd845c19bf8d16)
Signed-off-by: dann frazier <email address hidden>
Acked-by: Seth Forshee <email address hidden>
Acked-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
When probing via ACPI, we won't know up-front whether a CPU has a PMUv3
compatible PMU. Thus we need to consult ID registers during probe time.
This patch updates our PMUv3 probing code to test for the presence of
PMUv3 functionality before touching an PMUv3-specific registers, and
before updating the struct arm_pmu with PMUv3 data.
When a PMUv3-compatible PMU is not present, probing will return -ENODEV.
Signed-off-by: Mark Rutland <email address hidden>
Cc: Will Deacon <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit f1b36dcb5c316c276ca6faedc50d89d97f90d960)
Signed-off-by: dann frazier <email address hidden>
Acked-by: Seth Forshee <email address hidden>
Acked-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
This patch adds framework code to handle parsing PMU data out of the
MADT, sanity checking this, and managing the association of CPUs (and
their interrupts) with appropriate logical PMUs.
For the time being, we expect that only one PMU driver (PMUv3) will make
use of this, and we simply pass in a single probe function.
This is based on an earlier patch from Jeremy Linton.
Signed-off-by: Mark Rutland <email address hidden>
Tested-by: Jeremy Linton <email address hidden>
Cc: Will Deacon <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit 45736a72fb79b204c1fbdb08a1e1a2aa52c7281a)
Signed-off-by: dann frazier <email address hidden>
Acked-by: Seth Forshee <email address hidden>
Acked-by: Thadeu Lima de Souza Cascardo <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
