Merge ~vickdu31helpsite/ubuntu/+source/linux/+git/oracular:x1e-6.12/207-acer-swift-sf14-11 into ~ubuntu-concept/ubuntu/+source/linux/+git/oracular:qcom-x1e
- Git
- lp:~vickdu31helpsite/ubuntu/+source/linux/+git/oracular
- x1e-6.12/207-acer-swift-sf14-11
- Merge into qcom-x1e
Proposed by
Victorien Alric
Status: | Merged |
---|---|
Merge reported by: | Tobias Heider |
Merged at revision: | 08a9dbfb5ce18d47bd4b6edc33d268cdd3989752 |
Proposed branch: | ~vickdu31helpsite/ubuntu/+source/linux/+git/oracular:x1e-6.12/207-acer-swift-sf14-11 |
Merge into: | ~ubuntu-concept/ubuntu/+source/linux/+git/oracular:qcom-x1e |
Diff against target: |
1372 lines (+1358/-0) 2 files modified
arch/arm64/boot/dts/qcom/Makefile (+2/-0) arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts (+1356/-0) |
Related bugs: |
Reviewer | Review Type | Date Requested | Status |
---|---|---|---|
Tobias Heider | Approve | ||
Review via email: mp+477184@code.launchpad.net |
Commit message
Device tree for Acer Swift SF14
Description of the change
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- 08a9dbf... by Victorien
-
Update from tobhe comments
Revision history for this message
Tobias Heider (tobhe) wrote : | # |
After cloning the tree and taking a closer look I think we need to change a few more things, but I might just do that in-tree if that is ok with you:
- Indentation should be tabs, everything is also indented one space too much
- Copyright should start with Copyright (c) 2024 to match the previous lines
After adding dt-bindings and running `make ARCH=arm64 CHECK_DTBS=y qcom/x1p64100-
- The swrX nodes, lpass_* and vreg_l1b_1p8 are audio related and could be droppped for now.
- bluetooth is broken (because it was in the T14s dtb). We might need to remove or resync that.
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1 | diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile |
2 | index d12cebc..c211c14 100644 |
3 | --- a/arch/arm64/boot/dts/qcom/Makefile |
4 | +++ b/arch/arm64/boot/dts/qcom/Makefile |
5 | @@ -271,3 +271,5 @@ dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb |
6 | dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb |
7 | dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb |
8 | dtb-$(CONFIG_ARCH_QCOM) += x1e80100-samsung-galaxy-book4-edge.dtb |
9 | +dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb |
10 | + |
11 | diff --git a/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts b/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts |
12 | new file mode 100644 |
13 | index 0000000..8cb33ba |
14 | --- /dev/null |
15 | +++ b/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts |
16 | @@ -0,0 +1,1356 @@ |
17 | +// SPDX-License-Identifier: BSD-3-Clause |
18 | +/* |
19 | + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. |
20 | + * Copyright (c) 2024, Linaro Limited |
21 | + * Victorien Alric - vickdu31 |
22 | + */ |
23 | + |
24 | + /dts-v1/; |
25 | + |
26 | + #include <dt-bindings/gpio/gpio.h> |
27 | + #include <dt-bindings/input/gpio-keys.h> |
28 | + #include <dt-bindings/input/input.h> |
29 | + #include <dt-bindings/regulator/qcom,rpmh-regulator.h> |
30 | + |
31 | + #include "x1e80100.dtsi" |
32 | + #include "x1e80100-pmics.dtsi" |
33 | + |
34 | + / { |
35 | + model = "Acer Swift 14 AI (SF14-11)"; |
36 | + compatible = "acer,swift-sf14-11","qcom,x1p64100", "qcom,x1e80100"; |
37 | + chassis-type = "laptop"; |
38 | + |
39 | + aliases { |
40 | + serial0 = &uart21; |
41 | + serial1 = &uart14; |
42 | + }; |
43 | + |
44 | + backlight: backlight { |
45 | + compatible = "pwm-backlight"; |
46 | + pwms = <&pmk8550_pwm 0 5000000>; |
47 | + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; |
48 | + power-supply = <&vreg_edp_bl>; |
49 | + |
50 | + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; |
51 | + pinctrl-names = "default"; |
52 | + }; |
53 | + |
54 | + gpio-keys { |
55 | + compatible = "gpio-keys"; |
56 | + |
57 | + pinctrl-0 = <&hall_int_n_default>; |
58 | + pinctrl-names = "default"; |
59 | + |
60 | + switch-lid { |
61 | + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; |
62 | + linux,input-type = <EV_SW>; |
63 | + linux,code = <SW_LID>; |
64 | + wakeup-source; |
65 | + wakeup-event-action = <EV_ACT_DEASSERTED>; |
66 | + }; |
67 | + }; |
68 | + |
69 | + pmic-glink { |
70 | + compatible = "qcom,x1e80100-pmic-glink", |
71 | + "qcom,sm8550-pmic-glink", |
72 | + "qcom,pmic-glink"; |
73 | + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, |
74 | + <&tlmm 123 GPIO_ACTIVE_HIGH>; |
75 | + #address-cells = <1>; |
76 | + #size-cells = <0>; |
77 | + |
78 | + /* Display-adjacent port */ |
79 | + connector@0 { |
80 | + compatible = "usb-c-connector"; |
81 | + reg = <0>; |
82 | + power-role = "dual"; |
83 | + data-role = "dual"; |
84 | + |
85 | + ports { |
86 | + #address-cells = <1>; |
87 | + #size-cells = <0>; |
88 | + |
89 | + port@0 { |
90 | + reg = <0>; |
91 | + |
92 | + pmic_glink_ss0_hs_in: endpoint { |
93 | + remote-endpoint = <&usb_1_ss0_dwc3_hs>; |
94 | + }; |
95 | + }; |
96 | + |
97 | + port@1 { |
98 | + reg = <1>; |
99 | + |
100 | + pmic_glink_ss0_ss_in: endpoint { |
101 | + remote-endpoint = <&retimer_ss0_ss_out>; |
102 | + }; |
103 | + }; |
104 | + |
105 | + port@2 { |
106 | + reg = <2>; |
107 | + |
108 | + pmic_glink_ss0_con_sbu_in: endpoint { |
109 | + remote-endpoint = <&retimer_ss0_con_sbu_out>; |
110 | + }; |
111 | + }; |
112 | + }; |
113 | + }; |
114 | + |
115 | + /* User-adjacent port */ |
116 | + connector@1 { |
117 | + compatible = "usb-c-connector"; |
118 | + reg = <1>; |
119 | + power-role = "dual"; |
120 | + data-role = "dual"; |
121 | + |
122 | + ports { |
123 | + #address-cells = <1>; |
124 | + #size-cells = <0>; |
125 | + |
126 | + port@0 { |
127 | + reg = <0>; |
128 | + |
129 | + pmic_glink_ss1_hs_in: endpoint { |
130 | + remote-endpoint = <&usb_1_ss1_dwc3_hs>; |
131 | + }; |
132 | + }; |
133 | + |
134 | + port@1 { |
135 | + reg = <1>; |
136 | + |
137 | + pmic_glink_ss1_ss_in: endpoint { |
138 | + remote-endpoint = <&retimer_ss1_ss_out>; |
139 | + }; |
140 | + }; |
141 | + |
142 | + port@2 { |
143 | + reg = <2>; |
144 | + |
145 | + pmic_glink_ss1_con_sbu_in: endpoint { |
146 | + remote-endpoint = <&retimer_ss1_con_sbu_out>; |
147 | + }; |
148 | + }; |
149 | + }; |
150 | + }; |
151 | + }; |
152 | + |
153 | + reserved-memory { |
154 | + linux,cma { |
155 | + compatible = "shared-dma-pool"; |
156 | + size = <0x0 0x8000000>; |
157 | + reusable; |
158 | + linux,cma-default; |
159 | + }; |
160 | + }; |
161 | + |
162 | + vreg_edp_3p3: regulator-edp-3p3 { |
163 | + compatible = "regulator-fixed"; |
164 | + |
165 | + regulator-name = "VREG_EDP_3P3"; |
166 | + regulator-min-microvolt = <3300000>; |
167 | + regulator-max-microvolt = <3300000>; |
168 | + |
169 | + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; |
170 | + enable-active-high; |
171 | + |
172 | + pinctrl-0 = <&edp_reg_en>; |
173 | + pinctrl-names = "default"; |
174 | + |
175 | + regulator-boot-on; |
176 | + }; |
177 | + |
178 | + vreg_edp_bl: regulator-edp-bl { |
179 | + compatible = "regulator-fixed"; |
180 | + |
181 | + regulator-name = "VBL9"; |
182 | + regulator-min-microvolt = <3600000>; |
183 | + regulator-max-microvolt = <3600000>; |
184 | + |
185 | + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; |
186 | + enable-active-high; |
187 | + |
188 | + pinctrl-names = "default"; |
189 | + pinctrl-0 = <&edp_bl_reg_en>; |
190 | + |
191 | + regulator-boot-on; |
192 | + }; |
193 | + |
194 | + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { |
195 | + compatible = "regulator-fixed"; |
196 | + |
197 | + regulator-name = "VREG_RTMR0_1P15"; |
198 | + regulator-min-microvolt = <1150000>; |
199 | + regulator-max-microvolt = <1150000>; |
200 | + |
201 | + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; |
202 | + enable-active-high; |
203 | + |
204 | + pinctrl-0 = <&rtmr0_1p15_reg_en>; |
205 | + pinctrl-names = "default"; |
206 | + |
207 | + regulator-boot-on; |
208 | + }; |
209 | + |
210 | + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { |
211 | + compatible = "regulator-fixed"; |
212 | + |
213 | + regulator-name = "VREG_RTMR0_1P8"; |
214 | + regulator-min-microvolt = <1800000>; |
215 | + regulator-max-microvolt = <1800000>; |
216 | + |
217 | + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; |
218 | + enable-active-high; |
219 | + |
220 | + pinctrl-0 = <&rtmr0_1p8_reg_en>; |
221 | + pinctrl-names = "default"; |
222 | + |
223 | + regulator-boot-on; |
224 | + }; |
225 | + |
226 | + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { |
227 | + compatible = "regulator-fixed"; |
228 | + |
229 | + regulator-name = "VREG_RTMR0_3P3"; |
230 | + regulator-min-microvolt = <3300000>; |
231 | + regulator-max-microvolt = <3300000>; |
232 | + |
233 | + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; |
234 | + enable-active-high; |
235 | + |
236 | + pinctrl-0 = <&rtmr0_3p3_reg_en>; |
237 | + pinctrl-names = "default"; |
238 | + |
239 | + regulator-boot-on; |
240 | + }; |
241 | + |
242 | + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { |
243 | + compatible = "regulator-fixed"; |
244 | + |
245 | + regulator-name = "VREG_RTMR1_1P15"; |
246 | + regulator-min-microvolt = <1150000>; |
247 | + regulator-max-microvolt = <1150000>; |
248 | + |
249 | + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; |
250 | + enable-active-high; |
251 | + |
252 | + pinctrl-names = "default"; |
253 | + pinctrl-0 = <&rtmr1_1p15_reg_en>; |
254 | + |
255 | + regulator-boot-on; |
256 | + }; |
257 | + |
258 | + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { |
259 | + compatible = "regulator-fixed"; |
260 | + |
261 | + regulator-name = "VREG_RTMR1_1P8"; |
262 | + regulator-min-microvolt = <1800000>; |
263 | + regulator-max-microvolt = <1800000>; |
264 | + |
265 | + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; |
266 | + enable-active-high; |
267 | + |
268 | + pinctrl-names = "default"; |
269 | + pinctrl-0 = <&rtmr1_1p8_reg_en>; |
270 | + |
271 | + regulator-boot-on; |
272 | + }; |
273 | + |
274 | + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { |
275 | + compatible = "regulator-fixed"; |
276 | + |
277 | + regulator-name = "VREG_RTMR1_3P3"; |
278 | + regulator-min-microvolt = <3300000>; |
279 | + regulator-max-microvolt = <3300000>; |
280 | + |
281 | + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; |
282 | + enable-active-high; |
283 | + |
284 | + pinctrl-names = "default"; |
285 | + pinctrl-0 = <&rtmr1_3p3_reg_en>; |
286 | + |
287 | + regulator-boot-on; |
288 | + }; |
289 | + |
290 | + vreg_nvme: regulator-nvme { |
291 | + compatible = "regulator-fixed"; |
292 | + |
293 | + regulator-name = "VREG_NVME_3P3"; |
294 | + regulator-min-microvolt = <3300000>; |
295 | + regulator-max-microvolt = <3300000>; |
296 | + |
297 | + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; |
298 | + enable-active-high; |
299 | + |
300 | + pinctrl-0 = <&nvme_reg_en>; |
301 | + pinctrl-names = "default"; |
302 | + }; |
303 | + |
304 | + vph_pwr: regulator-vph-pwr { |
305 | + compatible = "regulator-fixed"; |
306 | + |
307 | + regulator-name = "vph_pwr"; |
308 | + regulator-min-microvolt = <3700000>; |
309 | + regulator-max-microvolt = <3700000>; |
310 | + |
311 | + regulator-always-on; |
312 | + regulator-boot-on; |
313 | + }; |
314 | + }; |
315 | + |
316 | + &apps_rsc { |
317 | + regulators-0 { |
318 | + compatible = "qcom,pm8550-rpmh-regulators"; |
319 | + qcom,pmic-id = "b"; |
320 | + |
321 | + vdd-bob1-supply = <&vph_pwr>; |
322 | + vdd-bob2-supply = <&vph_pwr>; |
323 | + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; |
324 | + vdd-l2-l13-l14-supply = <&vreg_bob1>; |
325 | + vdd-l5-l16-supply = <&vreg_bob1>; |
326 | + vdd-l6-l7-supply = <&vreg_bob2>; |
327 | + vdd-l8-l9-supply = <&vreg_bob1>; |
328 | + vdd-l12-supply = <&vreg_s5j_1p2>; |
329 | + vdd-l15-supply = <&vreg_s4c_1p8>; |
330 | + vdd-l17-supply = <&vreg_bob2>; |
331 | + |
332 | + vreg_bob1: bob1 { |
333 | + regulator-name = "vreg_bob1"; |
334 | + regulator-min-microvolt = <3008000>; |
335 | + regulator-max-microvolt = <3960000>; |
336 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
337 | + }; |
338 | + |
339 | + vreg_bob2: bob2 { |
340 | + regulator-name = "vreg_bob2"; |
341 | + regulator-min-microvolt = <2504000>; |
342 | + regulator-max-microvolt = <3008000>; |
343 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
344 | + }; |
345 | + |
346 | + vreg_l1b_1p8: ldo1 { |
347 | + regulator-name = "vreg_l1b_1p8"; |
348 | + regulator-min-microvolt = <1800000>; |
349 | + regulator-max-microvolt = <1800000>; |
350 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
351 | + }; |
352 | + |
353 | + vreg_l2b_3p0: ldo2 { |
354 | + regulator-name = "vreg_l2b_3p0"; |
355 | + regulator-min-microvolt = <3072000>; |
356 | + regulator-max-microvolt = <3072000>; |
357 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
358 | + }; |
359 | + |
360 | + vreg_l4b_1p8: ldo4 { |
361 | + regulator-name = "vreg_l4b_1p8"; |
362 | + regulator-min-microvolt = <1800000>; |
363 | + regulator-max-microvolt = <1800000>; |
364 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
365 | + }; |
366 | + |
367 | + vreg_l6b_1p8: ldo6 { |
368 | + regulator-name = "vreg_l6b_1p8"; |
369 | + regulator-min-microvolt = <1800000>; |
370 | + regulator-max-microvolt = <2960000>; |
371 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
372 | + }; |
373 | + |
374 | + vreg_l8b_3p0: ldo8 { |
375 | + regulator-name = "vreg_l8b_3p0"; |
376 | + regulator-min-microvolt = <3072000>; |
377 | + regulator-max-microvolt = <3072000>; |
378 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
379 | + }; |
380 | + |
381 | + vreg_l9b_2p9: ldo9 { |
382 | + regulator-name = "vreg_l9b_2p9"; |
383 | + regulator-min-microvolt = <2960000>; |
384 | + regulator-max-microvolt = <2960000>; |
385 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
386 | + }; |
387 | + |
388 | + vreg_l10b_1p8: ldo10 { |
389 | + regulator-name = "vreg_l10b_1p8"; |
390 | + regulator-min-microvolt = <1800000>; |
391 | + regulator-max-microvolt = <1800000>; |
392 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
393 | + }; |
394 | + |
395 | + vreg_l12b_1p2: ldo12 { |
396 | + regulator-name = "vreg_l12b_1p2"; |
397 | + regulator-min-microvolt = <1200000>; |
398 | + regulator-max-microvolt = <1200000>; |
399 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
400 | + }; |
401 | + |
402 | + vreg_l13b_3p0: ldo13 { |
403 | + regulator-name = "vreg_l13b_3p0"; |
404 | + regulator-min-microvolt = <3072000>; |
405 | + regulator-max-microvolt = <3072000>; |
406 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
407 | + }; |
408 | + |
409 | + vreg_l14b_3p0: ldo14 { |
410 | + regulator-name = "vreg_l14b_3p0"; |
411 | + regulator-min-microvolt = <3072000>; |
412 | + regulator-max-microvolt = <3072000>; |
413 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
414 | + }; |
415 | + |
416 | + vreg_l15b_1p8: ldo15 { |
417 | + regulator-name = "vreg_l15b_1p8"; |
418 | + regulator-min-microvolt = <1800000>; |
419 | + regulator-max-microvolt = <1800000>; |
420 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
421 | + }; |
422 | + |
423 | + vreg_l17b_2p5: ldo17 { |
424 | + regulator-name = "vreg_l17b_2p5"; |
425 | + regulator-min-microvolt = <2504000>; |
426 | + regulator-max-microvolt = <2504000>; |
427 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
428 | + }; |
429 | + }; |
430 | + |
431 | + regulators-1 { |
432 | + compatible = "qcom,pm8550ve-rpmh-regulators"; |
433 | + qcom,pmic-id = "c"; |
434 | + |
435 | + vdd-l1-supply = <&vreg_s5j_1p2>; |
436 | + vdd-l2-supply = <&vreg_s1f_0p7>; |
437 | + vdd-l3-supply = <&vreg_s1f_0p7>; |
438 | + vdd-s4-supply = <&vph_pwr>; |
439 | + |
440 | + vreg_s4c_1p8: smps4 { |
441 | + regulator-name = "vreg_s4c_1p8"; |
442 | + regulator-min-microvolt = <1856000>; |
443 | + regulator-max-microvolt = <2000000>; |
444 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
445 | + }; |
446 | + |
447 | + vreg_l1c_1p2: ldo1 { |
448 | + regulator-name = "vreg_l1c_1p2"; |
449 | + regulator-min-microvolt = <1200000>; |
450 | + regulator-max-microvolt = <1200000>; |
451 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
452 | + }; |
453 | + |
454 | + vreg_l2c_0p8: ldo2 { |
455 | + regulator-name = "vreg_l2c_0p8"; |
456 | + regulator-min-microvolt = <880000>; |
457 | + regulator-max-microvolt = <880000>; |
458 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
459 | + }; |
460 | + |
461 | + vreg_l3c_0p8: ldo3 { |
462 | + regulator-name = "vreg_l3c_0p8"; |
463 | + regulator-min-microvolt = <912000>; |
464 | + regulator-max-microvolt = <912000>; |
465 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
466 | + }; |
467 | + }; |
468 | + |
469 | + regulators-2 { |
470 | + compatible = "qcom,pmc8380-rpmh-regulators"; |
471 | + qcom,pmic-id = "d"; |
472 | + |
473 | + vdd-l1-supply = <&vreg_s1f_0p7>; |
474 | + vdd-l2-supply = <&vreg_s1f_0p7>; |
475 | + vdd-l3-supply = <&vreg_s4c_1p8>; |
476 | + vdd-s1-supply = <&vph_pwr>; |
477 | + |
478 | + vreg_l1d_0p8: ldo1 { |
479 | + regulator-name = "vreg_l1d_0p8"; |
480 | + regulator-min-microvolt = <880000>; |
481 | + regulator-max-microvolt = <880000>; |
482 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
483 | + }; |
484 | + |
485 | + vreg_l2d_0p9: ldo2 { |
486 | + regulator-name = "vreg_l2d_0p9"; |
487 | + regulator-min-microvolt = <912000>; |
488 | + regulator-max-microvolt = <912000>; |
489 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
490 | + }; |
491 | + |
492 | + vreg_l3d_1p8: ldo3 { |
493 | + regulator-name = "vreg_l3d_1p8"; |
494 | + regulator-min-microvolt = <1800000>; |
495 | + regulator-max-microvolt = <1800000>; |
496 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
497 | + }; |
498 | + }; |
499 | + |
500 | + regulators-3 { |
501 | + compatible = "qcom,pmc8380-rpmh-regulators"; |
502 | + qcom,pmic-id = "e"; |
503 | + |
504 | + vdd-l2-supply = <&vreg_s1f_0p7>; |
505 | + vdd-l3-supply = <&vreg_s5j_1p2>; |
506 | + |
507 | + vreg_l2e_0p8: ldo2 { |
508 | + regulator-name = "vreg_l2e_0p8"; |
509 | + regulator-min-microvolt = <880000>; |
510 | + regulator-max-microvolt = <880000>; |
511 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
512 | + }; |
513 | + |
514 | + vreg_l3e_1p2: ldo3 { |
515 | + regulator-name = "vreg_l3e_1p2"; |
516 | + regulator-min-microvolt = <1200000>; |
517 | + regulator-max-microvolt = <1200000>; |
518 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
519 | + }; |
520 | + }; |
521 | + |
522 | + regulators-4 { |
523 | + compatible = "qcom,pmc8380-rpmh-regulators"; |
524 | + qcom,pmic-id = "f"; |
525 | + |
526 | + vdd-l1-supply = <&vreg_s5j_1p2>; |
527 | + vdd-l2-supply = <&vreg_s5j_1p2>; |
528 | + vdd-l3-supply = <&vreg_s5j_1p2>; |
529 | + vdd-s1-supply = <&vph_pwr>; |
530 | + |
531 | + vreg_s1f_0p7: smps1 { |
532 | + regulator-name = "vreg_s1f_0p7"; |
533 | + regulator-min-microvolt = <700000>; |
534 | + regulator-max-microvolt = <1100000>; |
535 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
536 | + }; |
537 | + }; |
538 | + |
539 | + regulators-6 { |
540 | + compatible = "qcom,pm8550ve-rpmh-regulators"; |
541 | + qcom,pmic-id = "i"; |
542 | + |
543 | + vdd-l1-supply = <&vreg_s4c_1p8>; |
544 | + vdd-l2-supply = <&vreg_s5j_1p2>; |
545 | + vdd-l3-supply = <&vreg_s1f_0p7>; |
546 | + vdd-s1-supply = <&vph_pwr>; |
547 | + vdd-s2-supply = <&vph_pwr>; |
548 | + |
549 | + vreg_l1i_1p8: ldo1 { |
550 | + regulator-name = "vreg_l1i_1p8"; |
551 | + regulator-min-microvolt = <1800000>; |
552 | + regulator-max-microvolt = <1800000>; |
553 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
554 | + }; |
555 | + |
556 | + vreg_l2i_1p2: ldo2 { |
557 | + regulator-name = "vreg_l2i_1p2"; |
558 | + regulator-min-microvolt = <1200000>; |
559 | + regulator-max-microvolt = <1200000>; |
560 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
561 | + }; |
562 | + |
563 | + vreg_l3i_0p8: ldo3 { |
564 | + regulator-name = "vreg_l3i_0p8"; |
565 | + regulator-min-microvolt = <880000>; |
566 | + regulator-max-microvolt = <880000>; |
567 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
568 | + }; |
569 | + }; |
570 | + |
571 | + regulators-7 { |
572 | + compatible = "qcom,pm8550ve-rpmh-regulators"; |
573 | + qcom,pmic-id = "j"; |
574 | + |
575 | + vdd-l1-supply = <&vreg_s1f_0p7>; |
576 | + vdd-l2-supply = <&vreg_s5j_1p2>; |
577 | + vdd-l3-supply = <&vreg_s1f_0p7>; |
578 | + vdd-s5-supply = <&vph_pwr>; |
579 | + |
580 | + vreg_s5j_1p2: smps5 { |
581 | + regulator-name = "vreg_s5j_1p2"; |
582 | + regulator-min-microvolt = <1256000>; |
583 | + regulator-max-microvolt = <1304000>; |
584 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
585 | + }; |
586 | + |
587 | + vreg_l1j_0p8: ldo1 { |
588 | + regulator-name = "vreg_l1j_0p8"; |
589 | + regulator-min-microvolt = <912000>; |
590 | + regulator-max-microvolt = <912000>; |
591 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
592 | + }; |
593 | + |
594 | + vreg_l2j_1p2: ldo2 { |
595 | + regulator-name = "vreg_l2j_1p2"; |
596 | + regulator-min-microvolt = <1256000>; |
597 | + regulator-max-microvolt = <1256000>; |
598 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
599 | + }; |
600 | + |
601 | + vreg_l3j_0p8: ldo3 { |
602 | + regulator-name = "vreg_l3j_0p8"; |
603 | + regulator-min-microvolt = <880000>; |
604 | + regulator-max-microvolt = <880000>; |
605 | + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; |
606 | + }; |
607 | + }; |
608 | + }; |
609 | + |
610 | + &gpu { |
611 | + status = "okay"; |
612 | + |
613 | + zap-shader { |
614 | + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcdxkmsuc8380.mbn"; |
615 | + }; |
616 | + }; |
617 | + |
618 | + &i2c0 { |
619 | + clock-frequency = <400000>; |
620 | + |
621 | + status = "okay"; |
622 | + |
623 | + touchpad@68 { |
624 | + compatible = "hid-over-i2c"; |
625 | + reg = <0x68>; |
626 | + |
627 | + hid-descr-addr = <0x20>; |
628 | + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; |
629 | + |
630 | + wakeup-source; |
631 | + }; |
632 | + |
633 | + |
634 | + /* ELAN06F1 or SYNA06F2 */ |
635 | + keyboard@3a { |
636 | + compatible = "hid-over-i2c"; |
637 | + reg = <0x3a>; |
638 | + |
639 | + hid-descr-addr = <0x1>; |
640 | + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; |
641 | + |
642 | + pinctrl-0 = <&kybd_default>; |
643 | + pinctrl-names = "default"; |
644 | + |
645 | + wakeup-source; |
646 | + }; |
647 | + }; |
648 | + |
649 | + &i2c3 { |
650 | + clock-frequency = <400000>; |
651 | + |
652 | + status = "okay"; |
653 | + |
654 | + typec-mux@8 { |
655 | + compatible = "parade,ps8830"; |
656 | + reg = <0x08>; |
657 | + |
658 | + clocks = <&rpmhcc RPMH_RF_CLK3>; |
659 | + clock-names = "xo"; |
660 | + |
661 | + vdd-supply = <&vreg_rtmr0_1p15>; |
662 | + vdd33-supply = <&vreg_rtmr0_3p3>; |
663 | + vdd33-cap-supply = <&vreg_rtmr0_3p3>; |
664 | + vddar-supply = <&vreg_rtmr0_1p15>; |
665 | + vddat-supply = <&vreg_rtmr0_1p15>; |
666 | + vddio-supply = <&vreg_rtmr0_1p8>; |
667 | + |
668 | + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; |
669 | + |
670 | + retimer-switch; |
671 | + orientation-switch; |
672 | + |
673 | + ports { |
674 | + #address-cells = <1>; |
675 | + #size-cells = <0>; |
676 | + |
677 | + port@0 { |
678 | + reg = <0>; |
679 | + |
680 | + retimer_ss0_ss_out: endpoint { |
681 | + remote-endpoint = <&pmic_glink_ss0_ss_in>; |
682 | + }; |
683 | + }; |
684 | + |
685 | + port@1 { |
686 | + reg = <1>; |
687 | + |
688 | + retimer_ss0_ss_in: endpoint { |
689 | + remote-endpoint = <&usb_1_ss0_qmpphy_out>; |
690 | + }; |
691 | + }; |
692 | + |
693 | + port@2 { |
694 | + reg = <2>; |
695 | + |
696 | + retimer_ss0_con_sbu_out: endpoint { |
697 | + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; |
698 | + }; |
699 | + }; |
700 | + }; |
701 | + }; |
702 | + }; |
703 | + |
704 | + &i2c5 { |
705 | + clock-frequency = <400000>; |
706 | + |
707 | + status = "okay"; |
708 | + |
709 | + eusb5_repeater: redriver@43 { |
710 | + compatible = "nxp,ptn3222"; |
711 | + reg = <0x43>; |
712 | + #phy-cells = <0>; |
713 | + |
714 | + vdd3v3-supply = <&vreg_l13b_3p0>; |
715 | + vdd1v8-supply = <&vreg_l4b_1p8>; |
716 | + |
717 | + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; |
718 | + |
719 | + pinctrl-0 = <&eusb5_reset_n>; |
720 | + pinctrl-names = "default"; |
721 | + }; |
722 | + |
723 | + eusb3_repeater: redriver@47 { |
724 | + compatible = "nxp,ptn3222"; |
725 | + reg = <0x47>; |
726 | + #phy-cells = <0>; |
727 | + |
728 | + vdd3v3-supply = <&vreg_l13b_3p0>; |
729 | + vdd1v8-supply = <&vreg_l4b_1p8>; |
730 | + |
731 | + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; |
732 | + |
733 | + pinctrl-0 = <&eusb3_reset_n>; |
734 | + pinctrl-names = "default"; |
735 | + }; |
736 | + |
737 | + eusb6_repeater: redriver@4f { |
738 | + compatible = "nxp,ptn3222"; |
739 | + reg = <0x4f>; |
740 | + #phy-cells = <0>; |
741 | + |
742 | + vdd3v3-supply = <&vreg_l13b_3p0>; |
743 | + vdd1v8-supply = <&vreg_l4b_1p8>; |
744 | + |
745 | + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; |
746 | + |
747 | + pinctrl-0 = <&eusb6_reset_n>; |
748 | + pinctrl-names = "default"; |
749 | + }; |
750 | + }; |
751 | + |
752 | + &i2c7 { |
753 | + clock-frequency = <400000>; |
754 | + |
755 | + status = "okay"; |
756 | + |
757 | + typec-mux@8 { |
758 | + compatible = "parade,ps8830"; |
759 | + reg = <0x8>; |
760 | + |
761 | + clocks = <&rpmhcc RPMH_RF_CLK4>; |
762 | + clock-names = "xo"; |
763 | + |
764 | + vdd-supply = <&vreg_rtmr1_1p15>; |
765 | + vdd33-supply = <&vreg_rtmr1_3p3>; |
766 | + vdd33-cap-supply = <&vreg_rtmr1_3p3>; |
767 | + vddar-supply = <&vreg_rtmr1_1p15>; |
768 | + vddat-supply = <&vreg_rtmr1_1p15>; |
769 | + vddio-supply = <&vreg_rtmr1_1p8>; |
770 | + |
771 | + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; |
772 | + |
773 | + retimer-switch; |
774 | + orientation-switch; |
775 | + |
776 | + ports { |
777 | + #address-cells = <1>; |
778 | + #size-cells = <0>; |
779 | + |
780 | + port@0 { |
781 | + reg = <0>; |
782 | + |
783 | + retimer_ss1_ss_out: endpoint { |
784 | + remote-endpoint = <&pmic_glink_ss1_ss_in>; |
785 | + }; |
786 | + }; |
787 | + |
788 | + port@1 { |
789 | + reg = <1>; |
790 | + |
791 | + retimer_ss1_ss_in: endpoint { |
792 | + remote-endpoint = <&usb_1_ss1_qmpphy_out>; |
793 | + }; |
794 | + }; |
795 | + |
796 | + port@2 { |
797 | + reg = <2>; |
798 | + |
799 | + retimer_ss1_con_sbu_out: endpoint { |
800 | + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; |
801 | + }; |
802 | + }; |
803 | + |
804 | + }; |
805 | + }; |
806 | + }; |
807 | + |
808 | + &i2c8 { |
809 | + clock-frequency = <400000>; |
810 | + |
811 | + status = "okay"; |
812 | + |
813 | + /* ILIT2911 or GTCH1563 */ |
814 | + touchscreen@10 { |
815 | + compatible = "hid-over-i2c"; |
816 | + reg = <0x10>; |
817 | + |
818 | + hid-descr-addr = <0x1>; |
819 | + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; |
820 | + |
821 | + pinctrl-0 = <&ts0_default>; |
822 | + pinctrl-names = "default"; |
823 | + }; |
824 | + }; |
825 | + |
826 | +&i2c20 { |
827 | + clock-frequency = <400000>; |
828 | + |
829 | + status = "okay"; |
830 | + |
831 | +}; |
832 | + |
833 | + &lpass_tlmm { |
834 | + spkr_01_sd_n_active: spkr-01-sd-n-active-state { |
835 | + pins = "gpio12"; |
836 | + function = "gpio"; |
837 | + drive-strength = <16>; |
838 | + bias-disable; |
839 | + output-low; |
840 | + }; |
841 | + }; |
842 | + |
843 | + &lpass_vamacro { |
844 | + pinctrl-0 = <&dmic01_default>; |
845 | + pinctrl-names = "default"; |
846 | + |
847 | + vdd-micb-supply = <&vreg_l1b_1p8>; |
848 | + qcom,dmic-sample-rate = <4800000>; |
849 | + }; |
850 | + |
851 | + &mdss { |
852 | + status = "okay"; |
853 | + }; |
854 | + |
855 | + &mdss_dp0 { |
856 | + status = "okay"; |
857 | + }; |
858 | + |
859 | + &mdss_dp0_out { |
860 | + data-lanes = <0 1>; |
861 | + }; |
862 | + |
863 | + &mdss_dp1 { |
864 | + status = "okay"; |
865 | + }; |
866 | + |
867 | + &mdss_dp1_out { |
868 | + data-lanes = <0 1>; |
869 | + }; |
870 | + |
871 | + &mdss_dp3 { |
872 | + compatible = "qcom,x1e80100-dp"; |
873 | + /delete-property/ #sound-dai-cells; |
874 | + |
875 | + status = "okay"; |
876 | + |
877 | + aux-bus { |
878 | + panel { |
879 | + compatible = "edp-panel"; |
880 | + power-supply = <&vreg_edp_3p3>; |
881 | + |
882 | + backlight = <&backlight>; |
883 | + |
884 | + port { |
885 | + edp_panel_in: endpoint { |
886 | + remote-endpoint = <&mdss_dp3_out>; |
887 | + }; |
888 | + }; |
889 | + }; |
890 | + }; |
891 | + |
892 | + ports { |
893 | + port@1 { |
894 | + reg = <1>; |
895 | + |
896 | + mdss_dp3_out: endpoint { |
897 | + data-lanes = <0 1 2 3>; |
898 | + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; |
899 | + |
900 | + remote-endpoint = <&edp_panel_in>; |
901 | + }; |
902 | + }; |
903 | + }; |
904 | + }; |
905 | + |
906 | + &mdss_dp3_phy { |
907 | + vdda-phy-supply = <&vreg_l3j_0p8>; |
908 | + vdda-pll-supply = <&vreg_l2j_1p2>; |
909 | + |
910 | + status = "okay"; |
911 | + }; |
912 | + |
913 | + &pcie4 { |
914 | + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; |
915 | + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; |
916 | + |
917 | + pinctrl-0 = <&pcie4_default>; |
918 | + pinctrl-names = "default"; |
919 | + |
920 | + status = "okay"; |
921 | + }; |
922 | + |
923 | + &pcie4_phy { |
924 | + vdda-phy-supply = <&vreg_l3i_0p8>; |
925 | + vdda-pll-supply = <&vreg_l3e_1p2>; |
926 | + |
927 | + status = "okay"; |
928 | + }; |
929 | + |
930 | + &pcie6a { |
931 | + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; |
932 | + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; |
933 | + |
934 | + vddpe-3v3-supply = <&vreg_nvme>; |
935 | + |
936 | + pinctrl-0 = <&pcie6a_default>; |
937 | + pinctrl-names = "default"; |
938 | + |
939 | + status = "okay"; |
940 | + }; |
941 | + |
942 | + &pcie6a_phy { |
943 | + vdda-phy-supply = <&vreg_l1d_0p8>; |
944 | + vdda-pll-supply = <&vreg_l2j_1p2>; |
945 | + |
946 | + status = "okay"; |
947 | + }; |
948 | + |
949 | + &pm8550_gpios { |
950 | + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { |
951 | + pins = "gpio11"; |
952 | + function = "normal"; |
953 | + bias-disable; |
954 | + }; |
955 | + }; |
956 | + |
957 | + &pm8550ve_9_gpios { |
958 | + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { |
959 | + pins = "gpio8"; |
960 | + function = "normal"; |
961 | + bias-disable; |
962 | + }; |
963 | + }; |
964 | + |
965 | + &pmc8380_3_gpios { |
966 | + edp_bl_en: edp-bl-en-state { |
967 | + pins = "gpio4"; |
968 | + function = "normal"; |
969 | + power-source = <1>; |
970 | + input-disable; |
971 | + output-enable; |
972 | + }; |
973 | + |
974 | + edp_bl_reg_en: edp-bl-reg-en-state { |
975 | + pins = "gpio10"; |
976 | + function = "normal"; |
977 | + }; |
978 | + |
979 | + }; |
980 | + |
981 | + &pmk8550_gpios { |
982 | + edp_bl_pwm: edp-bl-pwm-state { |
983 | + pins = "gpio5"; |
984 | + function = "func3"; |
985 | + }; |
986 | + }; |
987 | + |
988 | + &pmk8550_pwm { |
989 | + status = "okay"; |
990 | + }; |
991 | + |
992 | + &pmc8380_5_gpios { |
993 | + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { |
994 | + pins = "gpio8"; |
995 | + function = "normal"; |
996 | + bias-disable; |
997 | + }; |
998 | + }; |
999 | + |
1000 | + &qupv3_0 { |
1001 | + status = "okay"; |
1002 | + }; |
1003 | + |
1004 | + &qupv3_1 { |
1005 | + status = "okay"; |
1006 | + }; |
1007 | + |
1008 | + &qupv3_2 { |
1009 | + status = "okay"; |
1010 | + }; |
1011 | + |
1012 | + &remoteproc_adsp { |
1013 | + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcadsp8380.mbn", |
1014 | + "qcom/x1e80100/ACER/SF14-11/adsp_dtbs.elf"; |
1015 | + |
1016 | + status = "okay"; |
1017 | + }; |
1018 | + |
1019 | + &remoteproc_cdsp { |
1020 | + firmware-name = "qcom/x1e80100/ACER/SF14-11/qccdsp8380.mbn", |
1021 | + "qcom/x1e80100/ACER/SF14-11/cdsp_dtbs.elf"; |
1022 | + |
1023 | + status = "okay"; |
1024 | + }; |
1025 | + |
1026 | + &smb2360_0_eusb2_repeater { |
1027 | + vdd18-supply = <&vreg_l3d_1p8>; |
1028 | + vdd3-supply = <&vreg_l2b_3p0>; |
1029 | + }; |
1030 | + |
1031 | + &smb2360_1_eusb2_repeater { |
1032 | + vdd18-supply = <&vreg_l3d_1p8>; |
1033 | + vdd3-supply = <&vreg_l14b_3p0>; |
1034 | + }; |
1035 | + &swr0 { |
1036 | + status = "okay"; |
1037 | + |
1038 | + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; |
1039 | + pinctrl-names = "default"; |
1040 | + |
1041 | + /* WSA8845, Left Speaker */ |
1042 | + left_spkr: speaker@0,0 { |
1043 | + compatible = "sdw20217020400"; |
1044 | + reg = <0 0>; |
1045 | + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; |
1046 | + #sound-dai-cells = <0>; |
1047 | + sound-name-prefix = "SpkrLeft"; |
1048 | + vdd-1p8-supply = <&vreg_l15b_1p8>; |
1049 | + vdd-io-supply = <&vreg_l12b_1p2>; |
1050 | + qcom,port-mapping = <1 2 3 7 10 13>; |
1051 | + }; |
1052 | + |
1053 | + /* WSA8845, Right Speaker */ |
1054 | + right_spkr: speaker@0,1 { |
1055 | + compatible = "sdw20217020400"; |
1056 | + reg = <0 1>; |
1057 | + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; |
1058 | + #sound-dai-cells = <0>; |
1059 | + sound-name-prefix = "SpkrRight"; |
1060 | + vdd-1p8-supply = <&vreg_l15b_1p8>; |
1061 | + vdd-io-supply = <&vreg_l12b_1p2>; |
1062 | + qcom,port-mapping = <4 5 6 7 11 13>; |
1063 | + }; |
1064 | + }; |
1065 | + |
1066 | + &swr1 { |
1067 | + status = "okay"; |
1068 | + |
1069 | + /* WCD9385 RX */ |
1070 | + wcd_rx: codec@0,4 { |
1071 | + compatible = "sdw20217010d00"; |
1072 | + reg = <0 4>; |
1073 | + qcom,rx-port-mapping = <1 2 3 4 5>; |
1074 | + }; |
1075 | + }; |
1076 | + |
1077 | + &swr2 { |
1078 | + status = "okay"; |
1079 | + |
1080 | + /* WCD9385 TX */ |
1081 | + wcd_tx: codec@0,3 { |
1082 | + compatible = "sdw20217010d00"; |
1083 | + reg = <0 3>; |
1084 | + qcom,tx-port-mapping = <2 2 3 4>; |
1085 | + }; |
1086 | + }; |
1087 | + |
1088 | + &tlmm { |
1089 | + gpio-reserved-ranges = <34 2>, /* Unused */ |
1090 | + <44 4>, /* SPI (TPM) */ |
1091 | + <72 2>, /* Secure EC I2C connection (?) */ |
1092 | + <238 1>; /* UFS Reset */ |
1093 | + |
1094 | + eusb3_reset_n: eusb3-reset-n-state { |
1095 | + pins = "gpio6"; |
1096 | + function = "gpio"; |
1097 | + drive-strength = <2>; |
1098 | + bias-disable; |
1099 | + output-low; |
1100 | + }; |
1101 | + |
1102 | + eusb5_reset_n: eusb5-reset-n-state { |
1103 | + pins = "gpio7"; |
1104 | + function = "gpio"; |
1105 | + drive-strength = <2>; |
1106 | + bias-disable; |
1107 | + output-low; |
1108 | + }; |
1109 | + |
1110 | + eusb6_reset_n: eusb6-reset-n-state { |
1111 | + pins = "gpio184"; |
1112 | + function = "gpio"; |
1113 | + drive-strength = <2>; |
1114 | + bias-disable; |
1115 | + output-low; |
1116 | + }; |
1117 | + |
1118 | + tpad_default: tpad-default-state { |
1119 | + pins = "gpio3"; |
1120 | + function = "gpio"; |
1121 | + bias-pull-up; |
1122 | + }; |
1123 | + |
1124 | + nvme_reg_en: nvme-reg-en-state { |
1125 | + pins = "gpio18"; |
1126 | + function = "gpio"; |
1127 | + drive-strength = <2>; |
1128 | + bias-disable; |
1129 | + }; |
1130 | + |
1131 | + ts0_default: ts0-default-state { |
1132 | + reset-n-pins { |
1133 | + pins = "gpio48"; |
1134 | + function = "gpio"; |
1135 | + output-high; |
1136 | + drive-strength = <16>; |
1137 | + }; |
1138 | + |
1139 | + int-n-pins { |
1140 | + pins = "gpio51"; |
1141 | + function = "gpio"; |
1142 | + bias-disable; |
1143 | + }; |
1144 | + }; |
1145 | + |
1146 | + kybd_default: kybd-default-state { |
1147 | + pins = "gpio67"; |
1148 | + function = "gpio"; |
1149 | + bias-disable; |
1150 | + }; |
1151 | + |
1152 | + bt_en_default: bt-en-sleep { |
1153 | + pins = "gpio116"; |
1154 | + function = "gpio"; |
1155 | + output-low; |
1156 | + bias-disable; |
1157 | + qcom,drive-strength = <16>; |
1158 | + }; |
1159 | + |
1160 | + edp_reg_en: edp-reg-en-state { |
1161 | + pins = "gpio70"; |
1162 | + function = "gpio"; |
1163 | + drive-strength = <16>; |
1164 | + bias-disable; |
1165 | + }; |
1166 | + |
1167 | + hall_int_n_default: hall-int-n-state { |
1168 | + pins = "gpio92"; |
1169 | + function = "gpio"; |
1170 | + bias-disable; |
1171 | + }; |
1172 | + |
1173 | + pcie4_default: pcie4-default-state { |
1174 | + clkreq-n-pins { |
1175 | + pins = "gpio147"; |
1176 | + function = "pcie4_clk"; |
1177 | + drive-strength = <2>; |
1178 | + bias-pull-up; |
1179 | + }; |
1180 | + |
1181 | + perst-n-pins { |
1182 | + pins = "gpio146"; |
1183 | + function = "gpio"; |
1184 | + drive-strength = <2>; |
1185 | + bias-disable; |
1186 | + }; |
1187 | + |
1188 | + wake-n-pins { |
1189 | + pins = "gpio148"; |
1190 | + function = "gpio"; |
1191 | + drive-strength = <2>; |
1192 | + bias-pull-up; |
1193 | + }; |
1194 | + }; |
1195 | + |
1196 | + pcie6a_default: pcie6a-default-state { |
1197 | + clkreq-n-pins { |
1198 | + pins = "gpio153"; |
1199 | + function = "pcie6a_clk"; |
1200 | + drive-strength = <2>; |
1201 | + bias-pull-up; |
1202 | + }; |
1203 | + |
1204 | + perst-n-pins { |
1205 | + pins = "gpio152"; |
1206 | + function = "gpio"; |
1207 | + drive-strength = <2>; |
1208 | + bias-disable; |
1209 | + }; |
1210 | + |
1211 | + wake-n-pins { |
1212 | + pins = "gpio154"; |
1213 | + function = "gpio"; |
1214 | + drive-strength = <2>; |
1215 | + bias-pull-up; |
1216 | + }; |
1217 | + }; |
1218 | + |
1219 | + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { |
1220 | + pins = "gpio188"; |
1221 | + function = "gpio"; |
1222 | + drive-strength = <2>; |
1223 | + bias-disable; |
1224 | + }; |
1225 | + |
1226 | + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { |
1227 | + pins = "gpio175"; |
1228 | + function = "gpio"; |
1229 | + drive-strength = <2>; |
1230 | + bias-disable; |
1231 | + }; |
1232 | + |
1233 | + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { |
1234 | + pins = "gpio186"; |
1235 | + function = "gpio"; |
1236 | + drive-strength = <2>; |
1237 | + bias-disable; |
1238 | + }; |
1239 | + |
1240 | + |
1241 | + wcd_default: wcd-reset-n-active-state { |
1242 | + pins = "gpio191"; |
1243 | + function = "gpio"; |
1244 | + drive-strength = <16>; |
1245 | + bias-disable; |
1246 | + output-low; |
1247 | + }; |
1248 | + }; |
1249 | + |
1250 | + &uart14 { |
1251 | + status = "okay"; |
1252 | + bluetooth: bt_wcn7850 { |
1253 | + compatible = "qcom,wcn7850-bt"; |
1254 | + pinctrl-names = "default"; |
1255 | + pinctrl-0 = <&bt_en_default>; |
1256 | + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; |
1257 | + max-speed = <3200000>; |
1258 | + }; |
1259 | + }; |
1260 | + |
1261 | + &usb_1_ss0_hsphy { |
1262 | + vdd-supply = <&vreg_l3j_0p8>; |
1263 | + vdda12-supply = <&vreg_l2j_1p2>; |
1264 | + |
1265 | + phys = <&smb2360_0_eusb2_repeater>; |
1266 | + |
1267 | + status = "okay"; |
1268 | + }; |
1269 | + |
1270 | + &usb_1_ss0_qmpphy { |
1271 | + vdda-phy-supply = <&vreg_l3e_1p2>; |
1272 | + vdda-pll-supply = <&vreg_l1j_0p8>; |
1273 | + |
1274 | + status = "okay"; |
1275 | + }; |
1276 | + |
1277 | + &usb_1_ss0 { |
1278 | + status = "okay"; |
1279 | + }; |
1280 | + |
1281 | + &usb_1_ss0_dwc3 { |
1282 | + dr_mode = "host"; |
1283 | + }; |
1284 | + |
1285 | + &usb_1_ss0_dwc3_hs { |
1286 | + remote-endpoint = <&pmic_glink_ss0_hs_in>; |
1287 | + }; |
1288 | + |
1289 | + &usb_1_ss0_qmpphy_out { |
1290 | + remote-endpoint = <&retimer_ss0_ss_in>; |
1291 | + }; |
1292 | + |
1293 | + &usb_1_ss1_hsphy { |
1294 | + vdd-supply = <&vreg_l3j_0p8>; |
1295 | + vdda12-supply = <&vreg_l2j_1p2>; |
1296 | + |
1297 | + phys = <&smb2360_1_eusb2_repeater>; |
1298 | + |
1299 | + status = "okay"; |
1300 | + }; |
1301 | + |
1302 | + &usb_1_ss1_qmpphy { |
1303 | + vdda-phy-supply = <&vreg_l3e_1p2>; |
1304 | + vdda-pll-supply = <&vreg_l2d_0p9>; |
1305 | + |
1306 | + status = "okay"; |
1307 | + }; |
1308 | + |
1309 | + &usb_1_ss1 { |
1310 | + status = "okay"; |
1311 | + }; |
1312 | + |
1313 | + &usb_1_ss1_dwc3 { |
1314 | + dr_mode = "host"; |
1315 | + }; |
1316 | + |
1317 | + &usb_1_ss1_dwc3_hs { |
1318 | + remote-endpoint = <&pmic_glink_ss1_hs_in>; |
1319 | + }; |
1320 | + |
1321 | + &usb_1_ss1_qmpphy_out { |
1322 | + remote-endpoint = <&retimer_ss1_ss_in>; |
1323 | + }; |
1324 | + |
1325 | + &usb_2 { |
1326 | + status = "okay"; |
1327 | + }; |
1328 | + |
1329 | + &usb_2_hsphy { |
1330 | + vdd-supply = <&vreg_l2e_0p8>; |
1331 | + vdda12-supply = <&vreg_l3e_1p2>; |
1332 | + |
1333 | + phys = <&eusb5_repeater>; |
1334 | + |
1335 | + status = "okay"; |
1336 | + }; |
1337 | + |
1338 | + &usb_mp { |
1339 | + status = "okay"; |
1340 | + }; |
1341 | + |
1342 | + &usb_mp_hsphy0 { |
1343 | + vdd-supply = <&vreg_l2e_0p8>; |
1344 | + vdda12-supply = <&vreg_l3e_1p2>; |
1345 | + |
1346 | + phys = <&eusb6_repeater>; |
1347 | + |
1348 | + status = "okay"; |
1349 | + }; |
1350 | + |
1351 | + &usb_mp_qmpphy0 { |
1352 | + vdda-phy-supply = <&vreg_l3e_1p2>; |
1353 | + vdda-pll-supply = <&vreg_l3c_0p8>; |
1354 | + |
1355 | + status = "okay"; |
1356 | + }; |
1357 | + |
1358 | + &usb_mp_hsphy1 { |
1359 | + vdd-supply = <&vreg_l2e_0p8>; |
1360 | + vdda12-supply = <&vreg_l3e_1p2>; |
1361 | + |
1362 | + phys = <&eusb3_repeater>; |
1363 | + |
1364 | + status = "okay"; |
1365 | + }; |
1366 | + |
1367 | + &usb_mp_qmpphy1 { |
1368 | + vdda-phy-supply = <&vreg_l3e_1p2>; |
1369 | + vdda-pll-supply = <&vreg_l3c_0p8>; |
1370 | + |
1371 | + status = "okay"; |
1372 | + }; |
Looks pretty good already! I left a few inline comments, in particular I'd like to get rid of all the leftover T14s mentions and get this into a state that we could send to the LKML for upstreaming.
If you upload a new version with those few comments addressed I will try to get this into our next kernel build.