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0f8c6c2... by Nicholas Kazlauskas <email address hidden> on 2021-11-04

drm/amd/display: Add callbacks for DMUB HPD IRQ notifications

[Why]
We need HPD IRQ notifications (RX, short pulse) to properly handle
DP MST for DPIA connections.

[How]
A null pointer exception currently occurs when these are received
so add a check to validate that we have a handler installed for
the notification.

Extend the HPD handler to also handle HPD IRQ (RX) since the logic is
the same.

Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")

Reviewed-by: Wayne Lin <email address hidden>
Reviewed-by: Jude Shih <email address hidden>
Acked-by: Anson Jacob <email address hidden>
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

5bf580c... by Nicholas Kazlauskas <email address hidden> on 2021-11-04

drm/amd/display: Don't lock connection_mutex for DMUB HPD

[Why]
Per DRM spec we only need to hold that lock when touching
connector->state - which we do not do in that handler.

Taking this locking introduces unnecessary dependencies with other
threads which is bad for performance and opens up the potential for
a deadlock since there are multiple locks being held at once.

[How]
Remove the connection_mutex lock/unlock routine and just iterate over
the drm connectors normally. The iter helpers implicitly lock the
connection list so this is safe to do.

DC link access also does not need to be guarded since the link
table is static at creation - we don't dynamically add or remove links,
just streams.

Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")

Reviewed-by: Jude Shih <email address hidden>
Acked-by: Anson Jacob <email address hidden>
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

7067239... by Richard Gong on 2021-10-27

drm/amd/display: MST support for DPIA

Backport the original commit d84755e5d0b476349ac2e96c91b5e615b4b00ea5 to
5.14.y kernel.

[Why]
- DPIA MST slot registers are not programmed during payload
  allocation and hence MST does not work with DPIA.
- HPD RX interrupts are not handled for DPIA.

[How]
- Added inbox command to program the MST slots whenever
  payload allocation happens for DPIA links.
- Added support for handling HPD RX interrupts

Signed-off-by: Richard Gong <email address hidden>
Signed-off-by: Meenakshikumar Somasundaram <email address hidden>
Reviewed-by: Jun Lei <email address hidden>
Acked-by: Nicholas Kazlauskas <email address hidden>
Change-Id: I14f727b0957973d10f4680db7666c7dbbd28ef59
Signed-off-by: You-Sheng Yang <email address hidden>

7c8d2dd... by Richard Gong on 2021-10-27

drm/amd/display: Set phy_mux_sel bit in dmub scratch register

Backport the original commit f90485176c9a41dc4184c90d53cc2a1feb663401 to
5.14.y kernel.

[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.

[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.

Signed-off-by: Richard Gong <email address hidden>
Cc: Wayne Lin <email address hidden>
Cc: Nicholas Kazlauskas <email address hidden>
Reviewed-by: Charlene Liu <email address hidden>
Acked-by: Rodrigo Siqueira <email address hidden>
Tested-by: Daniel Wheeler <email address hidden>
Signed-off-by: Hansen <email address hidden>
Change-Id: Ib8787e51454d2c62efd909b332d97fad55daebf2
Signed-off-by: You-Sheng Yang <email address hidden>

fd05e67... by Jude Shih <email address hidden> on 2021-10-15

dc: Enable dpia in dmub only for B0

[Why]
DMUB binary is common for both A0 and B0. Hence, driver should
intimate FW about the support for DPIA in B0.

[How]
Added dpia_supported bit in dmub_fw_boot_options and will be set
only for B0.

[CLEANED] Creating a fw boot options bit for an upcoming feature

[Why]
Need a bit for x86 driver to enable a FW boot option for an
upcoming feature.

[How]
Added a bit in dmub_fw_boot_options for an upcoming feature.

Signed-off-by: Jude Shih <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

7f96283... by Meenakshikumar Somasundaram <email address hidden> on 2021-09-10

drm/amd/display: Creating a fw boot options bit for an upcoming feature

[Why]
Need a bit for x86 driver to enable a FW boot option for an upcoming
feature.

[How]
Added a bit in dmub_fw_boot_options for an upcoming feature.

Reviewed-by: Jimmy Kizito <email address hidden>
Reviewed-by: Jun Lei <email address hidden>
Acked-by: Rodrigo Siqueira <email address hidden>
Signed-off-by: Meenakshikumar Somasundaram <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

47e252c... by Jude Shih <email address hidden> on 2021-10-14

drm/amd/display: Fix USB4 hot plug crash issue

[Why]
Notify data from outbox corrupt, the notify type should be 2 (HPD) instead of 0
(No data). We copied the address instead of the value. The memory might be
freed in the end of outbox IRQ

[How]
We should allocate the memory of notify and copy the whole content from outbox to
hpd handle function

Signed-off-by: Jude Shih <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

84580c1... by Mario Limonciello <email address hidden> on 2021-10-12

drm/amd/display: Fixup previous PSR policy commit

Commit ff06e2663509 ("drm/amd/display: Enable PSR by default on newer
DCN") relies upon IP version harvesting which isn't available until
5.16. For the backport of this commit, modify it to instead use
chip types (matching Van Gogh and Yellow Carp).

Signed-off-by: Mario Limonciello <email address hidden>
Change-Id: Ib50a2b278d644ad95c8cd7eeadcc496f6571c598
Signed-off-by: You-Sheng Yang <email address hidden>

f266258... by Nicholas Kazlauskas <email address hidden> on 2021-10-05

drm/amd/display: Enable PSR by default on newer DCN

[Why]
For optimal power savings on panels that can support it.

This was previously left disabled by default because of issues with
compositors that do not pageflip and scan out directly to the
frontbuffer.

For these compositors we now have detection methods that wait for x
number of pageflips after a full update - triggered by a buffer or
format change typically.

This may introduce bugs or new cases not tested by users so this is
only currently targeting newer DCN.

[How]
Add code in DM to set PSR state by default for newer DCN while falling
back to the feature mask for older.

Add a global debug flag that can be set to disable it for either.

Signed-off-by: Nicholas Kazlauskas <email address hidden>
Reviewed-by: Harry Wentland <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>

b135b74... by Nicholas Kazlauskas <email address hidden> on 2021-09-07

drm/amd/display: Add NULL checks for vblank workqueue

[Why]
If we're running a headless config with 0 links then the vblank
workqueue will be NULL - causing a NULL pointer exception during
any commit.

[How]
Guard access to the workqueue if it's NULL and don't queue or flush
work if it is.

Reported-by: Mike Lothian <email address hidden>
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1700
Fixes: 58aa1c50e5a231 ("drm/amd/display: Use vblank control events for PSR enable/disable")
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Reviewed-by: Harry Wentland <email address hidden>
Signed-off-by: Alex Deucher <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>