drm/amdgpu: support B0&B1 external revision id for yellow carp
B0 internal rev_id is 0x01, B1 internal rev_id is 0x02.
The external rev_id for B0 and B1 is 0x20.
The original expression is not suitable for B1.
Signed-off-by: Aaron Liu <email address hidden>
Reviewed-by: Huang Rui <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>
e6f517d...
by
Nicholas Kazlauskas <email address hidden>
drm/amd/display: Add callbacks for DMUB HPD IRQ notifications
[Why]
We need HPD IRQ notifications (RX, short pulse) to properly handle
DP MST for DPIA connections.
[How]
A null pointer exception currently occurs when these are received
so add a check to validate that we have a handler installed for
the notification.
Extend the HPD handler to also handle HPD IRQ (RX) since the logic is
the same.
Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")
Reviewed-by: Wayne Lin <email address hidden>
Reviewed-by: Jude Shih <email address hidden>
Acked-by: Anson Jacob <email address hidden>
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>
f9ff835...
by
Nicholas Kazlauskas <email address hidden>
drm/amd/display: Don't lock connection_mutex for DMUB HPD
[Why]
Per DRM spec we only need to hold that lock when touching
connector->state - which we do not do in that handler.
Taking this locking introduces unnecessary dependencies with other
threads which is bad for performance and opens up the potential for
a deadlock since there are multiple locks being held at once.
[How]
Remove the connection_mutex lock/unlock routine and just iterate over
the drm connectors normally. The iter helpers implicitly lock the
connection list so this is safe to do.
DC link access also does not need to be guarded since the link
table is static at creation - we don't dynamically add or remove links,
just streams.
Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")
Reviewed-by: Jude Shih <email address hidden>
Acked-by: Anson Jacob <email address hidden>
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>
Backport the original commit d84755e5d0b476349ac2e96c91b5e615b4b00ea5 to
5.14.y kernel.
[Why]
- DPIA MST slot registers are not programmed during payload
allocation and hence MST does not work with DPIA.
- HPD RX interrupts are not handled for DPIA.
[How]
- Added inbox command to program the MST slots whenever
payload allocation happens for DPIA links.
- Added support for handling HPD RX interrupts
Signed-off-by: Richard Gong <email address hidden>
Signed-off-by: Meenakshikumar Somasundaram <email address hidden>
Reviewed-by: Jun Lei <email address hidden>
Acked-by: Nicholas Kazlauskas <email address hidden>
Change-Id: I14f727b0957973d10f4680db7666c7dbbd28ef59
Signed-off-by: You-Sheng Yang <email address hidden>
5251804...
by
Nicholas Kazlauskas <email address hidden>
drm/amd/display: Fix deadlock when falling back to v2 from v3
[Why]
A deadlock in the kernel occurs when we fallback from the V3 to V2
add_topology_to_display or remove_topology_to_display because they
both try to acquire the dtm_mutex but recursive locking isn't
supported on mutex_lock().
[How]
Make the mutex_lock/unlock more fine grained and move them up such that
they're only required for the psp invocation itself.
Signed-off-by: Nicholas Kazlauskas <email address hidden>
Reviewed-by: Aric Cyr <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>
4daeff9...
by
Michael Strauss <email address hidden>
drm/amd/display: Fallback to clocks which meet requested voltage on DCN31
[WHY]
On certain configs, SMU clock table voltages don't match which cause parser
to behave incorrectly by leaving dcfclk and socclk table entries unpopulated.
[HOW]
Currently the function that finds the corresponding clock for a given voltage
only checks for exact voltage level matches. In the case that no match gets
found, parser now falls back to searching for the max clock which meets the
requested voltage (i.e. its corresponding voltage is below requested).
Signed-off-by: Michael Strauss <email address hidden>
Reviewed-by: Nicholas Kazlauskas <email address hidden>
Signed-off-by: You-Sheng Yang <email address hidden>
drm/amd/display: Set phy_mux_sel bit in dmub scratch register
Backport the original commit f90485176c9a41dc4184c90d53cc2a1feb663401 to
5.14.y kernel.
[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.
[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.
Signed-off-by: Richard Gong <email address hidden>
Cc: Wayne Lin <email address hidden>
Cc: Nicholas Kazlauskas <email address hidden>
Reviewed-by: Charlene Liu <email address hidden>
Acked-by: Rodrigo Siqueira <email address hidden>
Tested-by: Daniel Wheeler <email address hidden>
Signed-off-by: Hansen <email address hidden>
Change-Id: Ib8787e51454d2c62efd909b332d97fad55daebf2
Signed-off-by: You-Sheng Yang <email address hidden>
