$ perf record -e instructions:ppp -- true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (instructions:ppp).
The instruction PDIR is only available on the fixed counter 0. The event
constraint has been updated to fixed0_constraint in
icl_get_event_constraints(). The Sapphire Rapids codes unconditionally
error out for the event which is not available on the GP counter 0.
Make the instructions:ppp an exception.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Reported-by: Yasin, Ahmad <email address hidden>
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit 1d5c7880992a06679585e7e568cc679c0c5fd4f2)
Signed-off-by: You-Sheng Yang <email address hidden>
On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.
Update intel_spr_extra_regs[] to support them.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit d18216fafecf2a3a7c2b97086892269d6ab3cd5e)
Signed-off-by: You-Sheng Yang <email address hidden>
Current perf unconditionally increases the number of the GP counters and
the fixed counters for a big core PMU on an Alder Lake system, because
the number enumerated in the CPUID only reflects the common counters.
The big core may has more counters. However, Alder Lake may have an
alternative configuration. With that configuration,
the X86_FEATURE_HYBRID_CPU is not set. The number of the GP counters and
fixed counters enumerated in the CPUID is accurate. Perf mistakenly
increases the number of counters. The warning is triggered.
Directly use the enumerated value on the system with the alternative
configuration.
Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")
Reported-by: Jin Yao <email address hidden>
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit ee72a94ea4a6d8fa304a506859cd07ecdc0cf5c4)
Signed-off-by: You-Sheng Yang <email address hidden>
Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH
which cannot achieve PC10 without ignoring the PMC GBE LTR. Add this
work around for Alder Lake PCH as well.
Alder Lake has 14 status registers that are memory mapped. These
registers show the status of the low power mode requirements. The
registers are latched on every C10 entry or exit and on every s0ix.y
entry/exit. Accessing these registers is useful for debugging any low
power related activities.
Thus, add debugfs entry to access low power mode status registers.
Cc: Srinivas Pandruvada <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David Box <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
(cherry picked from https://patchwork.kernel.org/project/platform-driver-x86/patch/f31f15ec9c1e6ee72bb8525c64878d222e1fa09e<email address hidden>/)
Signed-off-by: You-Sheng Yang <email address hidden>
Signed-off-by: Timo Aaltonen <email address hidden>
145208a...
by
Gayatri Kammela <email address hidden>
UBUNTU: SAUCE: platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake
Add support to show the Latency Tolerance Reporting for the IPs on
the Alder Lake PCH as reported by the PMC. This LTR support on
Alder Lake is slightly different from the Cannon lake PCH that is being
reused by all platforms till Tiger Lake.
Cc: Srinivas Pandruvada <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David Box <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
(cherry picked from https://patchwork.kernel.org/project/platform-driver-x86/patch/0b1409212c2f84aa807e5315955c8e74903d031a<email address hidden>/)
Signed-off-by: You-Sheng Yang <email address hidden>
Signed-off-by: Timo Aaltonen <email address hidden>
ced6622...
by
Gayatri Kammela <email address hidden>
UBUNTU: SAUCE: platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
