$ perf record -e instructions:ppp -- true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (instructions:ppp).
The instruction PDIR is only available on the fixed counter 0. The event
constraint has been updated to fixed0_constraint in
icl_get_event_constraints(). The Sapphire Rapids codes unconditionally
error out for the event which is not available on the GP counter 0.
Make the instructions:ppp an exception.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Reported-by: Yasin, Ahmad <email address hidden>
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit 1d5c7880992a06679585e7e568cc679c0c5fd4f2)
Signed-off-by: You-Sheng Yang <email address hidden>
On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.
Update intel_spr_extra_regs[] to support them.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit d18216fafecf2a3a7c2b97086892269d6ab3cd5e)
Signed-off-by: You-Sheng Yang <email address hidden>
Current perf unconditionally increases the number of the GP counters and
the fixed counters for a big core PMU on an Alder Lake system, because
the number enumerated in the CPUID only reflects the common counters.
The big core may has more counters. However, Alder Lake may have an
alternative configuration. With that configuration,
the X86_FEATURE_HYBRID_CPU is not set. The number of the GP counters and
fixed counters enumerated in the CPUID is accurate. Perf mistakenly
increases the number of counters. The warning is triggered.
Directly use the enumerated value on the system with the alternative
configuration.
Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")
Reported-by: Jin Yao <email address hidden>
Signed-off-by: Kan Liang <email address hidden>
Signed-off-by: Peter Zijlstra (Intel) <email address hidden>
Cc: <email address hidden>
Link: https://<email address hidden>
(cherry picked from commit ee72a94ea4a6d8fa304a506859cd07ecdc0cf5c4)
Signed-off-by: You-Sheng Yang <email address hidden>
mm/page_alloc: Correct return value of populated elements if bulk array is populated
Dave Jones reported the following
This made it into 5.13 final, and completely breaks NFSD for me
(Serving tcp v3 mounts). Existing mounts on clients hang, as do
new mounts from new clients. Rebooting the server back to rc7
everything recovers.
The commit b3b64ebd3822 ("mm/page_alloc: do bulk array bounds check after
checking populated elements") returns the wrong value if the array is
already populated which is interpreted as an allocation failure. Dave
reported this fixes his problem and it also passed a test running dbench
over NFS.
Fixes: b3b64ebd3822 ("mm/page_alloc: do bulk array bounds check after checking populated elements")
Reported-and-tested-by: Dave Jones <email address hidden>
Signed-off-by: Mel Gorman <email address hidden>
Cc: <email address hidden> [5.13+]
Signed-off-by: Linus Torvalds <email address hidden>
(cherry picked from commit 66d9282523b3228183b14d9f812872dd2620704d)
Signed-off-by: Andrea Righi <email address hidden>
