Input: i8042 - add Fujitsu Lifebook UH554 to nomux/notimeout list
Similar to AH544, without these quirks, the touchpad is not responsive
on this product. Add it to the nomux/notimeout list alongside other
similar Fujitsu laptops.
When the reference clock is 38.4MHz, using the current TBT PLL
fractional divider value results in a slightly off TBT link frequency.
This causes an endless loop of link training success followed by a bad
link signaling and retraining at least on a Dell WD19TB TBT dock. The
workaround provided by the HW team is to divide the fractional divider
value by two. This fixed the link training problem on the ThinkPad dock.
The same workaround is needed on some EHL platforms and for combo PHY
PLLs, these will be addressed in a follow-up.
MST encoders must use the master MST transcoder's DP_TP_STATUS and
DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder
connected to a slave transcoder we reset these register addresses in
intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register
addresses incorrectly; fix this.
One example where the above overwite happens is the encoder HW state
validation after enabling multiple streams; see
intel_dp_mst_enc_get_config(). After that during disabling any stream
we'll get a
'Timed out waiting for ACT sent when disabling'
error, due to reading from the incorrect DP_TP_STATUS register.
A recent change in BSpec allow us to change EXTLINE while transcoder
is enabled so this allow us to change it even when doing the first
fastset after taking over previous hardware state set by BIOS.
BIOS don't enable PSR, so if sink supports PSR it will be enabled on
the first fastset, so moving the EXTLINE compute and set to PSR flows
allow us to simplfy a bunch of code.
This will save a lot of time in all the IGT tests that uses CRC, as
when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so
the previous code would compute dc3co_exitline=0 causing a full
modeset that would shutdown pipe, enable and train link.
v2: only programming EXTLINE when DC3CO is enabled
BSpec: 49196
Cc: Imre Deak <email address hidden>
Cc: Anshuman Gupta <email address hidden>
Reviewed-by: Anshuman Gupta <email address hidden>
Signed-off-by: José Roberto de Souza <email address hidden>
Link: https://patchwork<email address hidden>
(cherry picked from commit c5c772cf8d7cb68701b1c7fb9956857e646ae4b1 drm-tip)
Signed-off-by: Hsuan-Yu Lin <email address hidden>
Signed-off-by: Timo Aaltonen <email address hidden>
76d9a5c...
by
=?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= <email address hidden>
drm/i915/tgl: Add HBR and HBR2+ voltage swing table
As latest update we have now 2 voltage swing tables for DP over DKL
PHY with only one difference in Level 0 pre-emphasis 3.
So with 2 tables for DP is time to have one single function to return
all DKL voltage swing tables.
BSpec: 49292
Cc: Khaled Almahallawy <email address hidden>
Signed-off-by: José Roberto de Souza <email address hidden>
Tested-by: Khaled Almahallawy <email address hidden>
Reviewed-by: Khaled Almahallawy<email address hidden>
Link: https://patchwork<email address hidden>
(cherry picked from commit 9fa6769952ee14250bb7107a2ec66062d2ccae1e drm-tip)
Signed-off-by: Hsuan-Yu Lin <email address hidden>
Signed-off-by: Timo Aaltonen <email address hidden>
