b251d11...
by
Jarkko Nikula <email address hidden>
i2c: i801: Add support for Intel Comet Lake PCH-V
Add support for Intel Comet Lake PCH-V which is based on Intel Kaby
Lake. Difference between it and other Comet Lake variants is that former
uses previous iTCO version 4 and latter use version 6 like Intel Cannon
Lake PCH.
Signed-off-by: Jarkko Nikula <email address hidden>
Reviewed-by: Jean Delvare <email address hidden>
Signed-off-by: Wolfram Sang <email address hidden>
(backported from commit f53938d2c79ae3c768dc92b1c3d898dfe820a491)
Signed-off-by: You-Sheng Yang <email address hidden>
c35edbc...
by
Jarkko Nikula <email address hidden>
spi: pxa2xx: Add support for Intel Comet Lake PCH-V
Add support for Intel Comet Lake PCH-V which has the same LPSS than on
Intel Kaby lake unlike other Intel Comet Lake PCH variants that are based
on Intel Cannon Lake PCH LPSS.
Signed-off-by: Jarkko Nikula <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Mark Brown <email address hidden>
(cherry picked from commit 6157d4c255609da28f5a271ec1d56d74beb4c8be)
Signed-off-by: You-Sheng Yang <email address hidden>
a4aed94...
by
Andy Shevchenko <email address hidden>
mfd: intel-lpss: Add Intel Comet Lake PCH-V PCI IDs
Intel Comet Lake PCH-V has the same LPSS than Intel Kaby Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from
https://<email address hidden>/)
Signed-off-by: You-Sheng Yang <email address hidden>
a30d514...
by
Mika Westerberg <email address hidden>
mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-V SPI serial flash
Intel Comet Lake-V has the same SPI serial flash controller as Kaby
Lake. Add Comet Lake-V PCI ID to the driver list of supported devices.
Signed-off-by: Mika Westerberg <email address hidden>
Signed-off-by: Tudor Ambarus <email address hidden>
(cherry picked from commit 701a1676f313dbae578f31da4e06c5487c8aa7bb)
Signed-off-by: You-Sheng Yang <email address hidden>
08623b9...
by
Mika Westerberg <email address hidden>
pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
Intel Coffee Lake-S PCH has the same GPIO hardware than Sunrisepoint-H
PCH but the ACPI ID is different. Add this new ACPI ID to the list of
supported devices.
Signed-off-by: Mika Westerberg <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 899b7e3374b253888b048dd06338e043e4b7637c)
Signed-off-by: You-Sheng Yang <email address hidden>
Depending on the current link state the steps to resume the link to U0
varies. The normal case when a port is suspended (U3) we set the link
to U0 and wait for a port event when U3exit completed and port moved to
U0.
If the port is in U1/U2, then no event is issued, just set link to U0
If port is in Resume or Recovery state then the device has already
initiated resume, and this host initiated resume is racing against it.
Port event handler for device initiated resume will set link to U0,
just wait for the port to reach U0 before returning.
The xHCI spec doesn't specify the upper bound of U3 transition time. For
some devices 20ms is not enough, so we need to make sure the link state
is in U3 before further actions.
I've tried to use U3 Entry Capability by setting U3 Entry Enable in
config register, however the port change event for U3 transition
interrupts the system suspend process.
For now let's use the less ideal method by polling PLS.
[use usleep_range(), and shorten the delay time while polling -Mathias]
Signed-off-by: Kai-Heng Feng <email address hidden>
Signed-off-by: Mathias Nyman <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Greg Kroah-Hartman <email address hidden>
(cherry picked from commit eb002726fac7cefb98ff39ddb89e150a1c24fe85 linux-next)
Signed-off-by: Kai-Heng Feng <email address hidden>
Signed-off-by: Seth Forshee <email address hidden>
