b6a2a99...
by
Andy Shevchenko <email address hidden>
mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDs
Intel Comet Lake PCH-H has the same LPSS than Intel Cannon Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <email address hidden>
Signed-off-by: Lee Jones <email address hidden>
(cherry picked from commit dd047dce3a6f5233b98e792e2287cc549da35879)
Signed-off-by: You-Sheng Yang <email address hidden>
185726f...
by
Mika Westerberg <email address hidden>
mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flash
Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet
Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices.
Signed-off-by: Mika Westerberg <email address hidden>
Signed-off-by: Tudor Ambarus <email address hidden>
(cherry picked from commit 5a0feb6287e37018af4cbd7754786522ae712980)
Signed-off-by: You-Sheng Yang <email address hidden>
96c5731...
by
Jarkko Nikula <email address hidden>
i2c: i801: Add support for Intel Comet Lake PCH-H
Add support for another Intel Comet Lake variant.
Signed-off-by: Jarkko Nikula <email address hidden>
Reviewed-by: Jean Delvare <email address hidden>
Signed-off-by: Wolfram Sang <email address hidden>
(backported from commit 07f047e3fe33aefa44c34ed797b79f0415244202)
Signed-off-by: You-Sheng Yang <email address hidden>
UBUNTU: [Config] Disable TSX by default when possible
Turn on CONFIG_X86_INTEL_TSX_MODE_OFF to disable Intel's Transactional
Synchronization Extensions (TSX) feature by default. TSX can only be
disable on certain, newer processors that support the IA32_TSX_CTRL MSR
via a microcode update. Intel says that future processors will also
support the MSR. On processors that support the MSR, TSX will be
disabled unless the system administrator overrides the configuration
with the "tsx" kernel command line option.
CVE-2019-11135
Based on master commit b9665b885ab310744d8ae53d6860782ec7851613.