x86/tsc: set LAPIC timer frequency to crystal clock frequency
The APIC timer calibration (calibrate_APIC_timer()) can be skipped
in cases where we know the APIC timer frequency. On Intel SoCs,
we believe that the APIC is fed by the crystal clock; this would make
sense, and the crystal clock frequency has been verified against the
APIC timer calibration result on ApolloLake, GeminiLake, Kabylake,
CoffeeLake, WhiskeyLake and AmberLake.
Set lapic_timer_frequency based on the crystal clock frequency
accordingly.
APIC timer calibration would normally be skipped on modern CPUs
by nature of the TSC deadline timer being used instead,
however this change is still potentially useful, e.g. if the
TSC deadline timer has been disabled with a kernel parameter.
calibrate_APIC_timer() uses the legacy timer, but we are seeing
new platforms that omit such legacy functionality, so avoiding
such codepaths is becoming more important.
Link: https://<email address hidden>
Link: https://<email address hidden>
Suggested-by: Thomas Gleixner <email address hidden>
Signed-off-by: Daniel Drake <email address hidden>
x86/tsc: use CPUID.0x16 to calculate missing crystal frequency
native_calibrate_tsc() had a hardcoded table of Intel CPU families
and crystal clock, but we have found that it is possible to
calculate the crystal clock speed, and this is preferred to a hardcoded
table.
Where crystal clock frequency was not reported by CPUID.0x15,
use CPUID.0x16 data to calculate the crystal clock.
Using CPUID dump data from http://instlatx64.atw.hu/, the calculation
results can be seen to be sufficiently close to the previously hardcoded
values:
SKYLAKE_MOBILE: 24074074 Hz
SKYLAKE_DESKTOP: 23913043 Hz
KABYLAKE_MOBILE: 23893805 Hz
KABYLAKE_DESKTOP: 24050632 Hz
GOLDMONT: 19.2MHz crystal clock correctly reported by CPUID.0x15
Additionally, crystal clock frequency for platforms that were missing
from the list (e.g. SKYLAKE_X) will now be provided.
GOLDMONT_X was left as a hardcoded value, as the CPUID data on that site
indicates that the hardware does not report crystal clock nor CPUID.0x16
data.
Going forward, Intel have hopefully now started providing crystal
frequency in CPUID.0x15. At least ApolloLake, GeminiLake and CannonLake
CPUs all provide the relevant data directly.
Link: https://<email address hidden>
Suggested-by: Thomas Gleixner <email address hidden>
Signed-off-by: Daniel Drake <email address hidden>
Workaround problem with Samba responses to SMB3.1.1
null user (guest) mounts. The server doesn't set the
expected flag in the session setup response so we have
to do a similar check to what is done in smb3_validate_negotiate
where we also check if the user is a null user (but not sec=krb5
since username might not be passed in on mount for Kerberos case).
Note that the commit below tightened the conditions and forced signing
for the SMB2-TreeConnect commands as per MS-SMB2.
However, this should only apply to normal user sessions and not for
cases where there is no user (even if server forgets to set the flag
in the response) since we don't have anything useful to sign with.
This is especially important now that the more secure SMB3.1.1 protocol
is in the default dialect list.
An earlier patch ("cifs: allow guest mounts to work for smb3.11") fixed
the guest mounts to Windows.
Fixes: 6188f28bf608 ("Tree connect for SMB3.1.1 must be signed for non-encrypted shares")
Reviewed-by: Ronnie Sahlberg <email address hidden>
Reviewed-by: Paulo Alcantara <email address hidden>
CC: Stable <email address hidden>
Signed-off-by: Steve French <email address hidden>
(cherry picked from commit 8c11a607d1d9cd6e7f01fd6b03923597fb0ef95a)
Signed-off-by: Tyler Hicks <email address hidden>
Signed-off-by: Seth Forshee <email address hidden>
961b0e3...
by
Ronnie Sahlberg <email address hidden>
Fix Guest/Anonymous sessions so that they work with SMB 3.11.
The commit noted below tightened the conditions and forced signing for
the SMB2-TreeConnect commands as per MS-SMB2.
However, this should only apply to normal user sessions and not for
Guest/Anonumous sessions.
Fixes: 6188f28bf608 ("Tree connect for SMB3.1.1 must be signed for non-encrypted shares")
Signed-off-by: Ronnie Sahlberg <email address hidden>
CC: Stable <email address hidden>
Signed-off-by: Steve French <email address hidden>
(cherry picked from commit e71ab2aa06f731a944993120b0eef1556c63b81c)
Signed-off-by: Tyler Hicks <email address hidden>
Signed-off-by: Seth Forshee <email address hidden>
3754856...
by
Xiongfeng Wang <email address hidden>
cpufreq / cppc: Work around for Hisilicon CPPC cpufreq
Hisilicon chips do not support delivered performance counter register
and reference performance counter register. But the platform can
calculate the real performance using its own method. We reuse the
desired performance register to store the real performance calculated by
the platform. After the platform finished the frequency adjust, it gets
the real performance and writes it into desired performance register. Os
can use it to calculate the real frequency.
Signed-off-by: Xiongfeng Wang <email address hidden>
[ rjw: Drop unnecessary braces ]
Signed-off-by: Rafael J. Wysocki <email address hidden>
(cherry picked from commit 6c8d750f9784cef32a8cffdad74c8a351b4ca3a6)
Signed-off-by: dann frazier <email address hidden>
Signed-off-by: Seth Forshee <email address hidden>
c5817e9...
by
Xiongfeng Wang <email address hidden>
ACPI / CPPC: Add a helper to get desired performance
This patch add a helper to get the value of desired performance
register.
Signed-off-by: Xiongfeng Wang <email address hidden>
[ rjw: More white space ]
Signed-off-by: Rafael J. Wysocki <email address hidden>
(cherry picked from commit 1757d05f3112acc5c0cdbcccad3afdee99655bf9)
Signed-off-by: dann frazier <email address hidden>
Signed-off-by: Seth Forshee <email address hidden>
This patch provides a /proc/<pid>/attr/apparmor/
subdirectory. Enabling userspace to use the apparmor attributes
without having to worry about collisions with selinux or smack on
interface files in /proc/<pid>/attr.
