lp:~vcs-imports/mesa/trunk

Created by Jelmer Vernooij on 2011-06-06 and last modified on 2017-06-27
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Branch information

Owner:
VCS imports
Project:
Mesa
Status:
Development

Import details

Import Status: Reviewed

This branch is an import of the HEAD branch of the Git repository at git://anongit.freedesktop.org/mesa/mesa.git.

The next import is scheduled to run in 2 hours.

Last successful import was 3 hours ago.

Import started 3 hours ago on pear and finished 3 hours ago taking 1 minute — see the log
Import started 3 hours ago on russkaya and finished 3 hours ago taking 7 minutes
Import started 9 hours ago on russkaya and finished 9 hours ago taking 2 minutes — see the log
Import started 15 hours ago on pear and finished 15 hours ago taking 1 minute — see the log
Import started 21 hours ago on pear and finished 21 hours ago taking 1 minute — see the log
Import started on 2017-06-27 on pear and finished on 2017-06-27 taking 1 minute — see the log
Import started on 2017-06-26 on pear and finished on 2017-06-26 taking 1 minute — see the log
Import started on 2017-06-26 on russkaya and finished on 2017-06-26 taking 2 minutes — see the log
Import started on 2017-06-26 on pear and finished on 2017-06-26 taking 1 minute — see the log
Import started on 2017-06-26 on pear and finished on 2017-06-26 taking 1 minute — see the log

Recent revisions

69243. By Marek Olšák <email address hidden> 9 hours ago

radeonsi: move instance divisors into a constant buffer

Shader key size: 107 -> 47

Divisors of 0 and 1 are encoded in the shader key. Greater instance divisors
are loaded from a constant buffer.

The shader code doing the division is huge. Is it something we need to
worry about? Does any app use instance divisors >= 2?

VS prolog disassembly:
    s_load_dwordx4 s[12:15], s[0:1], 0x80 ; C00A0300 00000080
    s_nop 0 ; BF800000
    s_waitcnt lgkmcnt(0) ; BF8C007F
    s_buffer_load_dword s14, s[12:15], 0x4 ; C0220386 00000004
    s_waitcnt lgkmcnt(0) ; BF8C007F
    v_cvt_f32_u32_e32 v4, s14 ; 7E080C0E
    v_rcp_iflag_f32_e32 v4, v4 ; 7E084704
    v_mul_f32_e32 v4, 0x4f800000, v4 ; 0A0808FF 4F800000
    v_cvt_u32_f32_e32 v4, v4 ; 7E080F04
    v_mul_hi_u32 v5, v4, s14 ; D2860005 00001D04
    v_mul_lo_i32 v6, v4, s14 ; D2850006 00001D04
    v_cmp_eq_u32_e64 s[12:13], 0, v5 ; D0CA000C 00020A80
    v_sub_i32_e32 v5, vcc, 0, v6 ; 340A0C80
    v_cndmask_b32_e64 v5, v6, v5, s[12:13] ; D1000005 00320B06
    v_mul_hi_u32 v5, v5, v4 ; D2860005 00020905
    v_add_i32_e32 v6, vcc, v5, v4 ; 320C0905
    v_subrev_i32_e32 v4, vcc, v5, v4 ; 36080905
    v_cndmask_b32_e64 v4, v4, v6, s[12:13] ; D1000004 00320D04
    v_mul_hi_u32 v5, v4, v1 ; D2860005 00020304
    v_add_i32_e32 v4, vcc, s8, v0 ; 32080008
    v_mul_lo_i32 v6, v5, s14 ; D2850006 00001D05
    v_add_i32_e32 v7, vcc, 1, v5 ; 320E0A81
    v_cmp_ge_u32_e64 s[12:13], v1, v6 ; D0CE000C 00020D01
    v_sub_i32_e32 v6, vcc, v1, v6 ; 340C0D01
    v_cmp_le_u32_e32 vcc, s14, v6 ; 7D960C0E
    v_cndmask_b32_e64 v8, 0, -1, s[12:13] ; D1000008 00318280
    v_cndmask_b32_e64 v6, 0, -1, vcc ; D1000006 01A98280
    v_and_b32_e32 v6, v8, v6 ; 260C0D08
    v_cmp_eq_u32_e32 vcc, 0, v6 ; 7D940C80
    v_cndmask_b32_e32 v6, v7, v5, vcc ; 000C0B07
    v_add_i32_e32 v5, vcc, -1, v5 ; 320A0AC1
    v_cmp_eq_u32_e32 vcc, 0, v8 ; 7D941080
    v_cndmask_b32_e32 v5, v6, v5, vcc ; 000A0B06
    v_add_i32_e32 v5, vcc, s9, v5 ; 320A0A09

v2: set prefer_mono for fetched instance divisors

Reviewed-by: Nicolai Hähnle <email address hidden>

69242. By Marek Olšák <email address hidden> 10 hours ago

radeonsi: check nr_cbufs in other places before flushing CB

Reviewed-by: Nicolai Hähnle <email address hidden>

69241. By Marek Olšák <email address hidden> 10 hours ago

radeonsi: use #pragma pack to pack si_shader_key

sizeof(struct si_shader_key):
  Before reverting the 2 commits: 120 bytes
  After reverting the 2 commits: 128 bytes
  With #pragma pack: 107 bytes

Reviewed-by: Nicolai Hähnle <email address hidden>

69240. By Marek Olšák <email address hidden> 10 hours ago

Revert "radeonsi: use uint32_t to declare si_shader_key.opt.kill_outputs"

This reverts commit 7b2240ac9ce3ba9bd86f4ae8aac53af8878c0b10.

Reviewed-by: Nicolai Hähnle <email address hidden>

69239. By Marek Olšák <email address hidden> 10 hours ago

Revert "radeonsi: remove 8 bytes from si_shader_key with uint32_t ff_tcs_inputs_to_copy"

This reverts commit 6b6fed3a3c81c2b0d319ef121df20a0dc914705f.

Reviewed-by: Nicolai Hähnle <email address hidden>

69238. By Marek Olšák <email address hidden> 10 hours ago

mesa: optimize GL_PRIMITIVE_RESTART_NV more

And other client state changes don't have to call
update_derived_primitive_restart_state.

Reviewed-by: Nicolai Hähnle <email address hidden>

69237. By Marek Olšák <email address hidden> 10 hours ago

mesa: fix clip plane enable breakage

Broken by:

commit 00173d91b70ae4dcea7c6324ee4858c498cae14b
Author: Marek Olšák <email address hidden>
Date: Sat Jun 10 12:09:43 2017 +0200

    mesa: don't flag _NEW_TRANSFORM for st/mesa if possible

It also optimizes the case slightly for GL core.

It doesn't try to fix that glEnable might be a bad place to do the
clip plane transformation.

Reviewed-by: Nicolai Hähnle <email address hidden>
Tested-by: Michel Dänzer <email address hidden>
Reviewed-by: Roland Scheidegger <email address hidden>

69236. By Leo Liu <email address hidden> 12 hours ago

radeon/vcn: enable h264 decode entension support

It's enabled through message buffer for UVD

Signed-off-by: Leo Liu <email address hidden>
Acked-by: Christian König <email address hidden>

69235. By Charmaine Lee <email address hidden> 13 hours ago

svga: clean up format_cap_table

Per Jose's suggestion, this patch cleans up format_cap_table to remove
the unnecessary default cap value for vgpu10 formats since those devcap values
can be retrieved from the device.

Tested with MTT conform, glretrace, piglit in HWv13 and HWv8.

Reviewed-by: Brian Paul <email address hidden>
Reviewed-by: Jose Fonseca <email address hidden>

69234. By Charmaine Lee <email address hidden> 13 hours ago

svga: fix the default devcap for SVGA3D_Z_D24S8_INT

The default devcap for format SVGA3D_Z_D24S8_INT in HWv8 when its devcap is
not explicitly advertised should be set to zero to match the default value
in the device.

Tested with MTT piglit in HW version 8.

Reviewed-by: Neha Bhende <email address hidden>

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