lp:mesa

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74624. By Marek Olšák <email address hidden> 16 hours ago

ac: add ac_build_fmin/fmax helpers

Reviewed-by: Samuel Pitoiset <email address hidden>

74623. By Marek Olšák <email address hidden> 16 hours ago

mesa: remove dd_function_table::GetCompressedTexSubImage and clean it up

Reviewed-by: Ian Romanick <email address hidden>

74622. By Neil Roberts <email address hidden> 17 hours ago

mesa: Tidy up the 4.6 section of GL4x.xml

The enums are moved to the top and indented like the rest of the file.
Comments are added to split up the function aliases by corresponding
extension. This should make no functional difference.

Reviewed-by: Ian Romanick <email address hidden>

74621. By Samuel Pitoiset on 2018-01-05

radv: remove unused radv_color_buffer_info::cb_clear_valueX

Found by inspection.

Signed-off-by: Samuel Pitoiset <email address hidden>
Reviewed-by: Bas nieuwenhuizen <email address hidden>

74620. By Alex Smith on 2018-01-05

anv: Take write mask into account in has_color_buffer_write_enabled

If we have a color attachment, but its writes are masked, this would
have still returned true. This is inconsistent with how HasWriteableRT
in 3DSTATE_PS_BLEND is set, which does take the mask into account.

This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA
if the fragment shader does use UAVs, meaning the fragment shader may
not be invoked because HasWriteableRT is false. Specifically, this was
seen to occur when the shader also enables early fragment tests: the
fragment shader was not invoked despite passing depth/stencil.

Fix by taking the color write mask into account in this function. This
is consistent with how things are done on i965.

Signed-off-by: Alex Smith <email address hidden>
Cc: <email address hidden>
Reviewed-by: Iago Toral Quiroga <email address hidden>
Reviewed-by: Lionel Landwerlin <email address hidden>

74619. By Neil Roberts <email address hidden> on 2018-01-05

mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parameters

Reviewed-by: Ian Romanick <email address hidden>

74618. By Samuel Pitoiset on 2018-01-05

radv: enable denorms for 64-bit and 16-bit floats

Similar to RadeonSI.

This fixes:
dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat

Signed-off-by: Samuel Pitoiset <email address hidden>
Reviewed-by: Bas Nieuwenhuizen <email address hidden>

74617. By Samuel Pitoiset on 2018-01-05

amd/common: correctly detect if we need ring buffers

When allocate_user_sgprs() was called, ctx->stage was actually
unset and 0 is for the vertex shader. This doesn't change
anything for now because of the spill support thing.

Though, the number of user SGPRs has to be fixed for merged
shaders on GFX9. It was broken before anyway.

Signed-off-by: Samuel Pitoiset <email address hidden>
Reviewed-by: Bas Nieuwenhuizen <email address hidden>

74616. By Samuel Pitoiset on 2018-01-05

amd/common: use ac_image_load when lod is zero

This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.

Signed-off-by: Samuel Pitoiset <email address hidden>
Reviewed-by: Marek Olšák <email address hidden>

74615. By Samuel Pitoiset on 2018-01-05

radv: limit the scissor bug workaround to Vega 10 and Raven

Signed-off-by: Samuel Pitoiset <email address hidden>
Reviewed-by: Bas Nieuwenhuizen <email address hidden>