lp:~vcs-imports/gcc/+git/gcc

Author: Jakub Jelinek
Author Date: 2020-01-15 11:35:22 UTC

Handle output of older git in gcc-descr and gcc-undescr aliases.

Author: jsm28
Author Date: 2020-01-11 00:16:54 UTC

Add README.MOVED_TO_GIT.

 * README.MOVED_TO_GIT: New file.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@280156 138bc75d-0d04-0410-961f-82ee72b054a4

Author: gccadmin
Author Date: 2020-01-11 00:16:10 UTC

Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@280154 138bc75d-0d04-0410-961f-82ee72b054a4

Author: gccadmin
Author Date: 2020-01-11 00:16:05 UTC

Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-8-branch@280153 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Alexandre Oliva
Author Date: 2020-01-10 09:20:28 UTC

revamp dump and aux output names

Author: rguenth
Author Date: 2020-01-10 08:18:09 UTC

2020-01-10 Richard Biener <rguenther@suse.de>

 PR testsuite/93216
 * gcc.dg/optimize-bswaphi-1.c: Split previously added
 case into a LE and BE variant.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@280097 138bc75d-0d04-0410-961f-82ee72b054a4

Author: David Malcolm
Author Date: 2020-01-09 15:12:59 UTC

analyzer: fix ICE on METHOD_TYPE (PR 93212)

PR analyzer/93212 reports an ICE when attempting to use -fanalyzer
on a C++ source file. That isn't supported yet, but the fix is
trivial (handling METHOD_TYPE as well as FUNCTION_TYPE).

gcc/analyzer/ChangeLog:
 PR analyzer/93212
 * region-model.cc (make_region_for_type): Use
 FUNC_OR_METHOD_TYPE_P rather than comparing against FUNCTION_TYPE.
 * region-model.h (function_region::function_region): Likewise.

Author: David Malcolm
Author Date: 2019-12-11 02:18:23 UTC

hash-table.h: support non-zero empty values in empty_slow

gcc/ChangeLog:
 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
 (selftest::hash_map_tests_c_tests): Call it.
 * hash-table.h
 (hash_table<Descriptor, Lazy, Allocator>::empty_slow): When not
 resizing the entries buffer, replace the memset to zero with a
 loop that calls mark_empty on all elements.

Author: Richard Sandiford
Author Date: 2019-12-28 11:11:53 UTC

Unshare DR_STEP before gimplifying it

In this testcase we use an unmasked SVE loop with an Advanced SIMD
epilogue (because we don't yet support fully-masked downward loops).
The main loop uses a gather load for the strided access while the
epilogue loop builds the access from scalars instead. In both cases
we gimplify expressions based on the DR_STEP and insert them in the
loop preheader.

The problem was that the gather load code didn't copy the DR_STEP before
gimplifying it, meaning that the epilogue loop tried to reuse a result
from the (non-dominating) main loop preheader.

It looks at first glance like there could be other instances of this too,
but this patch just deals with the gather/scatter case.

2019-12-28 Richard Sandiford <richard.sandiford@arm.com>

gcc/
 * tree-vect-stmts.c (vect_get_strided_load_store_ops): Copy
 DR_STEP before gimplifying it.

gcc/testsuite/
 * gcc.dg/vect/vect-strided-epilogue-1.c: New test.

Author: ian
Author Date: 2019-12-19 06:03:51 UTC

Merge from trunk revision 279561.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gccgo@279562 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Jan Hubicka
Author Date: 2019-12-17 19:48:03 UTC

Merge remote-tracking branch 'origin/master' into honza-gcc-benchmark-branch

Author: David Malcolm
Author Date: 2019-12-11 02:18:23 UTC

hash-table.h: support non-zero empty values in empty_slow

gcc/ChangeLog:
 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
 (selftest::hash_map_tests_c_tests): Call it.
 * hash-table.h
 (hash_table<Descriptor, Lazy, Allocator>::empty_slow): When not
 resizing the entries buffer, replace the memset to zero with a
 loop that calls mark_empty on all elements.

Author: David Malcolm
Author Date: 2019-12-06 17:15:27 UTC

Autogenerated changes

gcc/ChangeLog:
 * config.in: Autogenerated changes.
 * configure: Autogenerated changes.

Author: Kwok Cheung Yeung
Author Date: 2019-11-22 17:02:19 UTC

[og9] Fix libgomp.oacc-fortran/lib-16.f90 test

2019-11-22 Kwok Cheung Yeung <kcy@codesourcery.com>

 libgomp/
 * testsuite/libgomp.oacc-fortran/lib-16.f90: Fix async-safety issue.

Author: David Malcolm
Author Date: 2019-11-20 17:02:41 UTC

[analyzer] Updates to internal documentation

gcc/ChangeLog:
 * doc/analyzer.texi (Analyzer Paths): Add path pruning and
 precision-of-wording vfuncs.
 (Debugging the Analyzer): Consolidate duplicated material.

Author: Maxim Kuvyrkov
Author Date: 2019-11-19 16:10:49 UTC

Merge branches/gcc-7-branch rev 278197.

Change-Id: Ibb71a61e711bfb73fb19339d3f402c53d9dfa681

Author: Iain Sandoe
Author Date: 2019-11-16 21:46:31 UTC

Testsuite.

There are two categories of test:

1. Checks for correctly formed source code and the error reporting.
2. Checks for transformation and code-gen.

The second set are run as 'torture' tests for the standard options
set, including LTO. These are also intentionally run with no options
provided (from the coroutines.exp script).

gcc/testsuite/ChangeLog:

2019-11-17 Iain Sandoe <iain@sandoe.co.uk>

 * g++.dg/coroutines/co-yield-syntax-1.C: New test.
 * g++.dg/coroutines/co-yield-syntax-2.C: New test.
 * g++.dg/coroutines/co-yield-syntax-3.C: New test.
 * g++.dg/coroutines/coro-auto-fn.C: New test.
 * g++.dg/coroutines/coro-await-context-auto-fn.C: New test.
 * g++.dg/coroutines/coro-bad-return.C: New test.
 * g++.dg/coroutines/coro-builtins.C: New test.
 * g++.dg/coroutines/coro-constexpr-fn.C: New test.
 * g++.dg/coroutines/coro-context-ctor-dtor.C: New test.
 * g++.dg/coroutines/coro-context-main.C: New test.
 * g++.dg/coroutines/coro-context-vararg.C: New test.
 * g++.dg/coroutines/coro-missing-gro.C: New test.
 * g++.dg/coroutines/coro-missing-promise-yield.C: New test.
 * g++.dg/coroutines/coro-missing-ret-value.C: New test.
 * g++.dg/coroutines/coro-missing-ret-void.C: New test.
 * g++.dg/coroutines/coro-missing-ueh-1.C: New test.
 * g++.dg/coroutines/coro-missing-ueh-2.C: New test.
 * g++.dg/coroutines/coro-missing-ueh-3.C: New test.
 * g++.dg/coroutines/coro-missing-ueh.h: New test.
 * g++.dg/coroutines/coro-pre-proc.C: New test.
 * g++.dg/coroutines/coro.h: New test.
 * g++.dg/coroutines/coroutines.exp: New file.
 * g++.dg/coroutines/torture/co-await-0-triv.C: New test.
 * g++.dg/coroutines/torture/co-await-1-value.C: New test.
 * g++.dg/coroutines/torture/co-await-2-xform.C: New test.
 * g++.dg/coroutines/torture/co-await-3-rhs-op.C: New test.
 * g++.dg/coroutines/torture/co-await-4-control-flow.C: New test.
 * g++.dg/coroutines/torture/co-await-5-loop.C: New test.
 * g++.dg/coroutines/torture/co-await-6-ovl.C: New test.
 * g++.dg/coroutines/torture/co-await-7-tmpl.C: New test.
 * g++.dg/coroutines/torture/co-await-8-cascade.C: New test.
 * g++.dg/coroutines/torture/co-await-9-pair.C: New test.
 * g++.dg/coroutines/torture/co-ret-3.C: New test.
 * g++.dg/coroutines/torture/co-ret-4.C: New test.
 * g++.dg/coroutines/torture/co-ret-5.C: New test.
 * g++.dg/coroutines/torture/co-ret-6.C: New test.
 * g++.dg/coroutines/torture/co-ret-7.C: New test.
 * g++.dg/coroutines/torture/co-ret-8.C: New test.
 * g++.dg/coroutines/torture/co-ret-9.C: New test.
 * g++.dg/coroutines/torture/co-ret-void-is-ready.C: New test.
 * g++.dg/coroutines/torture/co-ret-void-is-suspend.C: New test.
 * g++.dg/coroutines/torture/co-yield-0-triv.C: New test.
 * g++.dg/coroutines/torture/co-yield-1-multi.C: New test.
 * g++.dg/coroutines/torture/co-yield-2-loop.C: New test.
 * g++.dg/coroutines/torture/co-yield-3-tmpl.C: New test.
 * g++.dg/coroutines/torture/co-yield-strings.C: New test.
 * g++.dg/coroutines/torture/coro-torture.exp: New file.
 * g++.dg/coroutines/torture/exceptions-test-0.C: New test.
 * g++.dg/coroutines/torture/func-params-0.C: New test.
 * g++.dg/coroutines/torture/func-params-1.C: New test.
 * g++.dg/coroutines/torture/func-params-2.C: New test.
 * g++.dg/coroutines/torture/func-params-3.C: New test.
 * g++.dg/coroutines/torture/func-params-4.C: New test.
 * g++.dg/coroutines/torture/func-params-5.C: New test.
 * g++.dg/coroutines/torture/gro_on_alloc_fail_0.C: New test.
 * g++.dg/coroutines/torture/local-var-0.C: New test.
 * g++.dg/coroutines/torture/local-var-1.C: New test.
 * g++.dg/coroutines/torture/local-var-2.C: New test.
 * g++.dg/coroutines/torture/local-var-3.C: New test.
 * g++.dg/coroutines/torture/local-var-4.C: New test.
 * g++.dg/coroutines/torture/mid-suspend-destruction-0.C: New test.

Author: David Malcolm
Author Date: 2019-10-03 18:45:58 UTC

Autogenerated changes (configure/config.in)

Author: rguenth
Author Date: 2019-11-14 07:40:39 UTC

Update ChangeLog and version files for release

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@278197 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Iain Buclaw
Author Date: 2019-10-24 05:18:29 UTC

Merge dmd b70b154d7, druntime 9920757c, phobos 719214c7e, and testsuite

Author: Jason Merrill
Author Date: 2019-10-04 18:13:40 UTC

 * pt.c (for_each_template_parm_r): Handle SCOPE_REF.

Author: Martin Jambor
Author Date: 2019-09-18 13:20:05 UTC

Added two missing overlap checks

Author: Boris Kolpackov
Author Date: 2019-09-07 12:06:28 UTC

Add few TODO items

Author: Jonathan Wakely
Author Date: 2019-09-12 22:59:08 UTC

Adjust std::assignable_from for P1452R2 support

Author: Martin Liska
Author Date: 2019-09-09 12:33:21 UTC

Enable -fversion-loops-for-strides with -O2.

Author: Steve Ellcey
Author Date: 2019-06-07 21:09:23 UTC

Update with Andrew Pinski's struct reorg patch.

Author: Boris Kolpackov
Author Date: 2019-04-23 07:39:17 UTC

Add support for header include re-search

Author: Chung-Lin Tang
Author Date: 2019-04-01 15:21:42 UTC

[og] Handle Compute Capability 7.0 (Volta)

     libgomp/
     * plugin/plugin-nvptx.c (GOMP_OFFLOAD_load_image): Handle up to
     Compute Capability 7.0.

Author: Iain Sandoe
Author Date: 2019-04-01 09:16:52 UTC

[libstdc++, darwin, testsuite] Use -U__STRICT_ANSI__ on earlier darwin.

This is needed to expose the ll* functions.

Author: Michael Matz
Author Date: 2019-02-25 02:26:17 UTC

Fix miscompiles

there's a separate PBB for the out-of-ssa "copies" from BB to successor.
We always must add reads of incoming args even if the definition was
within the BB as it's bound to be in a different PBB.
Also generate those out-of-ssa copies only for the black box for
which they were analyzed, not for all of them.

Author: Richard Guenther
Author Date: 2019-01-30 15:12:31 UTC

fix-data-ref-enhancement-for-SLP-size-one

Author: Liu, Hongtao
Author Date: 2019-01-18 02:01:07 UTC

i386: Add mask2 to builtin_description

There are

struct builtin_description
{
  const HOST_WIDE_INT mask;
  const enum insn_code icode;
  const char *const name;
  const enum ix86_builtins code;
  const enum rtx_code comparison;
  const int flag;
};

Since "mask" is used for both ix86_isa_flags and ix86_isa_flags2, buitins
with both flags can't be handled easily. This patch adds mask2 to
builtin_description to handle it properly.

2019-01-23 Hongtao Liu <hongtao.liu@intel.com>
     H.J. Lu <hongjiu.lu@intel.com>

 PR target/88909
 * config/i386/i386-builtin.def: Add mask2 to all builtin
 initializations. Merge ARGS2 and SPECIAL_ARGS2 into ARGS and
 SPECIAL_ARGS.
 * config/i386/i386.c (BDESC): Add mask2 to the definition.
 (BDESC_FIRST): Likewise.
 (define_builtin): Add an argument for mask2. Updated to handle
 both ix86_isa_flags and ix86_isa_flags2.
 (define_builtin_const): Likewise.
 (define_builtin_pure): Likewise.
 (define_builtin2): Deleted.
 (define_builtin_const2): Likewise.
 (builtin_description): Add a member, mask2.
 (bdesc_*): Add mask2 to builtin initializations.
 (ix86_init_mmx_sse_builtins): Update calls to def_builtin,
 def_builtin_const and def_builtin_pure. Remove SPECIAL_ARGS2
 support.
 (ix86_get_builtin_func_type): Remove SPECIAL_ARGS2 support.

Author: TCWG Automation
Author Date: 2018-11-15 16:33:25 UTC

 gcc/
 * LINARO-VERSION: Bump version number, post snapshot.

Author: jcmvbkbc
Author Date: 2018-11-07 20:52:55 UTC

gcc: xtensa: don't force PIC for uclinux target

xtensa-uclinux uses bFLT executable file format that cannot relocate
fields representing offsets from data to code. C++ objects built as PIC
use offsets to encode FDE structures. As a result C++ exception handling
doesn't work correctly on xtensa-uclinux. Don't use PIC by default on
xtensa-uclinux.

gcc/
2018-11-07 Max Filippov <jcmvbkbc@gmail.com>

 Backport from mainline
 2018-11-05 Max Filippov <jcmvbkbc@gmail.com>

 * config/xtensa/uclinux.h (XTENSA_ALWAYS_PIC): Change to 0.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@265890 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Bernhard
Author Date: 2018-10-21 13:55:40 UTC

Fix memory leak of gsymbol

We did not free global symbols. For a simplified abstract_type_3.f90
valgrind reports:

96 bytes in 1 blocks are still reachable in loss record 461 of 602
   at 0x48377D5: calloc (vg_replace_malloc.c:711)
   by 0x21257C3: xcalloc (xmalloc.c:162)
   by 0x98611B: gfc_get_gsymbol(char const*) (symbol.c:4341)
   by 0x932C58: parse_module() (parse.c:5912)
   by 0x9336F8: gfc_parse_file() (parse.c:6236)
   by 0x991449: gfc_be_parse_file() (f95-lang.c:204)
   by 0x11D8EDE: compile_file() (toplev.c:455)
   by 0x11DB9C3: do_compile() (toplev.c:2170)
   by 0x11DBCAF: toplev::main(int, char**) (toplev.c:2305)
   by 0x2045D37: main (main.c:39)

This patch reduces this to

 LEAK SUMMARY:
    definitely lost: 344 bytes in 1 blocks
    indirectly lost: 3,024 bytes in 4 blocks
      possibly lost: 0 bytes in 0 blocks
- still reachable: 1,576,174 bytes in 2,277 blocks
+ still reachable: 1,576,078 bytes in 2,276 blocks
         suppressed: 0 bytes in 0 blocks

gcc/fortran/ChangeLog:

2018-10-21 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>

 * parse.c (clean_up_modules): Free gsym.

Author: dragan.mladjenovic
Author Date: 2018-05-23 12:59:57 UTC

Skip LRA compress_live_ranges if no vregs are alive

Fixes [GTM18-75] nanoMIPS 2018.04-02 ICE with -mlra-equiv and -fdump-rtl-reload

gcc/

   * lra-lives.c (lra_create_live_ranges_1): Assert that lra_live_max_point being 0
   is caused by removal of all vregs by process_bb_lives and skip compress_live_ranges.

gcc/testsuite/

   * gcc.target/nanomips/nanomips.exp: Add -mlra-equiv to allowed dg-options.
   * gcc.target/nanomips/lra-equiv-1.c: New file.

Author: Thomas Schwinge
Author Date: 2018-05-20 19:31:01 UTC

[PR81886] Avoid "GOMP_set_offload_targets: Assertion `!gomp_offload_targets_init' failed"

 PR libgomp/81886
 * openacc.h (enum acc_device_t): Add _acc_device_intel_mic,
 _acc_device_hsa.
 * oacc-init.c (get_openacc_name): Handle these.
 (resolve_device): Debugging output.
 * target.c (resolve_device, gomp_init_device)
 (gomp_offload_target_available_p): Likewise.
 (GOMP_set_offload_targets): Rewrite.
 * testsuite/libgomp.oacc-c++/c++.exp: Provide offload target in
 "-DACC_DEVICE_TYPE_host", and "-DACC_DEVICE_TYPE_nvidia".
 * testsuite/libgomp.oacc-c/c.exp: Likewise.
 * testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.
 * testsuite/libgomp.oacc-c/offload-targets-1.c: New file.
 * testsuite/libgomp.oacc-c/offload-targets-2.c: Likewise.
 * testsuite/libgomp.oacc-c/offload-targets-3.c: Likewise.
 * testsuite/libgomp.oacc-c/offload-targets-4.c: Likewise.
 * testsuite/libgomp.oacc-c/offload-targets-5.c: Likewise.
 * testsuite/libgomp.oacc-c/offload-targets-6.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/acc-on-device-2.c: Adjust.
 * testsuite/libgomp.oacc-c-c++-common/acc_on_device-1.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85381-2.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85381-3.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85381-4.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85381-5.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85381.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85486-2.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85486-3.c: Likewise.
 * testsuite/libgomp.oacc-c-c++-common/pr85486.c: Likewise.
 * testsuite/libgomp.oacc-fortran/acc_on_device-1-1.f90: Likewise.
 * testsuite/libgomp.oacc-fortran/acc_on_device-1-2.f: Likewise.
 * testsuite/libgomp.oacc-fortran/acc_on_device-1-3.f: Likewise.

Author: Richard Sandiford
Author Date: 2018-05-10 14:08:35 UTC

Merge trunk into sve

Also remove support for first-faulting loads and capped
vectorisation factors; these need more work.

Author: Richard Sandiford
Author Date: 2017-05-28 08:49:41 UTC

Use conditional internal functions in if-conversion

This allows us to vectorise things like:

    x[i] = a[i] < 0 ? x[i] + y : x[i];

even if the addition might trap.

The patch also adds new conditional functions for multiplication
and division, which previously weren't needed.

Author: roland
Author Date: 2018-05-05 23:35:25 UTC

PR other/77609: Let the assembler choose ELF section types for miscellaneous named sections

gcc/
 PR other/77609
 * varasm.c (default_section_type_flags): Set SECTION_NOTYPE for
 any section for which we don't know a specific type it should have,
 regardless of name. Previously this was done only for the exact
 names ".init_array", ".fini_array", and ".preinit_array".
 (default_elf_asm_named_section): Add comment about
 relationship with default_section_type_flags and SECTION_NOTYPE.
 (get_section): Don't consider it a type conflict if one side has
 SECTION_NOTYPE and the other doesn't, as long as neither has the
 SECTION_BSS et al used in the default_section_type_flags logic.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@259969 138bc75d-0d04-0410-961f-82ee72b054a4
(cherry picked from commit db7548a2771bbf34cf7430712af7ac670b429958)

Author: Roland McGrath
Author Date: 2018-02-28 00:25:03 UTC

PR other/77609: Let the assembler choose ELF section types for miscellaneous named sections

gcc/
 PR other/77609
 * varasm.c (default_section_type_flags): Set SECTION_NOTYPE for
 any section for which we don't know a specific type it should have,
 regardless of name. Previously this was done only for the exact
 names ".init_array", ".fini_array", and ".preinit_array".
 (default_elf_asm_named_section): Add comment about
 relationship with default_section_type_flags and SECTION_NOTYPE.
 (get_section): Don't consider it a type conflict if one side has
 SECTION_NOTYPE and the other doesn't, as long as neither has the
 SECTION_BSS et al used in the default_section_type_flags logic.

(cherry picked from commit 7e635af31c4c5caf25fc103bcc96f0e4970fb2da)

Author: Maxim Kuvyrkov
Author Date: 2018-04-27 08:54:57 UTC

Follow up fix for --with-system-zlib=no handling.

Change-Id: I4e8b179e2a2c68ffb9e6d3a2e35fee71618f9f5b

Author: Aldy Hernandez
Author Date: 2018-04-13 07:16:03 UTC

Fallout from merge.

Fix size_must_be_zero_p to fix builtin-stringop-chk-4.c regression.

Author: Alexandre Oliva
Author Date: 2018-03-16 21:41:17 UTC

Merge trunk, as of Mar 10, into lxoliva/SFN

Author: uros
Author Date: 2017-03-25 18:10:37 UTC

 PR target/80180
 * config/i386/i386.c (ix86_expand_builtin)
 <IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Do not expand arg0 between
 flags reg setting and flags reg using instructions.
 <IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Ditto. Use non-flags reg
 clobbering instructions to zero extend op2.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@246477 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Roland McGrath
Author Date: 2018-02-26 23:46:39 UTC

PR other/77609: Let the assembler choose ELF section types for miscellaneous named sections

gcc/
 PR other/77609
 * varasm.c (default_section_type_flags): Set SECTION_NOTYPE for
 any section for which we don't know a specific type it should have,
 regardless of name. Previously this was done only for the exact
 names ".init_array", ".fini_array", and ".preinit_array".

(cherry picked from commit b9a216a984df9f9fc676261886b5f394547d0a3d)

Author: Jonathan Wakely
Author Date: 2018-02-23 22:40:14 UTC

Merge branch 'master' into redi/parallelism

Author: H.J. Lu
Author Date: 2017-07-06 15:58:46 UTC

i386: Align stack frame if argument is passed on stack

When a function call is removed, it may become a leaf function. But if
argument may be passed on stack, we need to align the stack frame when
there is no tail call.

Tested on Linux/i686 and Linux/x86-64.

gcc/

 Backport from mainline
 PR target/83330
 * config/i386/i386.c (ix86_function_arg_advance): Set
 outgoing_args_on_stack to true if there are outgoing arguments
 on stack.
 (ix86_function_arg): Likewise.
 (ix86_compute_frame_layout): Align stack frame if argument is
 passed on stack.
 * config/i386/i386.h (machine_function): Add
 outgoing_args_on_stack.

gcc/testsuite/

 Backport from mainline
 PR target/83330
 * gcc.target/i386/pr83330.c: New test.

Author: H.J. Lu
Author Date: 2017-10-24 12:24:58 UTC

i386: Avoid PLT when shadow stack is enabled

PLT should be avoided with shadow stack in 32-bit mode if more than 2
parameters are passed in registers since only 2 parameters can be passed
in registers for external function calls via PLT with shadow stack
enabled.

gcc/

 PR target/81780
 * config/i386/i386.c (ix86_noplt_attribute_p): New function.
 (ix86_expand_call): Use it.
 (ix86_nopic_noplt_attribute_p): Likewise.

gcc/testsuite/

 PR target/81780
 * gcc.target/i386/pr81780-1.c: New test.
 * gcc.target/i386/pr81780-2.c: Likewise.
 * gcc.target/i386/pr81780-3.c: Likewise.
 * gcc.target/i386/pr81780-4.c: Likewise.

Author: hjl
Author Date: 2017-11-15 19:30:58 UTC

i386: Add X86_TUNE_EMIT_VZEROUPPER

Add X86_TUNE_EMIT_VZEROUPPER to indicate if vzeroupper instruction should
be inserted before a transfer of control flow out of the function. It is
turned on by default unless we are tuning for KNL. Users can always use
-mzeroupper or -mno-zeroupper to override X86_TUNE_EMIT_VZEROUPPER.

gcc/

 PR target/82990
 * config/i386/i386.c (pass_insert_vzeroupper::gate): Remove
 TARGET_AVX512ER check.
 (ix86_option_override_internal): Set MASK_VZEROUPPER if
 neither -mzeroupper nor -mno-zeroupper is used and
 TARGET_EMIT_VZEROUPPER is set.
 * config/i386/i386.h (TARGET_EMIT_VZEROUPPER): New.
 * config/i386/x86-tune.def: Add X86_TUNE_EMIT_VZEROUPPER.

gcc/testsuite/

 PR target/82990
 * gcc.target/i386/pr82942-2.c: Add -mtune=knl.
 * gcc.target/i386/pr82990-1.c: New test.
 * gcc.target/i386/pr82990-2.c: Likewise.
 * gcc.target/i386/pr82990-3.c: Likewise.
 * gcc.target/i386/pr82990-4.c: Likewise.
 * gcc.target/i386/pr82990-5.c: Likewise.
 * gcc.target/i386/pr82990-6.c: Likewise.
 * gcc.target/i386/pr82990-7.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254783 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Alexandre Oliva
Author Date: 2017-10-20 14:05:19 UTC

debug info: partial noentry functions: omp split-out blocks

Author: David Malcolm
Author Date: 2017-10-11 18:40:46 UTC

Introduce a blt_context class

Author: gccadmin
Author Date: 2017-10-10 08:11:01 UTC

Update ChangeLog and version files for release

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@253576 138bc75d-0d04-0410-961f-82ee72b054a4

Author: hjl
Author Date: 2017-10-05 10:45:04 UTC

Add sanitizer_linux_x86_64.lo if __x86_64__ is defined by $CC

Since size of "void *" is 4 bytes for x32, check if __x86_64__ is defined
by $CC, instead of

if test x$ac_cv_sizeof_void_p = x8; then

to decide wether sanitizer_linux_x86_64.lo should be used.

 Backported from mainline
 PR sanitizer/82379
 * configure.tgt (SANITIZER_COMMON_TARGET_DEPENDENT_OBJECTS): Set
 to sanitizer_linux_x86_64.lo if __x86_64__ is defined by $CC.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@253442 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2017-10-02 10:35:55 UTC

Fix x32 Ada

Author: H.J. Lu
Author Date: 2017-10-01 00:51:15 UTC

Add anitizer_linux_x86_64.lo if __x86_64__ is defined by $CC

Since size of "void *" is 4 bytes for x32, check if __x86_64__ is defined
by $CC, instead of

if test x$ac_cv_sizeof_void_p = x8; then

to decide wether anitizer_linux_x86_64.lo should be used.

 PR sanitizer/82379
 * configure.tgt (ANITIZER_COMMON_TARGET_DEPENDENT_OBJECTS): Set
 to anitizer_linux_x86_64.lo if __x86_64__ is defined by $CC.

Author: H.J. Lu
Author Date: 2017-09-23 20:26:50 UTC

x32: Encode %esp as %rsp to avoid 0x67 prefix

Since the upper 32 bits of stack register are always zero for x32, we
can encode %esp as %rsp to avoid 0x67 prefix in address if there is no
index or base register.

Back port from mainline r253127.

gcc/

2017-09-24 Uros Bizjak <ubizjak@gmail.com>

 PR target/82267
 * config/i386/i386.c (ix86_print_operand_address_as): Encode
 %esp as %rsp to avoid 0x67 prefix if there is no index or base
 register.

gcc/testsuite/

2017-09-24 H.J. Lu <hongjiu.lu@intel.com>

 PR target/82267
 * gcc.target/i386/pr82267.c: New tests.

Author: hjl
Author Date: 2017-09-17 21:11:04 UTC

i386: Update preferred stack boundary for leaf functions

preferred_stack_boundary may not be the minimum stack alignment. For
leaf functions without TLS access, max_used_stack_slot_alignment may be
smaller. We should update preferred_stack_boundary for leaf functions.

gcc/

 PR target/82166
 * config/i386/i386.c (ix86_finalize_stack_frame_flags): Properly
 compute the minimum stack alignment. Also update preferred stack
 boundary for leaf functions.

gcc/testsuite/

 PR target/82166
 * gcc.target/i386/pr82166.c: New test.

(cherry picked from commit a842b1bde9fa682693226e126fe8128d71ca944d)

Author: H.J. Lu
Author Date: 2017-09-15 23:31:52 UTC

Set need_drap to true for sp_is_unchanging

Author: H.J. Lu
Author Date: 2017-08-21 12:13:00 UTC

Update expected alignment in pr53037-1.C/pr53037-1.c

Since alignment of int is 2 bytes for m68k, expect either 2 or 4
alignments in warning.

 * g++.dg/pr53037-1.C: Expect either 2 or 4 alignments in
 warning.
 * gcc.dg/pr53037-1.c: Likewise.

Author: uros
Author Date: 2017-07-09 21:01:42 UTC

Update gcc.dg/stack-layout-dynamic-1.c

 PR target/81313
 * gcc.dg/stack-layout-dynamic-1.c (bar): Add 4 additional
 integer argumets to bypass x86_64 outgoing args optimization.

(cherry picked from commit ac2f5a408fa8768a0936b256f5cd7e0fe9f3b963)

Author: Richard Sandiford
Author Date: 2017-08-31 07:37:31 UTC

Add missing file

Author: H.J. Lu
Author Date: 2016-07-28 17:00:43 UTC

Add __attribute__((visibility("protected"))) tests

Author: uros
Author Date: 2017-07-09 21:01:42 UTC

Update gcc.dg/stack-layout-dynamic-1.c

 PR target/81313
 * gcc.dg/stack-layout-dynamic-1.c (bar): Add 4 additional
 integer argumets to bypass x86_64 outgoing args optimization.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250086 138bc75d-0d04-0410-961f-82ee72b054a4

(cherry picked from commit ac2f5a408fa8768a0936b256f5cd7e0fe9f3b963)

Author: jamborm
Author Date: 2017-08-14 14:33:54 UTC

Merged trunk revision 251080 into the hsa branch

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/hsa@251093 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2017-08-09 16:21:56 UTC

i386: Require MMX for builtins with MMX register

When MMX is disabled, MMX registers aren't available. We shouldn't
allow builtins with MMX registers when MMX registers aren't available.
This applies to MMX and 3DNow builtins as well as SSE builtins with
MMX registers.

Also we should always declare all builtins and ix86_expand_builtin
will give an error if the builtin isn't available.

gcc.target/i386/crc32-4.c is updated to scan __builtin_ia32_crc32di only
for ia32 since __builtin_ia32_crc32di is a normal function for ia32 and
a builtin function for x86-64.

Tested on i686 and x86-64.

gcc/

 PR target/79565
 * config/i386/i386-builtin.def: Add OPTION_MASK_ISA_MMX to all
 builtins with MMX register.
 * config/i386/i386.c (def_builtin): Always declare all builtins.
 (ix86_expand_builtin): Check if MMX is enabled for builtins with
 MMX register.
 * config/i386/sse.md: Require TARGET_MMX for all patterns with
 MMX register.

gcc/testsuite/

 PR target/79565
 * gcc.target/i386/crc32-4.c: Scan __builtin_ia32_crc32di only
 for ia32 target.
 (crc32d): Check for "needs isa option" error for non-ia32
 targets.
 * gcc.target/i386/pr70325.c (f): Check for "needs isa option"
 error instead.
 * gcc.target/i386/pr79565.c: New test.

Author: H.J. Lu
Author Date: 2017-08-06 13:24:36 UTC

i386: Don't use frame pointer without stack access

When there is no stack access, there is no need to use frame pointer
even if -fno-omit-frame-pointer is used and caller's frame pointer is
unchanged.

gcc/

 PR target/81736
 * config/i386/i386.c (ix86_finalize_stack_realign_flags): Renamed
 to ...
 (ix86_finalize_stack_frame_flags): This. Also clear
 frame_pointer_needed if -fno-omit-frame-pointer is used without
 stack access.
 (ix86_expand_prologue): Replace ix86_finalize_stack_realign_flags
 with ix86_finalize_stack_frame_flags.
 (ix86_expand_epilogue): Likewise.
 (ix86_expand_split_stack_prologue): Likewise.
 * doc/invoke.texi: Add a note for -fno-omit-frame-pointer.

gcc/testsuite/

 PR target/81736
 * gcc.target/i386/pr81736-1.c: New test.
 * gcc.target/i386/pr81736-2.c: Likewise.
 * gcc.target/i386/pr81736-3.c: Likewise.
 * gcc.target/i386/pr81736-4.c: Likewise.
 * gcc.target/i386/pr81736-5.c: Likewise.
 * gcc.target/i386/pr81736-6.c: Likewise.
 * gcc.target/i386/pr81736-7.c: Likewise.

Author: H.J. Lu
Author Date: 2017-07-07 13:01:16 UTC

i386: Avoid stack realignment if possible

Since DRAP isn't used with -maccumulate-outgoing-args, pr59501-4a.c was
xfailed due to stack frame access via frame pointer instead of DARP.
This patch finds the maximum stack alignment from the stack frame access
instructions and avoids stack realignment if stack alignment needed is
less than or equal to incoming stack boundary.

gcc/

 PR target/59501
 * config/i386/i386.c (ix86_finalize_stack_realign_flags): Don't
 realign stack if stack alignment needed is less than incoming
 stack boundary.

gcc/testsuite/

 PR target/59501
 * gcc.target/i386/pr59501-4a.c: Remove xfail.

Author: Martin Jambor
Author Date: 2017-07-31 12:43:24 UTC

Merge branch 'master' into gcn

Author: H.J. Lu
Author Date: 2017-07-25 11:43:05 UTC

Properly compute stack frame for exception handler

Author: H.J. Lu
Author Date: 2017-07-26 16:06:22 UTC

x86: Properly check saved register CFA offset

X86 prologue saves register at CFA offset. Since its location on stack
is computed as CFA - its CFA_OFFSET, CFA_OFFSET points the end of the
saved register area on stack. This patch updates sp_valid_at and
fp_valid_at to properly check saved register CFA offset.

gcc/

 PR target/81563
 * config/i386/i386.c (sp_valid_at): Properly check CFA offset.
 (fp_valid_at): Likewise.

gcc/testsuite/

 PR target/81563
 * gcc.target/i386/pr81563.c: New test

Author: David Malcolm
Author Date: 2017-07-20 16:40:33 UTC

FIXME: C: add c_expr::get_location

Author: H.J. Lu
Author Date: 2017-07-07 13:01:16 UTC

i386: Avoid stack realignment if possible

Since DRAP isn't used with -maccumulate-outgoing-args, pr59501-4a.c was
xfailed due to stack frame access via frame pointer instead of DARP.
This patch finds the maximum stack alignment from the stack frame access
instructions and avoids stack realignment if stack alignment needed is
less than incoming stack boundary.

gcc/

 PR target/59501
 * config/i386/i386.c (ix86_finalize_stack_realign_flags): Don't
 realign stack if stack alignment needed is less than incoming
 stack boundary.

gcc/testsuite/

 PR target/59501
 * gcc.target/i386/pr59501-4a.c: Remove xfail.

Author: Alexandre Oliva
Author Date: 2017-06-06 19:44:55 UTC

[libcc1] drop unused field from C++ lang_identifier

for gcc/cp/ChangeLog

 * cp-tree.h (lang_identifier): Drop oracle_looked_up, unused.

Author: yroux
Author Date: 2017-01-18 12:03:08 UTC

Bump version number, post release.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@244574 138bc75d-0d04-0410-961f-82ee72b054a4

Author: Richard Guenther
Author Date: 2016-11-15 14:42:58 UTC

Merge remote-tracking branch 'trunk' of git://gcc.gnu.org/git/gcc into gimplefe

Author: Alexander Monakov
Author Date: 2016-11-09 13:58:17 UTC

Merge remote-tracking branch 'origin/trunk' into gomp-nvptx-branch-merge-trunk

Author: burnus
Author Date: 2016-09-20 21:49:12 UTC

Merge from trunk (r239915 to r240230)

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/fortran-dev@240290 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2016-03-06 14:38:21 UTC

Add a TARGET_GEN_MEMSET_VALUE hook

builtin_memset_gen_str returns a register used for memset, which only
supports integer registers. But a target may use vector registers in
memmset. This patch adds a TARGET_GEN_MEMSET_VALUE hook to duplicate
QImode value to mode derived from STORE_MAX_PIECES, which can be used
with vector instructions. The default hook is the same as the original
builtin_memset_gen_str. A target can override it to support vector
instructions for STORE_MAX_PIECES.

gcc/

 * builtins.c (builtin_memset_gen_str): Call targetm.gen_memset_value.
 (default_gen_memset_value): New function.
 * target.def (gen_memset_value): New hook.
 * targhooks.c: Inclue "expmed.h" and "builtins.h".
 (default_gen_memset_value): New function.
 * targhooks.h (default_gen_memset_value): New prototype.
 * config/i386/i386.c (ix86_gen_memset_value): New function.
 (TARGET_GEN_MEMSET_VALUE): New.
 * config/i386/i386.h (STORE_MAX_PIECES): Likewise.
 * doc/tm.texi.in: Add TARGET_GEN_MEMSET_VALUE hook.
 * doc/tm.texi: Updated.

gcc/testsuite/

 * gcc.target/i386/pieces-memset-1.c: New test.
 * gcc.target/i386/pieces-memset-2.c: Likewise.
 * gcc.target/i386/pieces-memset-3.c: Likewise.
 * gcc.target/i386/pieces-memset-4.c: Likewise.
 * gcc.target/i386/pieces-memset-5.c: Likewise.
 * gcc.target/i386/pieces-memset-6.c: Likewise.
 * gcc.target/i386/pieces-memset-7.c: Likewise.
 * gcc.target/i386/pieces-memset-8.c: Likewise.
 * gcc.target/i386/pieces-memset-9.c: Likewise.
 * gcc.target/i386/pieces-memset-10.c: Likewise.
 * gcc.target/i386/pieces-memset-11.c: Likewise.
 * gcc.target/i386/pieces-memset-12.c: Likewise.
 * gcc.target/i386/pieces-memset-13.c: Likewise.
 * gcc.target/i386/pieces-memset-14.c: Likewise.
 * gcc.target/i386/pieces-memset-15.c: Likewise.
 * gcc.target/i386/pieces-memset-16.c: Likewise.
 * gcc.target/i386/pieces-memset-17.c: Likewise.
 * gcc.target/i386/pieces-memset-18.c: Likewise.
 * gcc.target/i386/pieces-memset-19.c: Likewise.
 * gcc.target/i386/pieces-memset-20.c: Likewise.
 * gcc.target/i386/pieces-memset-21.c: Likewise.
 * gcc.target/i386/pieces-memset-22.c: Likewise.
 * gcc.target/i386/pieces-memset-23.c: Likewise.
 * gcc.target/i386/pieces-memset-24.c: Likewise.
 * gcc.target/i386/pieces-memset-25.c: Likewise.
 * gcc.target/i386/pieces-memset-26.c: Likewise.
 * gcc.target/i386/pieces-memset-27.c: Likewise.
 * gcc.target/i386/pieces-memset-28.c: Likewise.
 * gcc.target/i386/pieces-memset-29.c: Likewise.
 * gcc.target/i386/pieces-memset-30.c: Likewise.
 * gcc.target/i386/pieces-memset-31.c: Likewise.
 * gcc.target/i386/pieces-memset-32.c: Likewise.
 * gcc.target/i386/pieces-memset-33.c: Likewise.
 * gcc.target/i386/pieces-memset-34.c: Likewise.
 * gcc.target/i386/pieces-memset-35.c: Likewise.
 * gcc.target/i386/pieces-memset-36.c: Likewise.
 * gcc.target/i386/pieces-memset-37.c: Likewise.
 * gcc.target/i386/pieces-memset-38.c: Likewise.
 * gcc.target/i386/pieces-memset-39.c: Likewise.
 * gcc.target/i386/pieces-memset-40.c: Likewise.
 * gcc.target/i386/pieces-memset-41.c: Likewise.
 * gcc.target/i386/pieces-memset-42.c: Likewise.
 * gcc.target/i386/pieces-memset-43.c: Likewise.
 * gcc.target/i386/pieces-memset-44.c: Likewise.

Author: H.J. Lu
Author Date: 2016-03-06 14:35:46 UTC

Don't limit piecewise move to MAX_FIXED_MODE_SIZE

alignment_for_piecewise_move is called only with MOVE_MAX_PIECES or
STORE_MAX_PIECES, which are the number of bytes at a time that we
can move or store efficiently. We should call mode_for_size without
limit to MAX_FIXED_MODE_SIZE, which is an integer expression for the
size in bits of the largest integer machine mode that should actually
be used, may be smaller than MOVE_MAX_PIECES or STORE_MAX_PIECES, which
may use vector register.

MAX_BITSIZE_MODE_ANY_INT is only defined for i386 and everyone else uses
the default. The widest mode for integer computation is determined by
MAX_FIXED_MODE_SIZE, not by MAX_BITSIZE_MODE_ANY_INT. OImode and XImode
can be used for load and store, including constant integers. Remove
MAX_BITSIZE_MODE_ANY_INT from i386 to avoid any potential problems for
constant integers > TImode.

 PR middle-end/74113
 * expr.c (alignment_for_piecewise_move): Call mode_for_size
 without limit to MAX_FIXED_MODE_SIZE.
 * config/i386/i386-modes.def (MAX_BITSIZE_MODE_ANY_INT): Removed.

Author: Thomas Schwinge
Author Date: 2016-08-11 14:34:22 UTC

[WIP] [PR fortran/72741] Rework Fortran OpenACC routine clause handling

Author: H.J. Lu
Author Date: 2016-04-01 20:26:57 UTC

Support 128-bit constant store in 64-bit STV

We can load a 128-bit constant from memory and store it.

gcc/

 * config/i386/i386.c (timode_scalar_to_vector_candidate_p): Allow
 store from 128-bit constant.
 (timode_scalar_chain::convert_insn): Handle store from 128-bit
 constant.

gcc/testsuite/

 * gcc.target/i386/pieces-strcpy-1.c: New test.
 * gcc.target/i386/pieces-strcpy-2.c: Likewise.

Author: H.J. Lu
Author Date: 2016-04-01 20:30:46 UTC

Check 128-bit constant store in 64-bit mode

Author: H.J. Lu
Author Date: 2015-07-09 02:46:43 UTC

IA MCU run-time doesn't support TLS

Return 0 in check_effective_target_tls_native and
check_effective_target_tls_emulated for IA MCU target.

Author: rguenth
Author Date: 2016-08-03 05:07:46 UTC

Mark as release

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@239063 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2016-05-27 20:19:18 UTC

Add __attribute__ ((target("general-regs-only")))

One test fails:

FAIL: gcc.target/i386/pr70738-15.c (test for errors, line 10)

due to

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71318

Author: bstarynk
Author Date: 2016-05-15 18:50:51 UTC

[gcc/]
2016-05-15 Basile Starynkevitch <basile@starynkevitch.net>
 {{unstable}}
 * melt/generated/*: Regenerated all.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@236255 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2016-05-07 14:25:57 UTC

Add pr70155-23.c

Author: H.J. Lu
Author Date: 2016-04-01 20:30:46 UTC

Check 128-bit constant store in 64-bit mode

Author: hjl
Author Date: 2016-05-02 21:45:34 UTC

Backport r265322 from llvm upstream

Since x86 psABIs require the function incoming stack must align at 16
bytes, child process stack passed to clone should be aligned at 16
bytes.

 PR testsuite/70520
 * c-c++-common/asan/clone-test-1.c (main): Align child process
 stack to 16 bytes.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235790 138bc75d-0d04-0410-961f-82ee72b054a4

Author: hjl
Author Date: 2016-04-20 13:39:28 UTC

Simplify ix86_expand_vector_move_misalign

Since mov<mode>_internal patterns handle both aligned/unaligned load
and store, we can simplify ix86_avx256_split_vector_move_misalign and
ix86_expand_vector_move_misalign.

 * config/i386/i386.c (ix86_avx256_split_vector_move_misalign):
 Short-cut unaligned load and store cases. Handle all integer
 vector modes.
 (ix86_expand_vector_move_misalign): Short-cut unaligned load
 and store cases. Call ix86_avx256_split_vector_move_misalign
 directly without checking mode class.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235283 138bc75d-0d04-0410-961f-82ee72b054a4

Author: H.J. Lu
Author Date: 2016-03-07 22:44:37 UTC

Extend STV pass to 64-bit mode

128-bit SSE load and store instructions can be used for load and store
of 128-bit integers if they are the only operations on 128-bit integers.
To convert load and store of 128-bit integers to 128-bit SSE load and
store, the original STV pass, which is designed to convert 64-bit integer
operations to SSE2 operations in 32-bit mode, is extended to 64-bit mode
in the following ways:

1. Class scalar_chain is turned into base class. The 32-bit specific
member functions are moved to the new derived class, dimode_scalar_chain.
The new derived class, timode_scalar_chain, is added to convert oad and
store of 128-bit integers to 128-bit SSE load and store.
2. Add the 64-bit version of scalar_to_vector_candidate_p and
remove_non_convertible_regs. Only TImode load and store are allowed
for conversion. If one instruction on the chain of dependent
instructions aren't TImode load or store, the chain of instructions
won't be converted.
3. In 64-bit, we only convert from TImode to V1TImode, which have the
same size. The difference is only vector registers are allowed in
TImode so that 128-bit SSE load and store instructions will be used
for load and store of 128-bit integers.
4. Put the 64-bit STV pass before the CSE pass so that instructions
changed or generated by the STV pass can be CSEed.

convert_scalars_to_vector calls free_dominance_info in 64-bit mode to
work around ICE in fwprop pass:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70807

when building libgcc on Linux/x86-64.

gcc/

 PR target/70155
 * config/i386/i386.c (scalar_to_vector_candidate_p): Renamed
 to ...
 (dimode_scalar_to_vector_candidate_p): This.
 (timode_scalar_to_vector_candidate_p): New function.
 (scalar_to_vector_candidate_p): Likewise.
 (timode_check_non_convertible_regs): Likewise.
 (timode_remove_non_convertible_regs): Likewise.
 (remove_non_convertible_regs): Likewise.
 (remove_non_convertible_regs): Renamed to ...
 (dimode_remove_non_convertible_regs): This.
 (scalar_chain::~scalar_chain): Make it virtual.
 (scalar_chain::compute_convert_gain): Make it pure virtual.
 (scalar_chain::mark_dual_mode_def): Likewise.
 (scalar_chain::convert_insn): Likewise.
 (scalar_chain::convert_registers): Likewise.
 (scalar_chain::add_to_queue): Make it protected.
 (scalar_chain::emit_conversion_insns): Likewise.
 (scalar_chain::replace_with_subreg): Likewise.
 (scalar_chain::replace_with_subreg_in_insn): Likewise.
 (scalar_chain::convert_op): Likewise.
 (scalar_chain::convert_reg): Likewise.
 (scalar_chain::make_vector_copies): Likewise.
 (scalar_chain::convert_registers): New pure virtual function.
 (class dimode_scalar_chain): New class.
 (class timode_scalar_chain): Likewise.
 (scalar_chain::mark_dual_mode_def): Renamed to ...
 (dimode_scalar_chain::mark_dual_mode_def): This.
 (timode_scalar_chain::mark_dual_mode_def): New function.
 (timode_scalar_chain::convert_insn): Likewise.
 (dimode_scalar_chain::convert_registers): Likewise.
 (scalar_chain::compute_convert_gain): Renamed to ...
 (dimode_scalar_chain::compute_convert_gain): This.
 (scalar_chain::replace_with_subreg): Renamed to ...
 (dimode_scalar_chain::replace_with_subreg): This.
 (scalar_chain::replace_with_subreg_in_insn): Renamed to ...
 (dimode_scalar_chain::replace_with_subreg_in_insn): This.
 (scalar_chain::make_vector_copies): Renamed to ...
 (dimode_scalar_chain::make_vector_copies): This.
 (scalar_chain::convert_reg): Renamed to ...
 (dimode_scalar_chain::convert_reg ): This.
 (scalar_chain::convert_op): Renamed to ...
 (dimode_scalar_chain::convert_op): This.
 (scalar_chain::convert_insn): Renamed to ...
 (dimode_scalar_chain::convert_insn): This.
 (scalar_chain::convert): Call convert_registers.
 (convert_scalars_to_vector): Change to scalar_chain pointer to
 use timode_scalar_chain in 64-bit mode and dimode_scalar_chain
 in 32-bit mode. Delete scalar_chain pointer. Call
 free_dominance_info in 64-bit mode.
 (pass_stv::gate): Remove TARGET_64BIT check.
 (ix86_option_override): Put the 64-bit STV pass before the CSE
 pass.

gcc/testsuite/

 PR target/70155
 * gcc.target/i386/pr55247-2.c: Updated to check movti_internal
 and movv1ti_internal patterns
 * gcc.target/i386/pr70155-1.c: New test.
 * gcc.target/i386/pr70155-2.c: Likewise.
 * gcc.target/i386/pr70155-3.c: Likewise.
 * gcc.target/i386/pr70155-4.c: Likewise.
 * gcc.target/i386/pr70155-5.c: Likewise.
 * gcc.target/i386/pr70155-6.c: Likewise.
 * gcc.target/i386/pr70155-7.c: Likewise.
 * gcc.target/i386/pr70155-8.c: Likewise.
 * gcc.target/i386/pr70155-9.c: Likewise.
 * gcc.target/i386/pr70155-10.c: Likewise.
 * gcc.target/i386/pr70155-11.c: Likewise.
 * gcc.target/i386/pr70155-12.c: Likewise.
 * gcc.target/i386/pr70155-13.c: Likewise.
 * gcc.target/i386/pr70155-14.c: Likewise.
 * gcc.target/i386/pr70155-15.c: Likewise.
 * gcc.target/i386/pr70155-16.c: Likewise.
 * gcc.target/i386/pr70155-17.c: Likewise.
 * gcc.target/i386/pr70155-18.c: Likewise.
 * gcc.target/i386/pr70155-19.c: Likewise.
 * gcc.target/i386/pr70155-20.c: Likewise.
 * gcc.target/i386/pr70155-21.c: Likewise.
 * gcc.target/i386/pr70155-22.c: Likewise.

Author: H.J. Lu
Author Date: 2016-03-07 22:44:37 UTC

Extend STV pass to 64-bit mode

128-bit SSE load and store instructions can be used for load and store
of 128-bit integers if they are the only operations on 128-bit integers.
To convert load and store of 128-bit integers to 128-bit SSE load and
store, the original STV pass, which is designed to convert 64-bit integer
operations to SSE2 operations in 32-bit mode, is extended to 64-bit mode
in the following ways:

1. Class scalar_chain is turned into base class. The 32-bit specific
member functions are moved to the new derived class, dimode_scalar_chain.
The new derived class, timode_scalar_chain, is added to convert oad and
store of 128-bit integers to 128-bit SSE load and store.
2. Add the 64-bit version of scalar_to_vector_candidate_p and
remove_non_convertible_regs. Only TImode load and store are allowed
for conversion. If one instruction on the chain of dependent
instructions aren't TImode load or store, the chain of instructions
won't be converted.
3. In 64-bit, we only convert from TImode to V1TImode, which have the
same size. The difference is only vector registers are allowed in
TImode so that 128-bit SSE load and store instructions will be used
for load and store of 128-bit integers.
4. Put the 64-bit STV pass before the CSE pass so that instructions
changed or generated by the STV pass can be CSEed.

convert_scalars_to_vector calls free_dominance_info in 64-bit mode to
work around ICE in fwprop pass:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70807

when building libgcc on Linux/x86-64.

gcc/

 PR target/70155
 * config/i386/i386.c (scalar_to_vector_candidate_p): Renamed
 to ...
 (dimode_scalar_to_vector_candidate_p): This.
 (timode_scalar_to_vector_candidate_p): New function.
 (scalar_to_vector_candidate_p): Likewise.
 (timode_check_non_convertible_regs): Likewise.
 (timode_remove_non_convertible_regs): Likewise.
 (remove_non_convertible_regs): Likewise.
 (remove_non_convertible_regs): Renamed to ...
 (dimode_remove_non_convertible_regs): This.
 (scalar_chain::~scalar_chain): Make it virtual.
 (scalar_chain::compute_convert_gain): Make it pure virtual.
 (scalar_chain::mark_dual_mode_def): Likewise.
 (scalar_chain::convert_insn): Likewise.
 (scalar_chain::convert_registers): Likewise.
 (scalar_chain::add_to_queue): Make it protected.
 (scalar_chain::emit_conversion_insns): Likewise.
 (scalar_chain::replace_with_subreg): Likewise.
 (scalar_chain::replace_with_subreg_in_insn): Likewise.
 (scalar_chain::convert_op): Likewise.
 (scalar_chain::convert_reg): Likewise.
 (scalar_chain::make_vector_copies): Likewise.
 (scalar_chain::convert_registers): New pure virtual function.
 (class dimode_scalar_chain): New class.
 (class timode_scalar_chain): Likewise.
 (scalar_chain::mark_dual_mode_def): Renamed to ...
 (dimode_scalar_chain::mark_dual_mode_def): This.
 (timode_scalar_chain::mark_dual_mode_def): New function.
 (timode_scalar_chain::convert_insn): Likewise.
 (dimode_scalar_chain::convert_registers): Likewise.
 (scalar_chain::compute_convert_gain): Renamed to ...
 (dimode_scalar_chain::compute_convert_gain): This.
 (scalar_chain::replace_with_subreg): Renamed to ...
 (dimode_scalar_chain::replace_with_subreg): This.
 (scalar_chain::replace_with_subreg_in_insn): Renamed to ...
 (dimode_scalar_chain::replace_with_subreg_in_insn): This.
 (scalar_chain::make_vector_copies): Renamed to ...
 (dimode_scalar_chain::make_vector_copies): This.
 (scalar_chain::convert_reg): Renamed to ...
 (dimode_scalar_chain::convert_reg ): This.
 (scalar_chain::convert_op): Renamed to ...
 (dimode_scalar_chain::convert_op): This.
 (scalar_chain::convert_insn): Renamed to ...
 (dimode_scalar_chain::convert_insn): This.
 (scalar_chain::convert): Call convert_registers.
 (convert_scalars_to_vector): Change to scalar_chain pointer to
 use timode_scalar_chain in 64-bit mode and dimode_scalar_chain
 in 32-bit mode. Delete scalar_chain pointer. Call
 free_dominance_info in 64-bit mode.
 (pass_stv::gate): Remove TARGET_64BIT check.
 (ix86_option_override): Put the 64-bit STV pass before the CSE
 pass.

gcc/testsuite/

 PR target/70155
 * gcc.target/i386/pr55247-2.c: Updated to check movti_internal
 and movv1ti_internal patterns
 * gcc.target/i386/pr70155-1.c: New test.
 * gcc.target/i386/pr70155-2.c: Likewise.
 * gcc.target/i386/pr70155-3.c: Likewise.
 * gcc.target/i386/pr70155-4.c: Likewise.
 * gcc.target/i386/pr70155-5.c: Likewise.
 * gcc.target/i386/pr70155-6.c: Likewise.
 * gcc.target/i386/pr70155-7.c: Likewise.
 * gcc.target/i386/pr70155-8.c: Likewise.
 * gcc.target/i386/pr70155-9.c: Likewise.
 * gcc.target/i386/pr70155-10.c: Likewise.
 * gcc.target/i386/pr70155-11.c: Likewise.
 * gcc.target/i386/pr70155-12.c: Likewise.
 * gcc.target/i386/pr70155-13.c: Likewise.
 * gcc.target/i386/pr70155-14.c: Likewise.
 * gcc.target/i386/pr70155-15.c: Likewise.
 * gcc.target/i386/pr70155-16.c: Likewise.
 * gcc.target/i386/pr70155-17.c: Likewise.
 * gcc.target/i386/pr70155-18.c: Likewise.
 * gcc.target/i386/pr70155-19.c: Likewise.
 * gcc.target/i386/pr70155-20.c: Likewise.
 * gcc.target/i386/pr70155-21.c: Likewise.
 * gcc.target/i386/pr70155-22.c: Likewise.

Author: H.J. Lu
Author Date: 2016-03-07 22:44:37 UTC

Extend STV pass to 64-bit mode

128-bit SSE load and store instructions can be used for load and store
of 128-bit integers if they are the only operations on 128-bit integers.
To convert load and store of 128-bit integers to 128-bit SSE load and
store, the original STV pass, which is designed to convert 64-bit integer
operations to SSE2 operations in 32-bit mode, is extended to 64-bit mode
in the following ways:

1. Class scalar_chain is turned into base class. The 32-bit specific
member functions are moved to the new derived class, scalar_chain_32.
The new derived class, scalar_chain_64, is added to convert oad and
store of 128-bit integers to 128-bit SSE load and store.
2. Add the 64-bit version of scalar_to_vector_candidate_p and
remove_non_convertible_regs. Only TImode load and store are allowed
for conversion. If one instruction on the chain of dependent
instructions aren't TImode load or store, the chain of instructions
won't be converted.
3. In 64-bit, we only convert from TImode to V1TImode, which have the
same size. The difference is only vector registers are allowed in
TImode so that 128-bit SSE load and store instructions will be used
for load and store of 128-bit integers.
4. Put the 64-bit STV pass before the CSE pass so that instructions
changed or generated by the STV pass can be CSEed.

gcc/

 PR target/70155
 * config/i386/i386.c (scalar_to_vector_candidate_p): Renamed
 to ...
 (scalar_to_vector_candidate_p_32): This.
 (scalar_to_vector_candidate_p_64): New function.
 (scalar_to_vector_candidate_p): Likewise.
 (check_non_convertible_regs_64): Likewise.
 (remove_non_convertible_regs_64): Likewise.
 (remove_non_convertible_regs): Likewise.
 (remove_non_convertible_regs): Renamed to ...
 (remove_non_convertible_regs_32): This.
 (scalar_chain::~scalar_chain): Make it virtual.
 (scalar_chain::compute_convert_gain): Make it pure virtual.
 (scalar_chain::convert_insn): Likewise.
 (scalar_chain::convert_registers): Likewise.
 (scalar_chain::analyze_register_chain): Likewise.
 (scalar_chain::add_to_queue): Make it protected.
 (scalar_chain::emit_conversion_insns): Likewise.
 (scalar_chain::mark_dual_mode_def): Moved to scalar_chain_32.
 (scalar_chain::replace_with_subreg): Likewise.
 (scalar_chain::replace_with_subreg_in_insn): Likewise.
 (scalar_chain::convert_op): Likewise.
 (scalar_chain::convert_reg): Likewise.
 (scalar_chain::make_vector_copies): Likewise.
 (scalar_chain::convert_registers): New pure virtual function.
 (class scalar_chain_32): New class.
 (class scalar_chain_64): Likewise.
 (scalar_chain::mark_dual_mode_def): Renamed to ...
 (scalar_chain_32::mark_dual_mode_def): This.
 (scalar_chain::analyze_register_chain): Renamed to ...
 (scalar_chain_32::analyze_register_chain ): This.
 (scalar_chain_64::analyze_register_chain): New function.
 (scalar_chain::compute_convert_gain): Renamed to ...
 (scalar_chain_32::compute_convert_gain): This.
 (scalar_chain::replace_with_subreg): Renamed to ...
 (scalar_chain_32::replace_with_subreg): This.
 (scalar_chain::replace_with_subreg_in_insn): Renamed to ...
 (scalar_chain_32::replace_with_subreg_in_insn): This.
 (scalar_chain::make_vector_copies): Renamed to ...
 (scalar_chain_32::make_vector_copies): This.
 (scalar_chain::convert_reg): Renamed to ...
 (scalar_chain_32::convert_reg ): This.
 (scalar_chain::convert_op): Renamed to ...
 (scalar_chain_32::convert_op): This.
 (scalar_chain::convert_insn): Renamed to ...
 (scalar_chain_32::convert_insn): This.
 (scalar_chain_64::convert_insn): New function.
 (scalar_chain_32::convert_registers): Likewise.
 (scalar_chain::convert): Call convert_registers.
 (convert_scalars_to_vector): Change to scalar_chain pointer to
 use scalar_chain_64 in 64-bit mode and scalar_chain_32 in 32-bit
 mode. Delete scalar_chain pointer. Call free_dominance_info in
 64-bit mode.
 (pass_stv::gate): Remove TARGET_64BIT check.
 (ix86_option_override): Put the 64-bit STV pass before the CSE
 pass.
 (standard_sse_constant_p): Allow V1TImode for all 1s.

gcc/testsuite/

 PR target/70155
 * gcc.target/i386/pr55247-2.c: Updated to check movti_internal
 and movv1ti_internal patterns
 * gcc.target/i386/pr70155-1.c: New test.
 * gcc.target/i386/pr70155-2.c: Likewise.
 * gcc.target/i386/pr70155-3.c: Likewise.
 * gcc.target/i386/pr70155-4.c: Likewise.
 * gcc.target/i386/pr70155-5.c: Likewise.
 * gcc.target/i386/pr70155-6.c: Likewise.
 * gcc.target/i386/pr70155-7.c: Likewise.
 * gcc.target/i386/pr70155-8.c: Likewise.
 * gcc.target/i386/pr70155-9.c: Likewise.
 * gcc.target/i386/pr70155-10.c: Likewise.
 * gcc.target/i386/pr70155-11.c: Likewise.
 * gcc.target/i386/pr70155-12.c: Likewise.
 * gcc.target/i386/pr70155-13.c: Likewise.
 * gcc.target/i386/pr70155-14.c: Likewise.
 * gcc.target/i386/pr70155-15.c: Likewise.
 * gcc.target/i386/pr70155-16.c: Likewise.
 * gcc.target/i386/pr70155-17.c: Likewise.
 * gcc.target/i386/pr70155-18.c: Likewise.
 * gcc.target/i386/pr70155-19.c: Likewise.
 * gcc.target/i386/pr70155-20.c: Likewise.
 * gcc.target/i386/pr70155-21.c: Likewise.
 * gcc.target/i386/pr70155-22.c: Likewise.

Author: kugan
Author Date: 2016-03-31 01:35:36 UTC

Adjust testcase patterns

Author: Andrew Pinski
Author Date: 2016-03-25 06:13:36 UTC

Handle ilp32 multiarch.

Author: Olga Golovanevsky
Author Date: 2016-02-27 03:01:29 UTC

Decompose function parameters: patch 7

Author: H.J. Lu
Author Date: 2015-12-19 14:51:44 UTC

Add vector_memory_operand and "Bm" constraint

SSE vector arithmetic and logic instructions only accept aligned memory
operand. This patch adds vector_memory_operand and "Bm" constraint for
aligned SSE memory operand. They are applied to SSE plusminus and
any_logic patterns.

gcc/

 PR target/68991
 * config/i386/constraints.md (Bm): New constraint.
 * config/i386/predicates.md (vector_memory_operand): New
 predicate.
 * config/i386/sse.md: Replace xm with xBm in plusminus and
 any_logic patterns.

gcc/testsuite/

 PR target/68991
 * g++.dg/pr68991-1.C: New test.
 * g++.dg/pr68991-2.C: Likewise.

Author: Alexandre Oliva
Author Date: 2016-02-06 07:40:21 UTC

[PR69634] fix debug_insn-inconsistent REG_N_CALLS_CROSSED

The testcase has a debug insn referencing a pseudo right before an
insn that modifies the pseudo.

Without debug insns, REG_N_CALLS_CROSSED was zero for that pseudo, so
sched_analyze_reg added a dep between the pseudo setter and an earlier
(lib)call.

With debug insns, we miscomputed REG_N_CALLS_CROSSED as nonzero
because of the debug insn, and then no dep was added between the two
insns. This was enough to change sched1's decisions about where to
place the pseudo setter.

REG_N_CALLS_CROSSED is computed by both regstat_bb_compute_ri and
regstat_bb_compute_calls_crossed, but although the former skipped
debug insns, the latter didn't.

Fixing this inconsistency was enough to fix the -fcompare-debug error.

for gcc/ChangeLog

 PR target/69634
 * regstat.c (regstat_bb_compute_calls_crossed): Disregard
 debug insns.

for gcc/testsuite/ChangeLog

 PR target/69634
 * gcc.dg/pr69634.c: New.

Author: H.J. Lu
Author Date: 2016-02-05 02:56:33 UTC

Enable STV if no stack realignment is needed

Add *movdi_to_v2di for STV to load a DI into an xmm register.