* Vendor target triples,
For assembler, the target vendor is defined as TARGET_VENDOR in the
gas/config.h, but I don't see any related settings in bfd/config.h
and opcode/config. Since we may have vendor relocations in the future,
and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR
in the bfd/config.h for riscv. The vendor name will be stored in the
bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get
the vendor name from the configure setting.
If the --with-arch configure option, -march gas option and elf architecture
attributes are not set, then we will generate the default ISA string
according to the chosen target vendor. For example, if you build the
binutils with the configure option, --target=riscv64-sifive-elf, then
the assembler will find the whole supported extension tables in the
bfd/elfxx-riscv.c, and generate the suitable ISA string.
bfd/
* configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor,
only when the target is riscv*.
* config.in: Regenerated.
* configure: Regenerated.
* cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR.
* cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE.
* elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions
for sifive.
(riscv_supported_vendor_sifive_ext): Added extensions for sifive cache
control instructions.
(riscv_supported_std_ext, riscv_all_supported_ext): Updated.
(riscv_get_default_ext_version): Updated.
(riscv_set_default_arch): Updated.
gas/
* config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added.
(riscv_extended_subset_supports): Handle INSN_CLASS_XSF*.
(op_vendor_sifive_hash): Added to store sifive opcodes.
(md_begin): Init the op_vendor_sifive_hash.
(riscv_find_extended_opcode_hash): Find the opcodes from
op_vendor_sifive_hash.
* testsuite/gas/riscv/extended/sifive-insns.d: New testcase.
* testsuite/gas/riscv/extended/sifive-insns.s: Likewise.
include/
* opcode/riscv-opc-extended.h: Added opcodes for sifive cache
instructions.
* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*.
opcodes/
* riscv-opc.c (riscv_vendor_sifive_opcodes): Added.
(riscv_extended_opcodes): Updated.
The general rule is that extension names imply the things they require.
Therefore, the current imply rules should be as follows,
- v imply f and d.
- zve64d imply d.
- zve64f and zve32f imply f.
- zvamo imply a.
Besides, consider the implicit zve and zvl extensions,
- v imply zve64d and zvl128b.
- zve64* imply the corresponding zve32*. For example, zve64f imply zve32f,
and zve64x imply zve32x.
- zve*d imply zve*f and zve*x. For example, zve64d imply zve64f and zve64x.
- zve*f imply zve*x. For example, zve64f imply zve64x.
- zve64* imply zvl64b, and zve32* imply zvl32b.
- The larger zvl* imply all smaller zvl*. For example, zvl128b imply zvl64b,
and zvl32b.
Therefore, "-march=rv64iv -misa-spec=20191213" will be
"rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0".
Note: zicsr is the imply extension of f.
* For zve32x, the (segmant) load/store instructions are illegal when EEW is
64. Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled.
* For zvl*b extensions, we also need to enable either v or zve* extensions.
Otherwise we should issue errors.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v,
zve* and zvl*b extensions.
(riscv_supported_std_z_ext): Added zve* and zvl*b extensions.
(riscv_parse_check_conflicts): The zvl*b extensions cannot be set
without v and zve* extensions.
gas/
* config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*.
(my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli
when zve32* is enabled.
(riscv_ip): The (segmant) loads and stores with EEW 64 cannot be
used when zve32x is enabled.
* testsuite/gas/riscv/extended/march-imply-v.d: New testcase.
* testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise.
* testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed
a-ext from -march since it will be added as implicit ext for zvamo.
* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
include/
* opcode/riscv.h: Defined INSN_V_EEW64.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector
loads and stores when the eew encodings are 64.
RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.
* Separate zvamo from v extension with v1.0, but keep the implementations.
* Removed zvlsseg extension name as the vector segmant loads and stores
are required (included) in v extension.
* Updated the versions of v and zvamo from draft v0.10 to frozen v1.0.
bfd/
* elfxx-riscv.c (riscv_supported_std_z_ext): Removed entry of zvlsseg.
gas/
* config/tc-riscv.c (riscv_extended_subset_supports): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed
INSN_CLASS_V_OR_ZVLSSEG.
(riscv_extended_csr_class_check): Updated since the name zvlsseg
is removed.
* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed
-march from rv32iav to rv32ia_zvamo.
* testsuite/gas/riscv/extended/vector-insns.d: Changed -march from
rv32iafv to rv32iafv_zvamo.
include/
* opcode/riscv.h (riscv_extended_insn_class): Changed
INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed
INSN_CLASS_V_OR_ZVLSSEG.
opcodes/
* riscv-opc.c (riscv_draft_opcodes): Changed INSN_CLASS_V_OR_ZVAMO
to INSN_CLASS_ZVAMO since they are separated from v. Also changed
INSN_CLASS_V_OR_ZVLSSEG to INSN_CLASS_V as they are included in v.
RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.
* Added pseudo instruction,
- vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs
* Changed assembler mnemonics, and the older names kept as aliases,
- Changed from vle1.v to vlm.v, and vse1.v to vsm.v.
- Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively.
- Changed from vpopc.m to vcpop.m, to be consistent with scalar instruction.
- Changed from vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.
RISC-V/t-head: Add CSRs and opcodes of the T-HEAD XUANTIE CPUs
Add CSRs and opcodes of the XUANTIE CPUs, extensions named "theadc",
"xtheade" and "xtheadse".
New ARG format for operands:
"Xgm@n": encode GPR with m bit at opcode[m+n-1:n].
"Xg5@0": encode GPR with 5 bit at opcode[4:0].
"Xg5@8": encode GPR with 5 bit at opcode[12:8].
"XIm@n": m bits unsigned immediate at opcode[m+n-1:n].
"XI5@0": 5 bits unsigned immediate at opcode[4:0].
"XI4@8": 4 bits unsigned immediate at opcode[11:8].
"XSm@n": m bits signed immediate at opcode[m+n-1:n].
"XS5@0": 5 bits signed immediate at opcode[4:0].
"XS4@8": 4 bits signed immediate at opcode[11:8].
"XFm@n": m bits FR at opcode[m+n-1:n].
"XF5@0": 5 bits FR at opcode[4:0].
"XF5@0": 5 bits FR at opcode[4:0].
There are five new instructions for svinval extension. According to
the above draft spec, two of them (HINVAL.VVMA and HINVAL.GVMA) need
to enable the hypervisor extension. But there is no implementation
of hypervisor extension in mainline, so let's consider the related
issues later.
RISC-V/zfh: Added big endian testcase for .float16 directive.
gas/
* testsuite/gas/riscv/extended/extended.exp: Updated.
* testsuite/gas/riscv/extended/float16.s: Minor fix for sNaNh.
* testsuite/gas/riscv/extended/float16-le.d: Updated and renamed
from float16.d.
* testsuite/gas/riscv/extended/float16-be.d: New testcase.
RISC-V/zfh: Support .float16 directive for assembler.
This probably need to be sent to mainline rather than here.
gas/
* config/tc-riscv.c (FLT_CHARS): Added h and H.
(riscv_pseudo_table): Added .float16.
* read.c (hex_float): Handle case 'h' and 'H'.
* testsuite/gas/riscv/extended/extended.exp: Updated.
* testsuite/gas/riscv/extended/float16.d: New testcase.
* testsuite/gas/riscv/extended/float16.s: Likewise.
