Add reserving memory node to the StarFive VisionFive 2 device tree
telling linux to avoid memory used by OpenSBI. This avoids an error when
booting through their U-Boots EFI implementation.
Signed-off-by: Emil Renner Berthing <email address hidden>
CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.
So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock
and the divider of cpu_core before the setting.
Reviewed-by: Hal Feng <email address hidden>
Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <email address hidden>
(cherry picked from https://<email address hidden>)
Signed-off-by: Emil Renner Berthing <email address hidden>
As the Starfive JH7110 hardware can't keep two inbound post write in
order all the time, such as MSI messages and NVMe completions. If the
NVMe completion update later than the MSI, an NVMe IRQ handle will miss.
As a workaround, we will wait a while before going to the generic
handle here.
Verified with NVMe SSD, USB SSD, R8169 NIC.
The performance are stable and even higher after this patch.
Signed-off-by: Kevin Xie <email address hidden>
Signed-off-by: Minda Chen <email address hidden>
(cherry picked from https://<email address hidden>)
Signed-off-by: Emil Renner Berthing <email address hidden>
