drm/i915: convert vlv_dpio_read()/write() from pipe to phy
vlv_dpio_read() and vlv_dpio_write() really operate on the phy, not
pipe. Passing the pipe instead of the phy as parameter is supposed to be
a convenience, but when the caller has the phy, it becomes an
inconvenience. See e.g. chv_dpio_cmn_power_well_enable() and
assert_chv_phy_powergate().
Figure out the phy in the callers, and pass phy to the dpio functions.
v2: retract one overzealous pipe->phy change (Ville)
Reviewed-by: Ville Syrjälä <email address hidden>
Signed-off-by: Jani Nikula <email address hidden>
Link: https://patchwork.<email address hidden>
drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY()
Add a helper with better typing and handing for bogus input, and better
in line with vlv_dig_port_to_channel(), vlv_dig_port_to_phy(), and
vlv_pipe_to_channel().
Reviewed-by: Ville Syrjälä <email address hidden>
Signed-off-by: Jani Nikula <email address hidden>
Link: https://patchwork.<email address hidden>
98ed369...
by
Animesh Manna <email address hidden>
drm/i915/dsb: DSB code refactoring
Refactor DSB implementation to be compatible with Xe driver.
v1: RFC version.
v2: Make intel_dsb structure opaque from external usage. [Jani]
v3: Rebased on latest.
v4:
- Add boundary check in dsb_buffer_memset(). [Luca]
- Use size_t instead of u32. [Luca]
v5: WARN_ON() added for out of boudary case with some optimization. [Luca]
v6: Rebased on latest and fix a rebase-miss.
ef75c25...
by
Animesh Manna <email address hidden>
drm/i915/panelreplay: Debugfs support for panel replay
Add debugfs support which will print source and sink status
per connector basis. Existing i915_psr_status and
i915_psr_sink_status will be used to get the source and
sink status of panel replay.
v1: Initial version. [rb-ed by Arun]
v2: Added check for DP 2.0 and connector type in connector_debugfs_add().
v3: Optimization and cosmetic changes. [Jouni]
8a4353d...
by
Vinod Govindapillai <email address hidden>
drm/i915/xe2lpd: implement WA for underruns while enabling FBC
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
At least one TGL had regression when using u8 types
for entry setup frames calculation. So, let's switch
to use ints instead.
intel_psr_entry_setup_frames() function expects
to return u8 but since in case of error the error
code -ETIME is returned. This doesn't fit into u8
and hence the return value is not as expected.
Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier")
Signed-off-by: Mika Kahola <email address hidden>
Reviewed-by: Jouni Högander <email address hidden>
Link: https://patchwork<email address hidden>
