lp:beignet

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2070. By Junyan He <email address hidden> on 2015-02-04

Fix a bug of 1d image array test case.

Because of the HW limitation, vertical stride is at
least aligned to 2. For 1D array image, the data has interval.
The image size is just twice as big as the buffer size we think.
Use clEnqueueWriteImage is safe and fix this bug.

Signed-off-by: Junyan He <email address hidden>
Reviewed-by: Zhigang Gong <email address hidden>

2069. By Ruiling Song <email address hidden> on 2015-02-04

GBE: Fix a build error against llvm release version

The DEBUG macro will try to link llvm::DebugFlag and llvm::isCurrentDebugType()
which is absent in release version of LLVM library. So define it to empty.
The problem occurs when building debug version of beignet against the
release version of llvm.

Signed-off-by: Ruiling Song <email address hidden>
Tested-by: "Meng, Mengmeng" <email address hidden>

2068. By Ruiling Song <email address hidden> on 2015-02-03

GBE: expand large integer instructions

The pass is also from PNaCl. which lower large integer into smaller ones.
But different from previous legalize pass. It is easy to handle various
instructions like load or phi with large integer operand.

I find that instruction combine may make me hard to totally eliminate
empty block. As CFG simplify pass may generate switch-case when preventing
empty block. And Switch lower pass after CFG simplify may make empty block
still exist in Gen IR. So, I temporarily disable the empty block check in backend.

Signed-off-by: Ruiling Song <email address hidden>

2067. By Ruiling Song <email address hidden> on 2015-02-03

GBE: Import constantexpr lower pass from pNaCl

The idea is lower the constantExpr into an Instruction.

Fix the ptrtoInt and IntToPtr implementation, it simply maps to
a convert if type size not the same.

Fix a bitcast from integer to float issue. As we expand llvm::ConstantExpr
into llvm::Instruction. We will meet below situation.
  %10 = bitcast i32 1073741824 to float
  %11 = fcmp float %10 0.000000e+00
This will translated into GenIR:
  %100 = loadi S32 1073741824
  %101 = fcmp %100, 0.0f
In later instruction selection, we may directly getFloat() from %100

Signed-off-by: Ruiling Song <email address hidden>

2066. By Junyan He <email address hidden> on 2015-01-30

Re-format the asm print for long imm

Use decimal to print signed long and use hex to print
unsigned long, which make the format more clear.

v2:
change %ld to %lld.

Signed-off-by: Junyan He <email address hidden>
Reviewed-by: Zhigang Gong <email address hidden>

2065. By Junyan He <email address hidden> on 2015-01-30

Backend: fix one bug of long mad_sat.

The bug caused because we didn't consider two overflow
cases when type is long, which do not cause carry and
are easy to be ignored.

V2:
   Clean some verbose NOPs.

Signed-off-by: Junyan He <email address hidden>
Reviewed-by: Zhigang Gong <email address hidden>

2064. By Luo Xionghu <email address hidden> on 2015-01-30

remove the libFunc interface.

the copysignf function is handled in libocl already.
v2: also remove the llvm intrinsic copysign function.

Signed-off-by: Luo Xionghu <email address hidden>
Reviewed-by: Zhigang Gong <email address hidden>

2063. By Yang Rong <email address hidden> on 2015-01-30

SKL: fix skl LD fail.

Skl's LD message payload order is changed from u, lod, v, w to u, v, lod, w.
Add the Gen9Context and Selection9 to handle it.
Skl Still use Gen8Encoder.

Signed-off-by: Yang Rong <email address hidden>
Reviewed-by: He Junyan <email address hidden>

2062. By Yang Rong <email address hidden> on 2015-01-30

SKL: Add function intel_gpgpu_bind_image_gen9.

SKL's qpitch is difference with BDW. And SURFTYPE_1D's qpitch means distance in pixels between array slices.
So add two parameters slice_pitch and bpp to calculate it.

Signed-off-by: Yang Rong <email address hidden>
Reviewed-by: He Junyan <email address hidden>

2061. By Yang Rong <email address hidden> on 2015-01-30

SKL: add skl select_pipeline and cache_control functions.

The skl's cache control field in the surface state changed index to the pre-defined registers.
Because index 9 is what beignet need, use it directly.
Skl's select_pipeline command need the mask, add intel_gpgpu_select_pipeline_gen9 for it.

Signed-off-by: Yang Rong <email address hidden>
Reviewed-by: He Junyan <email address hidden>