/**
 * STA Reflex constants, definitions, ..
 * Copyright (C) 2011 Petr Kubanek, Institute of Physics <kubanek@fzu.cz>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#ifndef __RTS2_REFLEX_H__
#define __RTS2_REFLEX_H__


#define FIXED_BOARD_COUNT          4
#define MAX_DAUGHTER_COUNT         8
#define TOTAL_BOARD_COUNT         12
#define PARAM_COUNT               64

// Maximum number of tap entries for deinterlacing
#define MAX_TAP_COUNT             32
#define MAX_PROTOTYPE_TAP_COUNT   24

// Maximum number of ADCs per daughter board
#define MAX_ADC_COUNT 8


#define SYSTEM_CONTROL_ADDR       0x10000000
#define SYSTEM_STATUS_ADDR        0x00000000
#define ERROR_SYSTEM_STATUS_ADDR  0x40000000

// Board type values
#define BT_NONE                   0x00
#define BT_BPX6                   0x10
#define BT_CLIF                   0x20
#define BT_PA                     0x30
#define BT_PB                     0x40
#define BT_AD8X120                0x50
#define BT_AD8X100                0x51
#define BT_DRIVER                 0x60
#define BT_BIAS                   0x70
#define BT_HS                     0x80

// System board index numbers
enum BOARD_INDICES
{
        BOARD_BP,
        BOARD_IF,
        BOARD_PA,
        BOARD_PB,
        BOARD_DAUGHTERS
};

// System status registers, starting at address 0x00000000
enum SYSTEM_STATUS_FIELDS
{
	ERROR_CODE,
	ERROR_SRC,
	ERROR_LINE,
	STATUS_INDEX,
	POWER,
	BOARD_TYPE_BP,
	BOARD_TYPE_IF,
	BOARD_TYPE_PA,
	BOARD_TYPE_PB,
	BOARD_TYPE_D1,
	BOARD_TYPE_D2,
	BOARD_TYPE_D3,
	BOARD_TYPE_D4,
	BOARD_TYPE_D5,
	BOARD_TYPE_D6,
	BOARD_TYPE_D7,
	BOARD_TYPE_D8,
	ROMID_BP,
	ROMID_IF,
	ROMID_PA,
	ROMID_PB,
	ROMID_D1,
	ROMID_D2,
	ROMID_D3,
	ROMID_D4,
	ROMID_D5,
	ROMID_D6,
	ROMID_D7,
	ROMID_D8,
	BUILD_BP,
	BUILD_IF,
	BUILD_PA,
	BUILD_PB,
	BUILD_D1,
	BUILD_D2,
	BUILD_D3,
	BUILD_D4,
	BUILD_D5,
	BUILD_D6,
	BUILD_D7,
	BUILD_D8,
	FLAGS_BP,
	FLAGS_IF,
	FLAGS_PA,
	FLAGS_PB,
	FLAGS_D1,
	FLAGS_D2,
	FLAGS_D3,
	FLAGS_D4,
	FLAGS_D5,
	FLAGS_D6,
	FLAGS_D7,
	FLAGS_D8,
	SYSTEM_STATUS_SIZE
};

enum BACKPLANE_CONTROL_FIELDS
{
	BACKPLANE_MCLK,
	BACKPLANE_DAUGHTER_ENABLE,
	BACKPLANE_TAP_COUNT,
	BACKPLANE_TAP_LENGTH,
	BACKPLANE_TAPA_ENABLE,
	BACKPLANE_TAPB_ENABLE,
	BACKPLANE_TAPA_7_0_SOURCE,
	BACKPLANE_TAPA_15_8_SOURCE,
	BACKPLANE_TAPA_23_16_SOURCE,
	BACKPLANE_TAPB_7_0_SOURCE,
	BACKPLANE_TAPB_15_8_SOURCE,
	BACKPLANE_TAPB_23_16_SOURCE,
	BACKPLANE_TAPA_0_START,
	BACKPLANE_TAPA_1_START,
	BACKPLANE_TAPA_2_START,
	BACKPLANE_TAPA_3_START,
	BACKPLANE_TAPA_4_START,
	BACKPLANE_TAPA_5_START,
	BACKPLANE_TAPA_6_START,
	BACKPLANE_TAPA_7_START,
	BACKPLANE_TAPA_8_START,
	BACKPLANE_TAPA_9_START,
	BACKPLANE_TAPA_10_START,
	BACKPLANE_TAPA_11_START,
	BACKPLANE_TAPA_12_START,
	BACKPLANE_TAPA_13_START,
	BACKPLANE_TAPA_14_START,
	BACKPLANE_TAPA_15_START,
	BACKPLANE_TAPA_16_START,
	BACKPLANE_TAPA_17_START,
	BACKPLANE_TAPA_18_START,
	BACKPLANE_TAPA_19_START,
	BACKPLANE_TAPA_20_START,
	BACKPLANE_TAPA_21_START,
	BACKPLANE_TAPA_22_START,
	BACKPLANE_TAPA_23_START,
	BACKPLANE_TAPB_0_START,
	BACKPLANE_TAPB_1_START,
	BACKPLANE_TAPB_2_START,
	BACKPLANE_TAPB_3_START,
	BACKPLANE_TAPB_4_START,
	BACKPLANE_TAPB_5_START,
	BACKPLANE_TAPB_6_START,
	BACKPLANE_TAPB_7_START,
	BACKPLANE_TAPB_8_START,
	BACKPLANE_TAPB_9_START,
	BACKPLANE_TAPB_10_START,
	BACKPLANE_TAPB_11_START,
	BACKPLANE_TAPB_12_START,
	BACKPLANE_TAPB_13_START,
	BACKPLANE_TAPB_14_START,
	BACKPLANE_TAPB_15_START,
	BACKPLANE_TAPB_16_START,
	BACKPLANE_TAPB_17_START,
	BACKPLANE_TAPB_18_START,
	BACKPLANE_TAPB_19_START,
	BACKPLANE_TAPB_20_START,
	BACKPLANE_TAPB_21_START,
	BACKPLANE_TAPB_22_START,
	BACKPLANE_TAPB_23_START,
	BACKPLANE_TAPA_0_DELTA,
	BACKPLANE_TAPA_1_DELTA,
	BACKPLANE_TAPA_2_DELTA,
	BACKPLANE_TAPA_3_DELTA,
	BACKPLANE_TAPA_4_DELTA,
	BACKPLANE_TAPA_5_DELTA,
	BACKPLANE_TAPA_6_DELTA,
	BACKPLANE_TAPA_7_DELTA,
	BACKPLANE_TAPA_8_DELTA,
	BACKPLANE_TAPA_9_DELTA,
	BACKPLANE_TAPA_10_DELTA,
	BACKPLANE_TAPA_11_DELTA,
	BACKPLANE_TAPA_12_DELTA,
	BACKPLANE_TAPA_13_DELTA,
	BACKPLANE_TAPA_14_DELTA,
	BACKPLANE_TAPA_15_DELTA,
	BACKPLANE_TAPA_16_DELTA,
	BACKPLANE_TAPA_17_DELTA,
	BACKPLANE_TAPA_18_DELTA,
	BACKPLANE_TAPA_19_DELTA,
	BACKPLANE_TAPA_20_DELTA,
	BACKPLANE_TAPA_21_DELTA,
	BACKPLANE_TAPA_22_DELTA,
	BACKPLANE_TAPA_23_DELTA,
	BACKPLANE_TAPB_0_DELTA,
	BACKPLANE_TAPB_1_DELTA,
	BACKPLANE_TAPB_2_DELTA,
	BACKPLANE_TAPB_3_DELTA,
	BACKPLANE_TAPB_4_DELTA,
	BACKPLANE_TAPB_5_DELTA,
	BACKPLANE_TAPB_6_DELTA,
	BACKPLANE_TAPB_7_DELTA,
	BACKPLANE_TAPB_8_DELTA,
	BACKPLANE_TAPB_9_DELTA,
	BACKPLANE_TAPB_10_DELTA,
	BACKPLANE_TAPB_11_DELTA,
	BACKPLANE_TAPB_12_DELTA,
	BACKPLANE_TAPB_13_DELTA,
	BACKPLANE_TAPB_14_DELTA,
	BACKPLANE_TAPB_15_DELTA,
	BACKPLANE_TAPB_16_DELTA,
	BACKPLANE_TAPB_17_DELTA,
	BACKPLANE_TAPB_18_DELTA,
	BACKPLANE_TAPB_19_DELTA,
	BACKPLANE_TAPB_20_DELTA,
	BACKPLANE_TAPB_21_DELTA,
	BACKPLANE_TAPB_22_DELTA,
	BACKPLANE_TAPB_23_DELTA,
	BACKPLANE_READ_COUNT,
	BACKPLANE_PRE_COUNT,
	BACKPLANE_POST_COUNT,
	BACKPLANE_CONTROL_SIZE
};

enum BACKPLANE_REVB_CONTROL_FIELDS
{
        BACKPLANE_REVB_MCLK,
        BACKPLANE_REVB_DAUGHTER_ENABLE,
        BACKPLANE_REVB_TAP_COUNT,
        BACKPLANE_REVB_TAPA_SOURCE0,
        BACKPLANE_REVB_TAPA_SOURCE1,
        BACKPLANE_REVB_TAPA_SOURCE2,
        BACKPLANE_REVB_TAPA_SOURCE3,
        BACKPLANE_REVB_TAPB_SOURCE0,
        BACKPLANE_REVB_TAPB_SOURCE1,
        BACKPLANE_REVB_TAPB_SOURCE2,
        BACKPLANE_REVB_TAPB_SOURCE3,
        BACKPLANE_REVB_PCLK,
        BACKPLANE_REVB_TRIGIN,
        BACKPLANE_REVB_CONTROL_SIZE
};

enum INTERFACE_REVC_CONTROL_FIELDS
{
	INTERFACE_REVC_TAP_COUNT,
	INTERFACE_REVC_LOOP_COUNT,
	INTERFACE_REVC_TAPA_ENABLE,
	INTERFACE_REVC_TAPB_ENABLE,
	INTERFACE_REVC_TAPA_0_START,
	INTERFACE_REVC_TAPA_1_START,
	INTERFACE_REVC_TAPA_2_START,
	INTERFACE_REVC_TAPA_3_START,
	INTERFACE_REVC_TAPA_4_START,
	INTERFACE_REVC_TAPA_5_START,
	INTERFACE_REVC_TAPA_6_START,
	INTERFACE_REVC_TAPA_7_START,
	INTERFACE_REVC_TAPA_8_START,
	INTERFACE_REVC_TAPA_9_START,
	INTERFACE_REVC_TAPA_10_START,
	INTERFACE_REVC_TAPA_11_START,
	INTERFACE_REVC_TAPA_12_START,
	INTERFACE_REVC_TAPA_13_START,
	INTERFACE_REVC_TAPA_14_START,
	INTERFACE_REVC_TAPA_15_START,
	INTERFACE_REVC_TAPA_16_START,
	INTERFACE_REVC_TAPA_17_START,
	INTERFACE_REVC_TAPA_18_START,
	INTERFACE_REVC_TAPA_19_START,
	INTERFACE_REVC_TAPA_20_START,
	INTERFACE_REVC_TAPA_21_START,
	INTERFACE_REVC_TAPA_22_START,
	INTERFACE_REVC_TAPA_23_START,
	INTERFACE_REVC_TAPA_24_START,
	INTERFACE_REVC_TAPA_25_START,
	INTERFACE_REVC_TAPA_26_START,
	INTERFACE_REVC_TAPA_27_START,
	INTERFACE_REVC_TAPA_28_START,
	INTERFACE_REVC_TAPA_29_START,
	INTERFACE_REVC_TAPA_30_START,
	INTERFACE_REVC_TAPA_31_START,
	INTERFACE_REVC_TAPB_0_START,
	INTERFACE_REVC_TAPB_1_START,
	INTERFACE_REVC_TAPB_2_START,
	INTERFACE_REVC_TAPB_3_START,
	INTERFACE_REVC_TAPB_4_START,
	INTERFACE_REVC_TAPB_5_START,
	INTERFACE_REVC_TAPB_6_START,
	INTERFACE_REVC_TAPB_7_START,
	INTERFACE_REVC_TAPB_8_START,
	INTERFACE_REVC_TAPB_9_START,
	INTERFACE_REVC_TAPB_10_START,
	INTERFACE_REVC_TAPB_11_START,
	INTERFACE_REVC_TAPB_12_START,
	INTERFACE_REVC_TAPB_13_START,
	INTERFACE_REVC_TAPB_14_START,
	INTERFACE_REVC_TAPB_15_START,
	INTERFACE_REVC_TAPB_16_START,
	INTERFACE_REVC_TAPB_17_START,
	INTERFACE_REVC_TAPB_18_START,
	INTERFACE_REVC_TAPB_19_START,
	INTERFACE_REVC_TAPB_20_START,
	INTERFACE_REVC_TAPB_21_START,
	INTERFACE_REVC_TAPB_22_START,
	INTERFACE_REVC_TAPB_23_START,
	INTERFACE_REVC_TAPB_24_START,
	INTERFACE_REVC_TAPB_25_START,
	INTERFACE_REVC_TAPB_26_START,
	INTERFACE_REVC_TAPB_27_START,
	INTERFACE_REVC_TAPB_28_START,
	INTERFACE_REVC_TAPB_29_START,
	INTERFACE_REVC_TAPB_30_START,
	INTERFACE_REVC_TAPB_31_START,
	INTERFACE_REVC_TAPA_0_DELTA,
	INTERFACE_REVC_TAPA_1_DELTA,
	INTERFACE_REVC_TAPA_2_DELTA,
	INTERFACE_REVC_TAPA_3_DELTA,
	INTERFACE_REVC_TAPA_4_DELTA,
	INTERFACE_REVC_TAPA_5_DELTA,
	INTERFACE_REVC_TAPA_6_DELTA,
	INTERFACE_REVC_TAPA_7_DELTA,
	INTERFACE_REVC_TAPA_8_DELTA,
	INTERFACE_REVC_TAPA_9_DELTA,
	INTERFACE_REVC_TAPA_10_DELTA,
	INTERFACE_REVC_TAPA_11_DELTA,
	INTERFACE_REVC_TAPA_12_DELTA,
	INTERFACE_REVC_TAPA_13_DELTA,
	INTERFACE_REVC_TAPA_14_DELTA,
	INTERFACE_REVC_TAPA_15_DELTA,
	INTERFACE_REVC_TAPA_16_DELTA,
	INTERFACE_REVC_TAPA_17_DELTA,
	INTERFACE_REVC_TAPA_18_DELTA,
	INTERFACE_REVC_TAPA_19_DELTA,
	INTERFACE_REVC_TAPA_20_DELTA,
	INTERFACE_REVC_TAPA_21_DELTA,
	INTERFACE_REVC_TAPA_22_DELTA,
	INTERFACE_REVC_TAPA_23_DELTA,
	INTERFACE_REVC_TAPA_24_DELTA,
	INTERFACE_REVC_TAPA_25_DELTA,
	INTERFACE_REVC_TAPA_26_DELTA,
	INTERFACE_REVC_TAPA_27_DELTA,
	INTERFACE_REVC_TAPA_28_DELTA,
	INTERFACE_REVC_TAPA_29_DELTA,
	INTERFACE_REVC_TAPA_30_DELTA,
	INTERFACE_REVC_TAPA_31_DELTA,
	INTERFACE_REVC_TAPB_0_DELTA,
	INTERFACE_REVC_TAPB_1_DELTA,
	INTERFACE_REVC_TAPB_2_DELTA,
	INTERFACE_REVC_TAPB_3_DELTA,
	INTERFACE_REVC_TAPB_4_DELTA,
	INTERFACE_REVC_TAPB_5_DELTA,
	INTERFACE_REVC_TAPB_6_DELTA,
	INTERFACE_REVC_TAPB_7_DELTA,
	INTERFACE_REVC_TAPB_8_DELTA,
	INTERFACE_REVC_TAPB_9_DELTA,
	INTERFACE_REVC_TAPB_10_DELTA,
	INTERFACE_REVC_TAPB_11_DELTA,
	INTERFACE_REVC_TAPB_12_DELTA,
	INTERFACE_REVC_TAPB_13_DELTA,
	INTERFACE_REVC_TAPB_14_DELTA,
	INTERFACE_REVC_TAPB_15_DELTA,
	INTERFACE_REVC_TAPB_16_DELTA,
	INTERFACE_REVC_TAPB_17_DELTA,
	INTERFACE_REVC_TAPB_18_DELTA,
	INTERFACE_REVC_TAPB_19_DELTA,
	INTERFACE_REVC_TAPB_20_DELTA,
	INTERFACE_REVC_TAPB_21_DELTA,
	INTERFACE_REVC_TAPB_22_DELTA,
	INTERFACE_REVC_TAPB_23_DELTA,
	INTERFACE_REVC_TAPB_24_DELTA,
	INTERFACE_REVC_TAPB_25_DELTA,
	INTERFACE_REVC_TAPB_26_DELTA,
	INTERFACE_REVC_TAPB_27_DELTA,
	INTERFACE_REVC_TAPB_28_DELTA,
	INTERFACE_REVC_TAPB_29_DELTA,
	INTERFACE_REVC_TAPB_30_DELTA,
	INTERFACE_REVC_TAPB_31_DELTA,
	INTERFACE_REVC_LINE_LENGTH,
	INTERFACE_REVC_PRE_COUNT,
	INTERFACE_REVC_POST_COUNT,
	INTERFACE_REVC_LINE_COUNT,
	INTERFACE_REVC_IDLE_COUNT,
	INTERFACE_REVC_CL_MODE,
	INTERFACE_REVC_CL_SPEED,
	INTERFACE_REVC_CONTROL_SIZE
};

enum POWERA_CONTROL_FIELDS
{
	POWERA_CONTROL_SIZE
};

enum POWERB_CONTROL_FIELDS
{
	POWERB_TEC_SETPOINT,
	POWERB_CONTROL_SIZE
};

enum AD8X120_CONTROL_FIELDS
{
	AD8X120_CLAMP_LOW,
	AD8X120_CLAMP_HIGH,
	AD8X120_RAW_MODE,
	AD8X120_RAW_CHANNEL,
	AD8X120_CDS_OFFSET,
	AD8X120_SHP_TOGGLE1,
	AD8X120_SHP_TOGGLE2,
	AD8X120_SHD_TOGGLE1,
	AD8X120_SHD_TOGGLE2,
	AD8X120_CONTROL_SIZE
};

enum AD8X100_CONTROL_FIELDS
{
	AD8X100_CLAMP_LOW,
	AD8X100_CLAMP_HIGH,
	AD8X100_RAW_MODE,
	AD8X100_RAW_CHANNEL,
	AD8X100_CDS_GAIN,
	AD8X100_CDS_OFFSET,
	AD8X100_CDS_MODE,
	AD8X100_SHP_TOGGLE1,
	AD8X100_SHP_TOGGLE2,
	AD8X100_SHD_TOGGLE1,
	AD8X100_SHD_TOGGLE2,
	AD8X100_CONTROL_SIZE
};

enum DRIVER_CONTROL_FIELDS
{
	DRIVER_ENABLE,
	DRIVER_DRV1_LOW,
	DRIVER_DRV1_HIGH,
	DRIVER_DRV1_SLEW,
	DRIVER_DRV2_LOW,
	DRIVER_DRV2_HIGH,
	DRIVER_DRV2_SLEW,
	DRIVER_DRV3_LOW,
	DRIVER_DRV3_HIGH,
	DRIVER_DRV3_SLEW,
	DRIVER_DRV4_LOW,
	DRIVER_DRV4_HIGH,
	DRIVER_DRV4_SLEW,
	DRIVER_DRV5_LOW,
	DRIVER_DRV5_HIGH,
	DRIVER_DRV5_SLEW,
	DRIVER_DRV6_LOW,
	DRIVER_DRV6_HIGH,
	DRIVER_DRV6_SLEW,
	DRIVER_DRV7_LOW,
	DRIVER_DRV7_HIGH,
	DRIVER_DRV7_SLEW,
	DRIVER_DRV8_LOW,
	DRIVER_DRV8_HIGH,
	DRIVER_DRV8_SLEW,
	DRIVER_DRV9_LOW,
	DRIVER_DRV9_HIGH,
	DRIVER_DRV9_SLEW,
	DRIVER_DRV10_LOW,
	DRIVER_DRV10_HIGH,
	DRIVER_DRV10_SLEW,
	DRIVER_DRV11_LOW,
	DRIVER_DRV11_HIGH,
	DRIVER_DRV11_SLEW,
	DRIVER_DRV12_LOW,
	DRIVER_DRV12_HIGH,
	DRIVER_DRV12_SLEW,
	DRIVER_DRV1_A,
	DRIVER_DRV1_B,
	DRIVER_DRV2_A,
	DRIVER_DRV2_B,
	DRIVER_DRV3_A,
	DRIVER_DRV3_B,
	DRIVER_DRV4_A,
	DRIVER_DRV4_B,
	DRIVER_DRV5_A,
	DRIVER_DRV5_B,
	DRIVER_DRV6_A,
	DRIVER_DRV6_B,
	DRIVER_DRV7_A,
	DRIVER_DRV7_B,
	DRIVER_DRV8_A,
	DRIVER_DRV8_B,
	DRIVER_DRV9_A,
	DRIVER_DRV9_B,
	DRIVER_DRV10_A,
	DRIVER_DRV10_B,
	DRIVER_DRV11_A,
	DRIVER_DRV11_B,
	DRIVER_DRV12_A,
	DRIVER_DRV12_B,
	DRIVER_CONTROL_SIZE
};

enum BIAS_CONTROL_FIELDS
{
	BIAS_ENABLE,
	BIAS_SET_LV1,
	BIAS_SET_LV2,
	BIAS_SET_LV3,
	BIAS_SET_LV4,
	BIAS_SET_LV5,
	BIAS_SET_LV6,
	BIAS_SET_LV7,
	BIAS_SET_LV8,
	BIAS_SET_HV1,
	BIAS_SET_HV2,
	BIAS_SET_HV3,
	BIAS_SET_HV4,
	BIAS_SET_HV5,
	BIAS_SET_HV6,
	BIAS_SET_HV7,
	BIAS_SET_HV8,
	BIAS_SET_LC1,
	BIAS_SET_LC2,
	BIAS_SET_LC3,
	BIAS_SET_LC4,
	BIAS_SET_LC5,
	BIAS_SET_LC6,
	BIAS_SET_LC7,
	BIAS_SET_LC8,
	BIAS_SET_HC1,
	BIAS_SET_HC2,
	BIAS_SET_HC3,
	BIAS_SET_HC4,
	BIAS_SET_HC5,
	BIAS_SET_HC6,
	BIAS_SET_HC7,
	BIAS_SET_HC8,
	BIAS_ORDER_LV1,
	BIAS_ORDER_LV2,
	BIAS_ORDER_LV3,
	BIAS_ORDER_LV4,
	BIAS_ORDER_LV5,
	BIAS_ORDER_LV6,
	BIAS_ORDER_LV7,
	BIAS_ORDER_LV8,
	BIAS_ORDER_HV1,
	BIAS_ORDER_HV2,
	BIAS_ORDER_HV3,
	BIAS_ORDER_HV4,
	BIAS_ORDER_HV5,
	BIAS_ORDER_HV6,
	BIAS_ORDER_HV7,
	BIAS_ORDER_HV8,
	BIAS_CONTROL_SIZE
};

enum HS_CONTROL_FIELDS
{
	HS_RG_RISING_EDGE,
	HS_RG_FALLING_EDGE,
	HS_S1_RISING_EDGE,
	HS_S1_FALLING_EDGE,
	HS_S2_RISING_EDGE,
	HS_S2_FALLING_EDGE,
	HS_S3_RISING_EDGE,
	HS_S3_FALLING_EDGE,
	HS_S4_RISING_EDGE,
	HS_S4_FALLING_EDGE,
	HS_S5_RISING_EDGE,
	HS_S5_FALLING_EDGE,
	HS_S6_RISING_EDGE,
	HS_S6_FALLING_EDGE,
	HS_LINE_LENGTH,
	HS_CLPOB_START,
	HS_CLPOB_END,
	HS_CLPOB_LEVEL,
	HS_S1_HIGH,
	HS_S2_HIGH,
	HS_S3_HIGH,
	HS_S4_HIGH,
	HS_S5_HIGH,
	HS_S6_HIGH,
	HS_LVDS_TEST,
	HS_TCLK_DELAY,
	HS_DOUT_PHASE,
	HS_SHP_LOC,
	HS_SHP_WIDTH,
	HS_SHD_LOC,
	HS_CDS_GAIN,
	HS_VGA_GAIN,
	HS_CONTROL_SIZE
};

#endif // !__RTS2_REFLEX_H__
