Merge lp:~rsandifo/gcc-linaro/lp803232-4.5 into lp:gcc-linaro/4.5

[Richard Sandiford]

[Linaro Toolchain Builder (cbuild)]

cbuild has taken a snapshot of this branch at r99522 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder armv5-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5
cbuild-ancestor: lp:gcc-linaro+bzr99521
cbuild-state: check

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on x86_64-natty-cbuild152-oort3-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/x86_64-natty-cbuild152-oort3-x86_64r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro+bzr99521.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/x86_64-natty-cbuild152-oort3-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild152-oort3-x86_64r1

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on i686-natty-cbuild152-oort4-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/i686-natty-cbuild152-oort4-i686r1

The test suite results were unchanged compared to the branch point lp:gcc-linaro+bzr99521.

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/i686-natty-cbuild152-oort4-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild152-oort4-i686r1

[Ramana Radhakrishnan (ramana)]

The patch looks ok but I'll wait for the ARM test results to come back.

Ramana

[Linaro Toolchain Builder (cbuild)]

cbuild successfully built this on armv7l-natty-cbuild157-ursa2-armv5r2.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/armv7l-natty-cbuild157-ursa2-armv5r2

The test suite results changed compared to the branch point lp:gcc-linaro+bzr99521:
 +PASS: gcc.target/arm/neon-modes-3.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/armv7l-natty-cbuild157-ursa2-armv5r2/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild157-ursa2-armv5r2

[Michael Hope (michaelh1)]

The A9 build got lost. I've kicked it now.

[Michael Hope (michaelh1)]

cbuild successfully built this on armv7l-natty-cbuild158-ursa3-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/armv7l-natty-cbuild158-ursa3-cortexa9r1

+PASS: gcc.target/arm/neon-modes-3.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99522~rsandifo~lp803232-4.5/logs/armv7l-natty-cbuild158-ursa3-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild158-ursa3-cortexa9r1

=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro	2011-07-08 12:54:44 +0000
+++ ChangeLog.linaro	2011-07-11 10:55:29 +0000
@@ -1,3 +1,17 @@
[phone]  Richard Sandiford  <[e-mail]>
+
+	Backport from mainline:
+	gcc/
+	2011-07-07  Richard Sandiford  <[e-mail]>
+
+	* reload1.c (choose_reload_regs): Use mode sizes to check whether
+	an old reload register completely defines the required value.
+
+	gcc/testsuite/
+	2011-07-07  Richard Sandiford  <[e-mail]>
+
+	* gcc.target/arm/neon-modes-3.c: New test.
+
 2011-07-08  Richard Sandiford  <[e-mail]>
 
 	gcc/

=== modified file 'gcc/reload1.c'
--- gcc/reload1.c	2011-07-01 09:27:50 +0000
+++ gcc/reload1.c	2011-07-11 10:55:29 +0000
@@ -6449,6 +6449,8 @@
 
 	      if (regno >= 0
 		  && reg_last_reload_reg[regno] != 0
+		  && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
+		      >= GET_MODE_SIZE (mode) + byte)
 #ifdef CANNOT_CHANGE_MODE_CLASS
 		  /* Verify that the register it's in can be used in
 		     mode MODE.  */
@@ -6460,24 +6462,12 @@
 		{
 		  enum reg_class rclass = rld[r].rclass, last_class;
 		  rtx last_reg = reg_last_reload_reg[regno];
-		  enum machine_mode need_mode;
 
 		  i = REGNO (last_reg);
 		  i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
 		  last_class = REGNO_REG_CLASS (i);
 
-		  if (byte == 0)
-		    need_mode = mode;
-		  else
-		    need_mode
-		      = smallest_mode_for_size
-		        (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
-			 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
-			 ? MODE_INT : GET_MODE_CLASS (mode));
-
-		  if ((GET_MODE_SIZE (GET_MODE (last_reg))
-		       >= GET_MODE_SIZE (need_mode))
-		      && reg_reloaded_contents[i] == regno
+		  if (reg_reloaded_contents[i] == regno
 		      && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
 		      && HARD_REGNO_MODE_OK (i, rld[r].mode)
 		      && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)

=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-3.c'
--- gcc/testsuite/gcc.target/arm/neon-modes-3.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.target/arm/neon-modes-3.c	2011-07-11 10:55:29 +0000
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n)
+{
+  float32x4x4_t a5, a6, a7, a8, a9;
+  int i;
+
+  a5 = *src;
+  a6 = *src;
+  a7 = *src;
+  a8 = *src;
+  a9 = *src;
+  while (n--)
+    {
+      for (i = 0; i < 8; i++)
+	{
+	  float32x4x4_t a0, a1, a2, a3, a4;
+
+	  a0 = *src;
+	  a1 = *src;
+	  a2 = *src;
+	  a3 = *src;
+	  a4 = *src;
+	  *src = a0;
+	  *dest = a0.val[0];
+	  *dest = a0.val[3];
+	  *src = a1;
+	  *dest = a1.val[0];
+	  *dest = a1.val[3];
+	  *src = a2;
+	  *dest = a2.val[0];
+	  *dest = a2.val[3];
+	  *src = a3;
+	  *dest = a3.val[0];
+	  *dest = a3.val[3];
+	  *src = a4;
+	  *dest = a4.val[0];
+	  *dest = a4.val[3];
+	}
+      *src = a5;
+      *dest = a5.val[0];
+      *dest = a5.val[3];
+      *src = a6;
+      *dest = a6.val[0];
+      *dest = a6.val[3];
+      *src = a7;
+      *dest = a7.val[0];
+      *dest = a7.val[3];
+      *src = a8;
+      *dest = a8.val[0];
+      *dest = a8.val[3];
+      *src = a9;
+      *dest = a9.val[0];
+      *dest = a9.val[3];
+    }
+}