Merge lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243 into lp:ubuntu/maverick/x-loader

Proposed by Ricardo Salveti on 2010-09-01
Status: Merged
Merge reported by: Andrew Starr-Bochicchio
Merged at revision: not available
Proposed branch: lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243
Merge into: lp:ubuntu/maverick/x-loader
Diff against target: 264 lines (+244/-0)
3 files modified
debian/changelog (+7/-0)
debian/patches/series (+1/-0)
debian/patches/support_micron_and_numonyx_memory.patch (+236/-0)
To merge this branch: bzr merge lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243
Reviewer Review Type Date Requested Status
Ubuntu Sponsors Team 2010-09-01 Pending
Review via email: mp+34325@code.launchpad.net

Description of the change

Just adding support_micron_and_numonyx_memory.patch to make x-loader work with Micron and Numonyx based Beagle xMs.

Patch is already x-loader upstream.

To post a comment you must log in.
Stefano Rivera (stefanor) wrote :

Looks good to me, but it's a main package, and thus beyond my sponsoring powers.

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1=== modified file 'debian/changelog'
2--- debian/changelog 2010-07-13 13:11:12 +0000
3+++ debian/changelog 2010-09-01 18:11:45 +0000
4@@ -1,3 +1,10 @@
5+x-loader (1.4.4git20100713-1ubuntu1) maverick; urgency=low
6+
7+ * adding support_micron_and_numonyx_memory.patch to make x-loader
8+ work with Micron and Numonyx based Beagle xMs (LP: #628243)
9+
10+ -- Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Wed, 01 Sep 2010 14:30:46 -0300
11+
12 x-loader (1.4.4git20100713-1) maverick; urgency=low
13
14 * new upstream release
15
16=== modified file 'debian/patches/series'
17--- debian/patches/series 2010-07-13 13:11:12 +0000
18+++ debian/patches/series 2010-09-01 18:11:45 +0000
19@@ -1,3 +1,4 @@
20 no_cross_compile.diff
21 no_stack_protector.diff
22 add_signGP.diff
23+support_micron_and_numonyx_memory.patch
24
25=== added file 'debian/patches/support_micron_and_numonyx_memory.patch'
26--- debian/patches/support_micron_and_numonyx_memory.patch 1970-01-01 00:00:00 +0000
27+++ debian/patches/support_micron_and_numonyx_memory.patch 2010-09-01 18:11:45 +0000
28@@ -0,0 +1,236 @@
29+From ead751e4a361ce19552ac94bbeba232f12849244 Mon Sep 17 00:00:00 2001
30+From: Steve Kipisz <s-kipisz2@ti.com>
31+Date: Thu, 8 Jul 2010 10:30:58 -0500
32+Subject: [PATCH] Support Micron or Numonyx memory
33+
34+---
35+ board/omap3530beagle/omap3530beagle.c | 56 +++++++++++++++++++++++++++-----
36+ drivers/k9f1g08r0a.c | 43 +++++++++++++++++++------
37+ include/asm/arch-omap3/mem.h | 43 ++++++++++++++++++++++++-
38+ 3 files changed, 121 insertions(+), 21 deletions(-)
39+
40+diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
41+index eb8008e..1254aa0 100644
42+--- a/board/omap3530beagle/omap3530beagle.c
43++++ b/board/omap3530beagle/omap3530beagle.c
44+@@ -265,6 +265,32 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
45+ }
46+
47+ #ifdef CFG_3430SDRAM_DDR
48++
49++#define MICRON_DDR 0
50++#define NUMONYX_MCP 1
51++int identify_xm_ddr()
52++{
53++ int mfr, id;
54++
55++ __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
56++ __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
57++ __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
58++ __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
59++ __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
60++ __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
61++
62++ /* Enable the GPMC Mapping */
63++ __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
64++ ((NAND_BASE_ADR>>24) & 0x3F) |
65++ (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
66++ delay(2000);
67++
68++ nand_readid(&mfr, &id);
69++ if (mfr == 0)
70++ return MICRON_DDR;
71++ if ((mfr == 0x20) && (id == 0xba))
72++ return NUMONYX_MCP;
73++}
74+ /*********************************************************************
75+ * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
76+ *********************************************************************/
77+@@ -279,15 +305,27 @@ void config_3430sdram_ddr(void)
78+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
79+
80+ if (beagle_revision() == REVISION_XM) {
81+- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
82+- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_0);
83+- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_1);
84+- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
85+- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
86+- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
87+- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
88+- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
89+- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
90++ if (identify_xm_ddr() == MICRON_DDR) {
91++ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
92++ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
93++ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
94++ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
95++ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
96++ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
97++ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
98++ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
99++ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
100++ } else {
101++ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
102++ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
103++ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
104++ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
105++ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
106++ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
107++ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
108++ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
109++ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
110++ }
111+ } else {
112+ __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
113+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
114+diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
115+index 8968a1b..d2da804 100644
116+--- a/drivers/k9f1g08r0a.c
117++++ b/drivers/k9f1g08r0a.c
118+@@ -154,6 +154,29 @@ static int NanD_Address(unsigned int numbytes, unsigned long ofs)
119+ return 0;
120+ }
121+
122++int nand_readid(int *mfr, int *id)
123++{
124++ NAND_ENABLE_CE();
125++
126++ if (NanD_Command(NAND_CMD_RESET)) {
127++ NAND_DISABLE_CE();
128++ return 1;
129++ }
130++
131++ if (NanD_Command(NAND_CMD_READID)) {
132++ NAND_DISABLE_CE();
133++ return 1;
134++ }
135++
136++ NanD_Address(ADDR_COLUMN, 0);
137++
138++ *mfr = READ_NAND(NAND_ADDR);
139++ *id = READ_NAND(NAND_ADDR);
140++
141++ NAND_DISABLE_CE();
142++ return 0;
143++}
144++
145+ /* read chip mfr and id
146+ * return 0 if they match board config
147+ * return 1 if not
148+@@ -162,23 +185,23 @@ int nand_chip()
149+ {
150+ int mfr, id;
151+
152+- NAND_ENABLE_CE();
153++ NAND_ENABLE_CE();
154+
155+- if (NanD_Command(NAND_CMD_RESET)) {
156+- printf("Err: RESET\n");
157+- NAND_DISABLE_CE();
158++ if (NanD_Command(NAND_CMD_RESET)) {
159++ printf("Err: RESET\n");
160++ NAND_DISABLE_CE();
161+ return 1;
162+ }
163+
164+- if (NanD_Command(NAND_CMD_READID)) {
165+- printf("Err: READID\n");
166+- NAND_DISABLE_CE();
167++ if (NanD_Command(NAND_CMD_READID)) {
168++ printf("Err: READID\n");
169++ NAND_DISABLE_CE();
170+ return 1;
171+- }
172++ }
173+
174+- NanD_Address(ADDR_COLUMN, 0);
175++ NanD_Address(ADDR_COLUMN, 0);
176+
177+- mfr = READ_NAND(NAND_ADDR);
178++ mfr = READ_NAND(NAND_ADDR);
179+ id = READ_NAND(NAND_ADDR);
180+
181+ NAND_DISABLE_CE();
182+diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
183+index cba4c6f..63cdba1 100644
184+--- a/include/asm/arch-omap3/mem.h
185++++ b/include/asm/arch-omap3/mem.h
186+@@ -46,6 +46,7 @@ typedef enum {
187+ #define MMC_NAND 4
188+ #define MMC_ONENAND 5
189+ #define GPMC_NONE 6
190++#define GPMC_ONENAND_TRY 7
191+
192+ #endif
193+
194+@@ -71,7 +72,8 @@ typedef enum {
195+ #define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */
196+ #else
197+ #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL)
198+-#define SDP_SDRC_MDCFG_0_DDR_XM (0x03588019|B_ALL)
199++#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
200++#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL)
201+ #endif
202+
203+ #define SDP_SDRC_MR_0_DDR 0x00000032
204+@@ -252,12 +254,47 @@ typedef enum {
205+ (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
206+
207+ #define MICRON_TWTR_200 2
208+-#define MICRON_TCKE_200 1
209++#define MICRON_TCKE_200 4
210+ #define MICRON_TXP_200 2
211+ #define MICRON_XSR_200 23
212+ #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
213+ (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
214+
215++/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
216++ * ACTIMA
217++ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
218++ * TDPL (Twr) = 15/6 = 2.5 -> 3
219++ * TRRD = 12/6 = 2
220++ * TRCD = 22.5/6 = 3.75 -> 4
221++ * TRP = 18/6 = 3
222++ * TRAS = 42/6 = 7
223++ * TRC = 60/6 = 10
224++ * TRFC = 140/6 = 23.3 -> 24
225++ * ACTIMB
226++ * TWTR = 2
227++ * TCKE = 2
228++ * TXSR = 200/6 = 33.3 -> 34
229++ * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿?
230++ */
231++#define NUMONYX_TDAL_165 6
232++#define NUMONYX_TDPL_165 3
233++#define NUMONYX_TRRD_165 2
234++#define NUMONYX_TRCD_165 4
235++#define NUMONYX_TRP_165 3
236++#define NUMONYX_TRAS_165 7
237++#define NUMONYX_TRC_165 10
238++#define NUMONYX_TRFC_165 24
239++#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
240++ | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
241++ (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
242++
243++#define NUMONYX_TWTR_165 2
244++#define NUMONYX_TCKE_165 2
245++#define NUMONYX_TXP_165 3
246++#define NUMONYX_XSR_165 34
247++#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
248++ (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
249++
250+ /* New and compatability speed defines */
251+ #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
252+ # define L3_100MHZ /* Use with <= 100MHz SDRAM */
253+@@ -276,6 +313,8 @@ typedef enum {
254+ #elif defined(L3_165MHZ)
255+ # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165
256+ # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165
257++# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165
258++# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165
259+ #endif
260+
261+
262+--
263+1.7.1
264+

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