Ubuntu
x-loader-omap4 package

Merge lp:~rsalveti/ubuntu/maverick/x-loader-omap4/fix-624652 into lp:ubuntu/maverick/x-loader-omap4

  1. Maverick (10.10)
  2. fix-624652
  3. Merge into maverick
Proposed by Ricardo Salveti
Status: Needs review
Proposed branch: lp:~rsalveti/ubuntu/maverick/x-loader-omap4/fix-624652
Merge into: lp:ubuntu/maverick/x-loader-omap4
Diff against target: 2509 lines (+1289/-511)
13 files modified
Makefile (+15/-4)
board/omap4430panda/clock.c (+78/-30)
board/omap4430panda/omap4430panda.c (+124/-177)
board/omap4430sdp/clock.c (+62/-25)
board/omap4430sdp/omap4430sdp.c (+204/-267)
cpu/omap4/cpu.c (+24/-0)
debian/changelog (+11/-0)
debian/patches/02-panda-fix-ddr-timings.patch (+299/-0)
debian/patches/03-panda-x-loader-emif-1gb-support.patch (+247/-0)
debian/patches/series (+2/-0)
include/asm/arch-omap4/cpu.h (+13/-0)
include/configs/omap4430panda.h (+2/-7)
scripts/signGP.c (+208/-1)
To merge this branch: bzr merge lp:~rsalveti/ubuntu/maverick/x-loader-omap4/fix-624652
Reviewer Review Type Date Requested Status
Oliver Grawert Pending
Review via email: mp+34597@code.launchpad.net

Commit message

* new upstream release
 - adds Omap 4 ES2 6 layer and 8 layer support (LP: #624652)
 - uses branch omap4_panda_L24.9 from http://gitorious.org/pandaboard/x-loader
 - es2 compatible only
* adding 02-panda-fix-ddr-timings.patch and 03-panda-x-loader-emif-1gb-support.patch
  to have 1gb support

Description of the change

Updated from latest upstream release. Also add 2 patches from robclark's tree to have 1gb support at Panda.

Tested and confirm that it works fine with ES2 6 and 8 layer boards.

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Unmerged revisions

5. By Ricardo Salveti

* new upstream release
 - adds Omap 4 ES2 6 layer and 8 layer support (LP: #624652)
 - uses branch omap4_panda_L24.9 from http://gitorious.org/pandaboard/x-loader
 - es2 compatible only
* adding 02-panda-fix-ddr-timings.patch and 03-panda-x-loader-emif-1gb-support.patch
  to have 1gb support

Preview Diff

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1=== modified file 'Makefile'
2--- Makefile 2010-06-24 15:15:33 +0000
3+++ Makefile 2010-09-04 03:39:41 +0000
4@@ -53,7 +53,7 @@
5 include $(TOPDIR)/config.mk
6
7 ifndef CROSS_COMPILE
8-CROSS_COMPILE = arm-none-linux-gnueabi-
9+CROSS_COMPILE = arm-angstrom-linux-gnueabi-
10 #CROSS_COMPILE = arm-linux-
11 export CROSS_COMPILE
12 endif
13@@ -153,22 +153,33 @@
14 omap3430sdp_config : unconfig
15 @./mkconfig $(@:_config=) arm omap3 omap3430sdp
16
17-omap4430sdp_MPU_1G_config \
18+omap4430sdp_600_config \
19 omap4430sdp_config : unconfig
20 @./mkconfig $(@:_config=) arm omap4 omap4430sdp
21 echo "/* Generarated file. Do not edit */" >./include/config.h
22 echo "#include <configs/omap4430sdp.h>" >>./include/config.h
23- @[ -z "$(findstring _MPU_1G,$@)" ] || \
24+ @[ -n "$(findstring _MPU_600MHz,$@)" ] || \
25 { echo "#define CONFIG_MPU_1000 1" >>./include/config.h ; \
26 echo "MPU at 1GHz revision.." ; \
27 }
28- @[ -n "$(findstring _MPU_1G,$@)" ] || \
29+ @[ -z "$(findstring _MPU_600MHz,$@)" ] || \
30 { echo "#define CONFIG_MPU_600 1" >>./include/config.h ; \
31 echo "MPU at 600MHz revision.." ; \
32 }
33
34+omap4430panda_600MHZ_config \
35 omap4430panda_config : unconfig
36 @./mkconfig $(@:_config=) arm omap4 omap4430panda
37+ echo "/* Generarated file. Do not edit */" >./include/config.h
38+ echo "#include <configs/omap4430panda.h>" >>./include/config.h
39+ @[ -n "$(findstring _600MHZ,$@)" ] || \
40+ { echo "#define CONFIG_MPU_1000 1" >>./include/config.h ; \
41+ echo "MPU at 1GHz revision.." ; \
42+ }
43+ @[ -z "$(findstring _600MHZ,$@)" ] || \
44+ { echo "#define CONFIG_MPU_600 1" >>./include/config.h ; \
45+ echo "MPU at 600MHz revision.." ; \
46+ }
47
48 omap3430labrador_config : unconfig
49 @./mkconfig $(@:_config=) arm omap3 omap3430labrador
50
51=== modified file 'board/omap4430panda/clock.c'
52--- board/omap4430panda/clock.c 2010-06-24 15:15:33 +0000
53+++ board/omap4430panda/clock.c 2010-09-04 03:39:41 +0000
54@@ -70,6 +70,8 @@
55 #ifdef CONFIG_MPU_600
56 /* RUN MPU @ 600 MHz */
57 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
58+#elif CONFIG_MPU_1000
59+ {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
60 #else
61 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
62 #endif
63@@ -111,6 +113,24 @@
64 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
65 /* 27M values */
66 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
67+ /* 38.4M values - DDR@200MHz*/
68+ {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
69+};
70+
71+/* CORE parameters for L3 at 190 MHz - For ES1 only*/
72+struct dpll_param core_dpll_param_l3_190[7] = {
73+ /* 12M values */
74+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
75+ /* 13M values */
76+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
77+ /* 16.8M values */
78+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
79+ /* 19.2M values */
80+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
81+ /* 26M values */
82+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
83+ /* 27M values */
84+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
85 /* 38.4M values */
86 #ifdef CONFIG_OMAP4_SDC
87 #ifdef CORE_190MHZ
88@@ -123,6 +143,7 @@
89 #endif
90 };
91
92+
93 /* PER parameters */
94 struct dpll_param per_dpll_param[7] = {
95 /* 12M values */
96@@ -138,11 +159,11 @@
97 /* 27M values */
98 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
99 /* 38.4M values */
100-#ifdef CONFIG_OMAP4_SDC
101+#if 0
102+ /* SDC settings */
103 {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
104-#else
105- {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
106 #endif
107+ {0x14, 0x00, 0x08, 0x04, 0x0c, 0x02, 0x04, 0x05},
108 };
109
110 /* ABE parameters */
111@@ -265,17 +286,22 @@
112 sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
113 sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
114 sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
115- sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
116 sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
117- sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
118 sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
119- sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
120 sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
121- sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
122 sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
123- sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
124 sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
125- sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
126+
127+// if(omap_revision() == OMAP4430_ES1_0)
128+// {
129+ /* Do this only on ES1.0 */
130+ sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
131+ sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
132+ sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
133+ sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
134+ sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
135+ sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
136+// }
137
138 /* Lock the per dpll */
139 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
140@@ -376,26 +402,35 @@
141 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
142 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
143
144- /* Program USB DPLL */
145- dpll_param_p = &core_dpll_param[clk_index];
146-
147+ /* Program Core DPLL */
148+ if(omap_revision() == OMAP4430_ES1_0)
149+ dpll_param_p = &core_dpll_param_l3_190[clk_index];
150+ else
151+ dpll_param_p = &core_dpll_param[clk_index];
152+
153 /* Disable autoidle */
154 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
155
156 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
157 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
158 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
159- sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
160 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
161- sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
162 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
163- sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
164 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
165- sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
166 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
167- sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
168 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
169- sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
170+
171+ if(omap_revision() == OMAP4430_ES1_0)
172+ {
173+ /* Do this only on ES1.0 */
174+ sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
175+ sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
176+ sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
177+ sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
178+ sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
179+ sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
180+ }
181+
182
183 /* Lock the core dpll */
184 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
185@@ -424,8 +459,11 @@
186 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
187 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
188
189- /* Program USB DPLL */
190- dpll_param_p = &core_dpll_param[clk_index];
191+ /* Program Core DPLL */
192+ if(omap_revision() == OMAP4430_ES1_0)
193+ dpll_param_p = &core_dpll_param_l3_190[clk_index];
194+ else
195+ dpll_param_p = &core_dpll_param[clk_index];
196
197 /* Disable autoidle */
198 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
199@@ -433,17 +471,22 @@
200 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
201 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
202 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
203- sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
204 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
205- sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
206 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
207- sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
208 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
209- sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
210 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
211- sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
212 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
213- sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
214+
215+// if(omap_revision() == OMAP4430_ES1_0)
216+// {
217+ /* Do this only on ES1.0 */
218+ sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
219+ sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
220+ sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
221+ sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
222+ sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
223+ sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
224+// }
225
226 return;
227 }
228@@ -459,13 +502,15 @@
229
230 void lock_core_dpll_shadow(void)
231 {
232+ dpll_param *dpll_param_p;
233 /* Lock the core dpll using freq update method */
234 *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE)
235
236+ dpll_param_p = &core_dpll_param[6];
237 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
238 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
239 */
240- *(volatile int*)0x4A004260 = 0xF0D;
241+ *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
242
243 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
244 while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
245@@ -600,9 +645,11 @@
246 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
247
248 /* MMC clocks */
249- sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 32, 0x1000002);
250+ sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
251+ sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
252 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY);
253- sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 32, 0x1000002);
254+ sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
255+ sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
256 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY);
257 sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
258 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
259@@ -691,7 +738,8 @@
260 //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
261 sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
262 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
263- sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x1);
264+ /* enable the 32K, 48M optional clocks and enable the module */
265+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
266 //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
267 return;
268 }
269
270=== modified file 'board/omap4430panda/omap4430panda.c'
271--- board/omap4430panda/omap4430panda.c 2010-06-24 15:15:33 +0000
272+++ board/omap4430panda/omap4430panda.c 2010-09-04 03:39:41 +0000
273@@ -35,8 +35,6 @@
274 #include <linux/mtd/nand_legacy.h>
275 #endif
276
277-#define CONFIG_OMAP4_SDC 1
278-
279 /* EMIF and DMM registers */
280 #define EMIF1_BASE 0x4c000000
281 #define EMIF2_BASE 0x4d000000
282@@ -63,6 +61,7 @@
283 #define EMIF_L3_CONFIG 0x0054
284 #define EMIF_L3_CFG_VAL_1 0x0058
285 #define EMIF_L3_CFG_VAL_2 0x005C
286+#define IODFT_TLGC 0x0060
287 #define EMIF_PERF_CNT_1 0x0080
288 #define EMIF_PERF_CNT_2 0x0084
289 #define EMIF_PERF_CNT_CFG 0x0088
290@@ -130,137 +129,25 @@
291 * should be programmed for new OPP.
292 */
293 /* Elpida 2x2Gbit */
294-#ifdef CONFIG_OMAP4_SDC
295-#ifndef CORE_190MHZ
296- /*
297- * EMIF_SDRAM_REF_CTRL
298- * refresh rate = DDR_CLK / reg_refresh_rate
299- * 1/3.9 uS = (333MHz) / reg_refresh_rate
300- */
301-#define SDRAM_REF_CTRL 0x0000004A
302-#define SDRAM_REF_CTRL_OPP100 0x0000050E
303-/*
304- * 28:25 REG_T_RP Minimum number of m_clk cycles from
305- * Precharge to Activate or Refresh, minus one.
306- * 24:21 REG_T_RCD Minimum number of m_clk cycles from
307- * Activate to Read or Write, minus one.
308- * 20:17 REG_T_WR Minimum number of m_clk cycles from last
309- * Write transfer to Pre-charge, minus one.
310- * 16:12 REG_T_RAS Minimum number of m_clk cycles from Activate
311- * to Pre-charge, minus one. reg_t_ras value need
312- * to be bigger than or equal to reg_t_rcd value.
313- * 11:6 REG_T_RC Minimum number of m_clk cycles from
314- * Activate to Activate, minus one.
315- * 5:3 REG_T_RRD Minimum number of m_clk cycles from
316- * Activate to Activate for a different bank, minus one.
317- * For an 8-bank, this field must be equal to
318- * ((tFAW/(4*tCK))-1).
319- * 2:0 REG_T_WTR Minimum number of m_clk cycles from last Write
320- */
321-#define SDRAM_TIM_1 0x04442049
322-#define SDRAM_TIM_1_OPP100 0x0CA8D51A
323-
324-/*
325- * 30:28 REG_T_XP Minimum number of m_clk cycles from
326- * Powerdown exit to any command other than a
327- * Read command, minus one.
328- * 24:16 REG_T_XSNR Minimum number of m_clk cycles from Self-Refresh
329- * exit to any command other than a Read command,
330- * minusone. REG_T_XSNR and REG_T_XSRD must be
331- * programmed with the same value.
332- * 15:6 REG_T_XSRD Minimum number of m_clk cycles from Self-Refresh
333- * exit to a Read command,
334- * minus one. REG_T_XSNR and REG_T_XSRD must be
335- * programmed with the same value.
336- * 5:3 REG_T_RTP Minimum number of m_clk cycles for the last
337- * read command to a Pre-charge command, minus one.
338- */
339-#define SDRAM_TIM_2 0x1002008A
340-#define SDRAM_TIM_2_OPP100 0x202E0B92
341-
342-/*
343- * 23:21 REG_T_CKESR Minimum number of m_clk cycles for which LPDDR2
344- * must remain in Self Refresh, minus one.
345- * 20:15 REG_ZQ_ZQCS Number of m_clk clock cycles for a ZQCS command
346- * minus one.
347- * 14:13 REG_T_TDQSCKMAX Number of m_clk that satisfies tDQSCKmax for
348- * LPDDR2,minus one.
349- * 12:4 REG_T_RFC Minimum number of m_clk cycles from Refresh or
350- * Load
351- * Mode to Refresh or Activate, minus one.
352- * 3:0 REG_T_RAS_MAX Maximum number of reg_refresh_rate intervals
353- * from Activate to Precharge command. This field
354- * must be equal to ((tRASmax / tREFI)-1)
355- * rounded down to the next lower integer.
356- * Value for REG_T_RAS_MAX can be calculated as
357- * follows:
358- * If tRASmax = 120 us and tREFI = 15.7 us, then
359- * REG_T_RAS_MAX = ((120/15.7)-1) = 6.64.
360- * Round down to the next lower integer.
361- * Therefore, the programmed value must be 6
362- */
363-#define SDRAM_TIM_3 0x0040802F
364-#define SDRAM_TIM_3_OPP100 0x008EA2BF
365-#define SDRAM_CONFIG_INIT 0x80800EB1
366-#define SDRAM_CONFIG_FINAL 0x80801AB1
367-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
368-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
369-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
370-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
371-#define DDR_PHY_CTRL_2 0x00000000
372-#define READ_IDLE_CTRL 0x000501FF
373-#define READ_IDLE_CTRL_OPP100 0x000501FF
374-#define PWR_MGMT_CTRL 0x40000000
375-#define PWR_MGMT_CTRL_OPP100 0x80000000
376-
377-#else /* DDR @ 380.928 MHz */
378-
379-#define SDRAM_REF_CTRL 0x0000004A
380-#define SDRAM_REF_CTRL_OPP100 0x000005CD
381-#define SDRAM_TIM_1 0x04442049
382-#define SDRAM_TIM_1_OPP100 0x10EB065A
383-#define SDRAM_TIM_2 0x1002008A
384-#define SDRAM_TIM_2_OPP100 0x20370DD2
385-#define SDRAM_TIM_3 0x0040802F
386-#define SDRAM_TIM_3_OPP100 0x008EA2BF
387-#define SDRAM_CONFIG_INIT 0x80800EB1
388-#define SDRAM_CONFIG_FINAL 0x80801AB1
389-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
390-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
391-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
392-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
393-#define DDR_PHY_CTRL_2 0x00000000
394-#define READ_IDLE_CTRL 0x000501FF
395-#define READ_IDLE_CTRL_OPP100 0x000501FF
396-#define PWR_MGMT_CTRL 0x40000000
397-#define PWR_MGMT_CTRL_OPP100 0x80000000
398-#endif
399-
400-#else /* ES1.0 */
401-/* TODO: ES1.0 OPP100 valuse are still not popullated
402- * 600 MHz/200 MHz
403- */
404-#define SDRAM_REF_CTRL 0x0000004A
405-#define SDRAM_REF_CTRL_OPP100 0x0000050E
406-#define SDRAM_TIM_1 0x04442049
407-#define SDRAM_TIM_1_OPP100 0x0CA8D51A
408-#define SDRAM_TIM_2 0x1002008A
409-#define SDRAM_TIM_2_OPP100 0x202E0B92
410-#define SDRAM_TIM_3 0x0040802F
411-#define SDRAM_TIM_3_OPP100 0x008EA2BF
412-#define SDRAM_CONFIG_INIT 0x80800EB1
413-#define SDRAM_CONFIG_FINAL 0x80801AB1
414-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
415-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
416-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
417-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
418-#define DDR_PHY_CTRL_2 0x00000000
419-#define READ_IDLE_CTRL 0x000501FF
420-#define READ_IDLE_CTRL_OPP100 0x000501FF
421-#define PWR_MGMT_CTRL 0x80000000
422-#define PWR_MGMT_CTRL_OPP100 0x00000000
423-
424-#endif
425+#define SDRAM_REF_CTRL 0x0000004A
426+#define SDRAM_REF_CTRL_OPP100 0x0000030c
427+#define SDRAM_TIM_1 0x04442049
428+#define SDRAM_TIM_1_OPP100 0x10eb066A
429+#define SDRAM_TIM_2 0x1002008A
430+#define SDRAM_TIM_2_OPP100 0x20370dd2
431+#define SDRAM_TIM_3 0x0040802F
432+#define SDRAM_TIM_3_OPP100 0x00b1c33f
433+#define SDRAM_CONFIG_INIT 0x80800EB1
434+#define SDRAM_CONFIG_FINAL 0x98801ab1
435+#define DDR_PHY_CTRL_1_INIT 0x849FFFF5
436+#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
437+#define DDR_PHY_CTRL_1_OPP100 0x849FF408
438+#define DDR_PHY_CTRL_2 0x00000000
439+#define READ_IDLE_CTRL 0x00050139
440+#define READ_IDLE_CTRL_OPP100 0x00050139
441+#define PWR_MGMT_CTRL 0x4000000f
442+#define PWR_MGMT_CTRL_OPP100 0x4000000f
443+#define ZQ_CONFIG 0x50073214
444
445
446 /*******************************************************
447@@ -273,6 +160,14 @@
448 "bne 1b" : "=r" (loops) : "0"(loops));
449 }
450
451+
452+void big_delay(unsigned int count)
453+{
454+ int i;
455+ for (i=0; i<count; i++)
456+ delay(1);
457+}
458+
459 /* TODO: FREQ update method is not working so shadow registers programming
460 * is just for same of completeness. This would be safer if auto
461 * trasnitions are working
462@@ -296,7 +191,7 @@
463 /* PHY control values */
464 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT;
465 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= \
466- DDR_PHY_CTRL_1_OPP100_INIT;
467+ DDR_PHY_CTRL_1_OPP100;
468 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
469
470 /*
471@@ -323,6 +218,7 @@
472 *(volatile int*)(base + EMIF_SDRAM_TIM_3) = SDRAM_TIM_3;
473 *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = SDRAM_TIM_3_OPP100;
474
475+ *(volatile int*)(base + EMIF_ZQ_CONFIG) = ZQ_CONFIG;
476 /*
477 * EMIF_PWR_MGMT_CTRL
478 */
479@@ -334,12 +230,14 @@
480 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
481 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
482 */
483-
484+ big_delay(1000);
485+#if 0
486 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR;
487 do
488 {
489 reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
490 } while((reg_value & 0x1) != 0);
491+#endif
492
493 /* set MR10 register */
494 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR;
495@@ -358,8 +256,6 @@
496 /* Set SDRAM CONFIG register again here with final RL-WL value */
497 *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_FINAL;
498 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_FINAL;
499- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= \
500- DDR_PHY_CTRL_1_OPP100_FINAL;
501
502 /*
503 * EMIF_SDRAM_REF_CTRL
504@@ -389,7 +285,7 @@
505
506 /* PHY control values */
507 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) \
508- = DDR_PHY_CTRL_1_OPP100_FINAL;
509+ = DDR_PHY_CTRL_1_OPP100;
510 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
511
512 /*
513@@ -435,19 +331,46 @@
514 *****************************************/
515 static void ddr_init(void)
516 {
517- unsigned int base_addr;
518+ unsigned int base_addr, rev;
519+ rev = omap_revision();
520
521- /* Configurte the Control Module DDRIO device */
522- __raw_writel(0x1c1c1c1c, 0x4A100638);
523- __raw_writel(0x1c1c1c1c, 0x4A10063c);
524- __raw_writel(0x1c1c1c1c, 0x4A100640);
525- __raw_writel(0x1c1c1c1c, 0x4A100648);
526- __raw_writel(0x1c1c1c1c, 0x4A10064c);
527- __raw_writel(0x1c1c1c1c, 0x4A100650);
528+ if(rev == OMAP4430_ES2_0)
529+ {
530+ __raw_writel(0x9e9e9e9e, 0x4A100638);
531+ __raw_writel(0x9e9e9e9e, 0x4A10063c);
532+ __raw_writel(0x9e9e9e9e, 0x4A100640);
533+ __raw_writel(0x9e9e9e9e, 0x4A100648);
534+ __raw_writel(0x9e9e9e9e, 0x4A10064c);
535+ __raw_writel(0x9e9e9e9e, 0x4A100650);
536+ }
537+ else if(rev == OMAP4430_ES1_0)
538+ {
539+ /* Configurte the Control Module DDRIO device */
540+ __raw_writel(0x1c1c1c1c, 0x4A100638);
541+ __raw_writel(0x1c1c1c1c, 0x4A10063c);
542+ __raw_writel(0x1c1c1c1c, 0x4A100640);
543+ __raw_writel(0x1c1c1c1c, 0x4A100648);
544+ __raw_writel(0x1c1c1c1c, 0x4A10064c);
545+ __raw_writel(0x1c1c1c1c, 0x4A100650);
546+ }
547
548 /* LPDDR2IO set to NMOS PTV */
549 __raw_writel(0x00ffc000, 0x4A100704);
550
551+
552+ /*
553+ * DMM Configuration
554+ */
555+
556+ /* Both EMIFs 128 byte interleaved*/
557+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
558+
559+ /* EMIF2 only at 0x90000000 */
560+ //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
561+
562+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
563+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
564+
565 /* DDR needs to be initialised @ 19.2 MHz
566 * So put core DPLL in bypass mode
567 * Configure the Core DPLL but don't lock it
568@@ -510,7 +433,6 @@
569 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
570
571 /* Put the Core Subsystem PD to ON State */
572- sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x30E03);
573
574 /* No IDLE: BUG in SDC */
575 //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
576@@ -542,16 +464,12 @@
577 * [9:8] SDRC_MAP 0x3
578 * [7:0] SDRC_ADDR 0X0
579 */
580- /* 256 MB configeration */
581- /*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80400200; */
582- /* 512MB configeration */
583- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
584- /* TODO: Settings can be locked but kept open for TILER */
585- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x00000000;
586- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
587- /* Invalid address TRAP */
588- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
589+ reset_phy(EMIF1_BASE);
590+ reset_phy(EMIF2_BASE);
591
592+ *((volatile int *)0x80000000) = 0;
593+ *((volatile int *)0x80000080) = 0;
594+ //*((volatile int *)0x90000000) = 0;
595 }
596 /*****************************************
597 * Routine: board_init
598@@ -612,9 +530,10 @@
599 }
600
601
602-#ifdef CONFIG_MPU_600
603+#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
604 static scale_vcores(void)
605 {
606+ unsigned int rev = omap_revision();
607 /* For VC bypass only VCOREx_CGF_FORCE is necessary and
608 * VCOREx_CFG_VOLTAGE changes can be discarded
609 */
610@@ -625,7 +544,10 @@
611
612 /* set VCORE1 force VSEL */
613 /* PRM_VC_VAL_BYPASS) */
614- *(volatile int*)(0x4A307BA0) = 0x395512;
615+ if(rev == OMAP4430_ES1_0)
616+ *(volatile int*)(0x4A307BA0) = 0x3B5512;
617+ else
618+ *(volatile int*)(0x4A307BA0) = 0x3A5512;
619 *(volatile int*)(0x4A307BA0) |= 0x1000000;
620 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
621
622@@ -635,7 +557,10 @@
623
624 /* FIXME: set VCORE2 force VSEL, Check the reset value */
625 /* PRM_VC_VAL_BYPASS) */
626- *(volatile int*)(0x4A307BA0) = 0x315B12;
627+ if(rev == OMAP4430_ES1_0)
628+ *(volatile int*)(0x4A307BA0) = 0x315B12;
629+ else
630+ *(volatile int*)(0x4A307BA0) = 0x295B12;
631 *(volatile int*)(0x4A307BA0) |= 0x1000000;
632 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
633
634@@ -644,7 +569,10 @@
635
636 /*/set VCORE3 force VSEL */
637 /* PRM_VC_VAL_BYPASS */
638- *(volatile int*)(0x4A307BA0) = 0x316112;
639+ if(rev == OMAP4430_ES1_0)
640+ *(volatile int*)(0x4A307BA0) = 0x316112;
641+ else
642+ *(volatile int*)(0x4A307BA0) = 0x296112;
643 *(volatile int*)(0x4A307BA0) |= 0x1000000;
644 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
645
646@@ -662,6 +590,8 @@
647
648 void s_init(void)
649 {
650+ unsigned int rev = omap_revision();
651+
652 set_muxconf_regs();
653 delay(100);
654
655@@ -674,11 +604,28 @@
656 ddr_init();
657
658 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
659-#ifdef CONFIG_MPU_600
660+#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
661 scale_vcores();
662 #endif
663 prcm_init();
664
665+ if(rev == OMAP4430_ES2_0) {
666+ if (__raw_readl(0x4805D138) & (1<<22)) {
667+ sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */
668+ sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */
669+ sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */
670+ sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
671+ sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
672+ }
673+ else {
674+ sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */
675+ sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */
676+ sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */
677+ sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
678+ sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
679+ }
680+ }
681+
682 }
683
684 /*******************************************************
685@@ -778,7 +725,7 @@
686 MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
687 MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \
688 MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \
689- MV(CP(GPMC_A22) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \
690+ MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \
691 MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
692 MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \
693 MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \
694@@ -794,9 +741,9 @@
695 MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \
696 MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \
697 MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \
698- MV(CP(GPMC_WAIT1) , ( IEN | M3)) /* gpio_62 */ \
699+ MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \
700 MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \
701- MV(CP(C2C_DATA12) , ( M1)) /* dsi1_te0 */ \
702+ MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \
703 MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \
704 MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \
705 MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \
706@@ -914,12 +861,12 @@
707 MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \
708 MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
709 MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
710- MV(CP(UNIPRO_TX0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \
711+ MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \
712 MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
713 MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
714 MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
715- MV(CP(UNIPRO_TX2) , ( OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \
716- MV(CP(UNIPRO_TY2) , ( OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \
717+ MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \
718+ MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \
719 MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
720 MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
721 MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
722@@ -930,7 +877,7 @@
723 MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
724 MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
725 MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
726- MV(CP(FREF_CLK2_OUT) , ( M0)) /* fref_clk2_out */ \
727+ MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
728 MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
729 MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
730 MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
731@@ -981,13 +928,10 @@
732 MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \
733 MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \
734 MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \
735-// MV1(WK(PAD0_JTAG_NTRST) , ( IEN | M0)) /* jtag_ntrst */ \
736- MV1(WK(PAD1_JTAG_TCK) , ( IEN | M0)) /* jtag_tck */ \
737- MV1(WK(PAD0_JTAG_RTCK) , ( M0)) /* jtag_rtck */ \
738- MV1(WK(PAD1_JTAG_TMS_TMSC) , ( IEN | M0)) /* jtag_tms_tmsc */ \
739- MV1(WK(PAD0_JTAG_TDI) , ( IEN | M0)) /* jtag_tdi */ \
740- MV1(WK(PAD1_JTAG_TDO) , ( M0)) /* jtag_tdo */
741-
742+ MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \
743+ MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \
744+ MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */
745+
746 #define MUX_DEFAULT_OMAP4_ALL() \
747 MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
748 MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
749@@ -1027,7 +971,7 @@
750 MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \
751 MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \
752 MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \
753- MV(CP(GPMC_WAIT1), (M3_SAFE)) /* gpio_62 */ \
754+ MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
755 MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \
756 MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \
757 MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \
758@@ -1214,7 +1158,6 @@
759 MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \
760 MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \
761 MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \
762- //MV1(WK(PAD0_JTAG_NTRST), (IEN | M0)) /* jtag_ntrst */ \
763 MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \
764 MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \
765 MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \
766@@ -1255,3 +1198,7 @@
767 {
768 return 1;
769 }
770+void reset_phy(unsigned int base)
771+{
772+ *(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
773+}
774
775=== modified file 'board/omap4430sdp/clock.c'
776--- board/omap4430sdp/clock.c 2010-06-24 15:15:33 +0000
777+++ board/omap4430sdp/clock.c 2010-09-04 03:39:41 +0000
778@@ -113,18 +113,33 @@
779 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
780 /* 27M values */
781 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
782+ /* 38.4M values - DDR@200MHz*/
783+ {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
784+};
785+
786+/* CORE parameters for L3 at 190 MHz - For ES1 only*/
787+struct dpll_param core_dpll_param_l3_190[7] = {
788+ /* 12M values */
789+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
790+ /* 13M values */
791+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
792+ /* 16.8M values */
793+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
794+ /* 19.2M values */
795+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
796+ /* 26M values */
797+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
798+ /* 27M values */
799+ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
800 /* 38.4M values */
801-#ifdef CONFIG_OMAP4_SDC
802 #ifdef CORE_190MHZ
803 {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
804 #else /* Default CORE @166MHz */
805 {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
806 #endif
807-#else
808- {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08},
809-#endif
810 };
811
812+
813 /* PER parameters */
814 struct dpll_param per_dpll_param[7] = {
815 /* 12M values */
816@@ -140,11 +155,11 @@
817 /* 27M values */
818 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
819 /* 38.4M values */
820-#ifdef CONFIG_OMAP4_SDC
821+#if 0
822+ /* SDC settings */
823 {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
824-#else
825+#endif
826 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
827-#endif
828 };
829
830 /* ABE parameters */
831@@ -378,26 +393,35 @@
832 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
833 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
834
835- /* Program USB DPLL */
836- dpll_param_p = &core_dpll_param[clk_index];
837-
838+ /* Program Core DPLL */
839+ if(omap_revision() == OMAP4430_ES1_0)
840+ dpll_param_p = &core_dpll_param_l3_190[clk_index];
841+ else
842+ dpll_param_p = &core_dpll_param[clk_index];
843+
844 /* Disable autoidle */
845 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
846
847 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
848 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
849 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
850- sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
851 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
852- sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
853 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
854- sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
855 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
856- sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
857 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
858- sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
859 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
860- sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
861+
862+ if(omap_revision() == OMAP4430_ES1_0)
863+ {
864+ /* Do this only on ES1.0 */
865+ sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
866+ sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
867+ sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
868+ sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
869+ sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
870+ sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
871+ }
872+
873
874 /* Lock the core dpll */
875 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
876@@ -426,8 +450,11 @@
877 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
878 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
879
880- /* Program USB DPLL */
881- dpll_param_p = &core_dpll_param[clk_index];
882+ /* Program Core DPLL */
883+ if(omap_revision() == OMAP4430_ES1_0)
884+ dpll_param_p = &core_dpll_param_l3_190[clk_index];
885+ else
886+ dpll_param_p = &core_dpll_param[clk_index];
887
888 /* Disable autoidle */
889 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
890@@ -435,17 +462,22 @@
891 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
892 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
893 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
894- sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
895 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
896- sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
897 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
898- sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
899 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
900- sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
901 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
902- sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
903 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
904- sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
905+
906+ if(omap_revision() == OMAP4430_ES1_0)
907+ {
908+ /* Do this only on ES1.0 */
909+ sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
910+ sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
911+ sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
912+ sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
913+ sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
914+ sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
915+ }
916
917 return;
918 }
919@@ -461,13 +493,18 @@
920
921 void lock_core_dpll_shadow(void)
922 {
923+ dpll_param *dpll_param_p;
924 /* Lock the core dpll using freq update method */
925 *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE)
926
927+ if(omap_revision() == OMAP4430_ES1_0)
928+ dpll_param_p = &core_dpll_param_l3_190[6];
929+ else
930+ dpll_param_p = &core_dpll_param[6];
931 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
932 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
933 */
934- *(volatile int*)0x4A004260 = 0xF0D;
935+ *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
936
937 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
938 while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
939
940=== modified file 'board/omap4430sdp/omap4430sdp.c'
941--- board/omap4430sdp/omap4430sdp.c 2010-06-24 15:15:33 +0000
942+++ board/omap4430sdp/omap4430sdp.c 2010-09-04 03:39:41 +0000
943@@ -63,6 +63,7 @@
944 #define EMIF_L3_CONFIG 0x0054
945 #define EMIF_L3_CFG_VAL_1 0x0058
946 #define EMIF_L3_CFG_VAL_2 0x005C
947+#define IODFT_TLGC 0x0060
948 #define EMIF_PERF_CNT_1 0x0080
949 #define EMIF_PERF_CNT_2 0x0084
950 #define EMIF_PERF_CNT_CFG 0x0088
951@@ -130,138 +131,83 @@
952 * should be programmed for new OPP.
953 */
954 /* Elpida 2x2Gbit */
955-#ifdef CONFIG_OMAP4_SDC
956-#ifndef CORE_190MHZ
957- /*
958- * EMIF_SDRAM_REF_CTRL
959- * refresh rate = DDR_CLK / reg_refresh_rate
960- * 1/3.9 uS = (333MHz) / reg_refresh_rate
961- */
962-#define SDRAM_REF_CTRL 0x0000004A
963-#define SDRAM_REF_CTRL_OPP100 0x0000050E
964-/*
965- * 28:25 REG_T_RP Minimum number of m_clk cycles from
966- * Precharge to Activate or Refresh, minus one.
967- * 24:21 REG_T_RCD Minimum number of m_clk cycles from
968- * Activate to Read or Write, minus one.
969- * 20:17 REG_T_WR Minimum number of m_clk cycles from last
970- * Write transfer to Pre-charge, minus one.
971- * 16:12 REG_T_RAS Minimum number of m_clk cycles from Activate
972- * to Pre-charge, minus one. reg_t_ras value need
973- * to be bigger than or equal to reg_t_rcd value.
974- * 11:6 REG_T_RC Minimum number of m_clk cycles from
975- * Activate to Activate, minus one.
976- * 5:3 REG_T_RRD Minimum number of m_clk cycles from
977- * Activate to Activate for a different bank, minus one.
978- * For an 8-bank, this field must be equal to
979- * ((tFAW/(4*tCK))-1).
980- * 2:0 REG_T_WTR Minimum number of m_clk cycles from last Write
981- */
982-#define SDRAM_TIM_1 0x04442049
983-#define SDRAM_TIM_1_OPP100 0x0CA8D51A
984-
985-/*
986- * 30:28 REG_T_XP Minimum number of m_clk cycles from
987- * Powerdown exit to any command other than a
988- * Read command, minus one.
989- * 24:16 REG_T_XSNR Minimum number of m_clk cycles from Self-Refresh
990- * exit to any command other than a Read command,
991- * minusone. REG_T_XSNR and REG_T_XSRD must be
992- * programmed with the same value.
993- * 15:6 REG_T_XSRD Minimum number of m_clk cycles from Self-Refresh
994- * exit to a Read command,
995- * minus one. REG_T_XSNR and REG_T_XSRD must be
996- * programmed with the same value.
997- * 5:3 REG_T_RTP Minimum number of m_clk cycles for the last
998- * read command to a Pre-charge command, minus one.
999- */
1000-#define SDRAM_TIM_2 0x1002008A
1001-#define SDRAM_TIM_2_OPP100 0x202E0B92
1002-
1003-/*
1004- * 23:21 REG_T_CKESR Minimum number of m_clk cycles for which LPDDR2
1005- * must remain in Self Refresh, minus one.
1006- * 20:15 REG_ZQ_ZQCS Number of m_clk clock cycles for a ZQCS command
1007- * minus one.
1008- * 14:13 REG_T_TDQSCKMAX Number of m_clk that satisfies tDQSCKmax for
1009- * LPDDR2,minus one.
1010- * 12:4 REG_T_RFC Minimum number of m_clk cycles from Refresh or
1011- * Load
1012- * Mode to Refresh or Activate, minus one.
1013- * 3:0 REG_T_RAS_MAX Maximum number of reg_refresh_rate intervals
1014- * from Activate to Precharge command. This field
1015- * must be equal to ((tRASmax / tREFI)-1)
1016- * rounded down to the next lower integer.
1017- * Value for REG_T_RAS_MAX can be calculated as
1018- * follows:
1019- * If tRASmax = 120 us and tREFI = 15.7 us, then
1020- * REG_T_RAS_MAX = ((120/15.7)-1) = 6.64.
1021- * Round down to the next lower integer.
1022- * Therefore, the programmed value must be 6
1023- */
1024-#define SDRAM_TIM_3 0x0040802F
1025-#define SDRAM_TIM_3_OPP100 0x008EA2BF
1026-#define SDRAM_CONFIG_INIT 0x80800EB1
1027-#define SDRAM_CONFIG_FINAL 0x80801AB1
1028-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
1029-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
1030-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
1031-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
1032-#define DDR_PHY_CTRL_2 0x00000000
1033-#define READ_IDLE_CTRL 0x000501FF
1034-#define READ_IDLE_CTRL_OPP100 0x000501FF
1035-#define PWR_MGMT_CTRL 0x40000000
1036-#define PWR_MGMT_CTRL_OPP100 0x80000000
1037-
1038-#else /* DDR @ 380.928 MHz */
1039-
1040-#define SDRAM_REF_CTRL 0x0000004A
1041-#define SDRAM_REF_CTRL_OPP100 0x000005CD
1042-#define SDRAM_TIM_1 0x04442049
1043-#define SDRAM_TIM_1_OPP100 0x10EB065A
1044-#define SDRAM_TIM_2 0x1002008A
1045-#define SDRAM_TIM_2_OPP100 0x20370DD2
1046-#define SDRAM_TIM_3 0x0040802F
1047-#define SDRAM_TIM_3_OPP100 0x008EA2BF
1048-#define SDRAM_CONFIG_INIT 0x80800EB1
1049-#define SDRAM_CONFIG_FINAL 0x80801AB1
1050-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
1051-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
1052-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
1053-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
1054-#define DDR_PHY_CTRL_2 0x00000000
1055-#define READ_IDLE_CTRL 0x000501FF
1056-#define READ_IDLE_CTRL_OPP100 0x000501FF
1057-#define PWR_MGMT_CTRL 0x40000000
1058-#define PWR_MGMT_CTRL_OPP100 0x80000000
1059-#endif
1060-
1061-#else /* ES1.0 */
1062-/* TODO: ES1.0 OPP100 valuse are still not popullated
1063- * 600 MHz/200 MHz
1064- */
1065-#define SDRAM_REF_CTRL 0x0000004A
1066-#define SDRAM_REF_CTRL_OPP100 0x0000050E
1067-#define SDRAM_TIM_1 0x04442049
1068-#define SDRAM_TIM_1_OPP100 0x0CA8D51A
1069-#define SDRAM_TIM_2 0x1002008A
1070-#define SDRAM_TIM_2_OPP100 0x202E0B92
1071-#define SDRAM_TIM_3 0x0040802F
1072-#define SDRAM_TIM_3_OPP100 0x008EA2BF
1073-#define SDRAM_CONFIG_INIT 0x80800EB1
1074-#define SDRAM_CONFIG_FINAL 0x80801AB1
1075-#define DDR_PHY_CTRL_1_INIT 0x849FFFF4
1076-#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404
1077-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
1078-#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408
1079-#define DDR_PHY_CTRL_2 0x00000000
1080-#define READ_IDLE_CTRL 0x000501FF
1081-#define READ_IDLE_CTRL_OPP100 0x000501FF
1082-#define PWR_MGMT_CTRL 0x80000000
1083-#define PWR_MGMT_CTRL_OPP100 0x00000000
1084-
1085-#endif
1086-
1087+#define SDRAM_CONFIG_INIT 0x80800EB1
1088+#define DDR_PHY_CTRL_1_INIT 0x849FFFF5
1089+#define READ_IDLE_CTRL 0x000501FF
1090+#define PWR_MGMT_CTRL 0x4000000f
1091+#define PWR_MGMT_CTRL_OPP100 0x4000000f
1092+#define ZQ_CONFIG 0x500b3215
1093+
1094+#define CS1_MR(mr) ((mr) | 0x80000000)
1095+struct ddr_regs{
1096+ u32 tim1;
1097+ u32 tim2;
1098+ u32 tim3;
1099+ u32 phy_ctrl_1;
1100+ u32 ref_ctrl;
1101+ u32 config_init;
1102+ u32 config_final;
1103+ u32 zq_config;
1104+ u8 mr1;
1105+ u8 mr2;
1106+};
1107+const struct ddr_regs ddr_regs_380_mhz = {
1108+ .tim1 = 0x10cb061a,
1109+ .tim2 = 0x20350d52,
1110+ .tim3 = 0x00b1431f,
1111+ .phy_ctrl_1 = 0x849FF408,
1112+ .ref_ctrl = 0x000005ca,
1113+ .config_init = 0x80000eb1,
1114+ .config_final = 0x80001ab1,
1115+ .zq_config = 0x500b3215,
1116+ .mr1 = 0x83,
1117+ .mr2 = 0x4
1118+};
1119+
1120+/*
1121+ * Unused timings - but we may need them later
1122+ * Keep them commented
1123+ */
1124+#if 0
1125+const struct ddr_regs ddr_regs_400_mhz = {
1126+ .tim1 = 0x10eb065a,
1127+ .tim2 = 0x20370dd2,
1128+ .tim3 = 0x00b1c33f,
1129+ .phy_ctrl_1 = 0x849FF408,
1130+ .ref_ctrl = 0x00000618,
1131+ .config_init = 0x80000eb1,
1132+ .config_final = 0x80001ab1,
1133+ .zq_config = 0x500b3215,
1134+ .mr1 = 0x83,
1135+ .mr2 = 0x4
1136+};
1137+
1138+const struct ddr_regs ddr_regs_200_mhz = {
1139+ .tim1 = 0x08648309,
1140+ .tim2 = 0x101b06ca,
1141+ .tim3 = 0x0048a19f,
1142+ .phy_ctrl_1 = 0x849FF405,
1143+ .ref_ctrl = 0x0000030c,
1144+ .config_init = 0x80000eb1,
1145+ .config_final = 0x80000eb1,
1146+ .zq_config = 0x500b3215,
1147+ .mr1 = 0x23,
1148+ .mr2 = 0x1
1149+};
1150+#endif
1151+
1152+const struct ddr_regs ddr_regs_200_mhz_2cs = {
1153+ .tim1 = 0x08648309,
1154+ .tim2 = 0x101b06ca,
1155+ .tim3 = 0x0048a19f,
1156+ .phy_ctrl_1 = 0x849FF405,
1157+ .ref_ctrl = 0x0000030c,
1158+ .config_init = 0x80000eb9,
1159+ .config_final = 0x80000eb9,
1160+ .zq_config = 0xD00b3215,
1161+ .mr1 = 0x23,
1162+ .mr2 = 0x1
1163+};
1164
1165 /*******************************************************
1166 * Routine: delay
1167@@ -273,14 +219,28 @@
1168 "bne 1b" : "=r" (loops) : "0"(loops));
1169 }
1170
1171+
1172+void big_delay(unsigned int count)
1173+{
1174+ int i;
1175+ for (i=0; i<count; i++)
1176+ delay(1);
1177+}
1178+
1179 /* TODO: FREQ update method is not working so shadow registers programming
1180 * is just for same of completeness. This would be safer if auto
1181 * trasnitions are working
1182 */
1183 static int emif_config(unsigned int base)
1184 {
1185- unsigned int reg_value;
1186+ unsigned int reg_value, rev;
1187+ const struct ddr_regs *ddr_regs;
1188+ rev = omap_revision();
1189
1190+ if(rev == OMAP4430_ES1_0)
1191+ ddr_regs = &ddr_regs_380_mhz;
1192+ else if (rev == OMAP4430_ES2_0)
1193+ ddr_regs = &ddr_regs_200_mhz_2cs;
1194 /*
1195 * set SDRAM CONFIG register
1196 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
1197@@ -291,38 +251,38 @@
1198 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
1199 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
1200 */
1201- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_INIT;
1202+ *(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF;
1203+ *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_init;
1204
1205 /* PHY control values */
1206 *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT;
1207- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= \
1208- DDR_PHY_CTRL_1_OPP100_INIT;
1209- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
1210+ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1;
1211
1212 /*
1213 * EMIF_READ_IDLE_CTRL
1214 */
1215 *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL;
1216- *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL_OPP100;
1217+ *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL;
1218
1219 /*
1220 * EMIF_SDRAM_TIM_1
1221 */
1222- *(volatile int*)(base + EMIF_SDRAM_TIM_1) = SDRAM_TIM_1;
1223- *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = SDRAM_TIM_1_OPP100;
1224+ *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1;
1225+ *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1;
1226
1227 /*
1228 * EMIF_SDRAM_TIM_2
1229 */
1230- *(volatile int*)(base + EMIF_SDRAM_TIM_2) = SDRAM_TIM_2;
1231- *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = SDRAM_TIM_2_OPP100;
1232+ *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2;
1233+ *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2;
1234
1235 /*
1236 * EMIF_SDRAM_TIM_3
1237 */
1238- *(volatile int*)(base + EMIF_SDRAM_TIM_3) = SDRAM_TIM_3;
1239- *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = SDRAM_TIM_3_OPP100;
1240+ *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3;
1241+ *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3;
1242
1243+ *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config;
1244 /*
1245 * EMIF_PWR_MGMT_CTRL
1246 */
1247@@ -336,97 +296,59 @@
1248 */
1249
1250 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR;
1251- do
1252- {
1253- reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
1254- } while((reg_value & 0x1) != 0);
1255+ do {
1256+ reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
1257+ } while ((reg_value & 0x1) != 0);
1258+
1259+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR);
1260+ do {
1261+ reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
1262+ } while ((reg_value & 0x1) != 0);
1263+
1264
1265 /* set MR10 register */
1266 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR;
1267 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
1268+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR);
1269+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
1270+
1271 /* wait for tZQINIT=1us */
1272 delay(10);
1273
1274 /* set MR1 register */
1275 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR;
1276- *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR1_VALUE;
1277+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
1278+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR);
1279+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
1280+
1281
1282 /* set MR2 register RL=6 for OPP100 */
1283 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR;
1284- *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR2_RL6_WL3;
1285+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
1286+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR);
1287+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
1288
1289 /* Set SDRAM CONFIG register again here with final RL-WL value */
1290- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_FINAL;
1291- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_FINAL;
1292- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= \
1293- DDR_PHY_CTRL_1_OPP100_FINAL;
1294+ *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final;
1295+ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1;
1296
1297 /*
1298 * EMIF_SDRAM_REF_CTRL
1299 * refresh rate = DDR_CLK / reg_refresh_rate
1300 * 3.9 uS = (400MHz) / reg_refresh_rate
1301 */
1302- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = SDRAM_REF_CTRL;
1303- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = \
1304- SDRAM_REF_CTRL_OPP100;
1305+ *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl;
1306+ *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl;
1307
1308 /* set MR16 register */
1309 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN;
1310 *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
1311+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) =
1312+ CS1_MR(MR16_ADDR | REF_EN);
1313+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
1314 /* LPDDR2 init complete */
1315
1316 }
1317-/* FREQ update method is not working so use Normal Reconfigure method
1318- * Shadow registers are programmed for completeness already in emif_config
1319- * fucntion @ 100 OPP
1320- * This fucntion popullated the 100% OPP values
1321- */
1322-static int emif_reconfig(unsigned int base)
1323-{
1324- unsigned int reg_value;
1325-
1326- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_FINAL;
1327-
1328- /* PHY control values */
1329- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) \
1330- = DDR_PHY_CTRL_1_OPP100_FINAL;
1331- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
1332-
1333- /*
1334- * EMIF_READ_IDLE_CTRL
1335- */
1336- *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL_OPP100;
1337-
1338- /*
1339- * EMIF_SDRAM_TIM_1
1340- */
1341- *(volatile int*)(base + EMIF_SDRAM_TIM_1) = SDRAM_TIM_1_OPP100;
1342-
1343- /*
1344- * EMIF_SDRAM_TIM_2
1345- */
1346- *(volatile int*)(base + EMIF_SDRAM_TIM_2) = SDRAM_TIM_2_OPP100;
1347-
1348- /*
1349- * EMIF_SDRAM_TIM_3
1350- */
1351- *(volatile int*)(base + EMIF_SDRAM_TIM_3) = SDRAM_TIM_3_OPP100;
1352-
1353- /*
1354- * EMIF_PWR_MGMT_CTRL
1355- */
1356- *(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL_OPP100;
1357-
1358- /*
1359- * EMIF_SDRAM_REF_CTRL
1360- * refresh rate = DDR_CLK / reg_refresh_rate
1361- * 3.9 uS = (400MHz) / reg_refresh_rate
1362- */
1363- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = SDRAM_REF_CTRL_OPP100;
1364-
1365- /* LPDDR2 init complete at 100 OPP*/
1366-
1367-}
1368 /*****************************************
1369 * Routine: ddr_init
1370 * Description: Configure DDR
1371@@ -435,19 +357,46 @@
1372 *****************************************/
1373 static void ddr_init(void)
1374 {
1375- unsigned int base_addr;
1376-
1377- /* Configurte the Control Module DDRIO device */
1378- __raw_writel(0x1c1c1c1c, 0x4A100638);
1379- __raw_writel(0x1c1c1c1c, 0x4A10063c);
1380- __raw_writel(0x1c1c1c1c, 0x4A100640);
1381- __raw_writel(0x1c1c1c1c, 0x4A100648);
1382- __raw_writel(0x1c1c1c1c, 0x4A10064c);
1383- __raw_writel(0x1c1c1c1c, 0x4A100650);
1384-
1385+ unsigned int base_addr, rev;
1386+ rev = omap_revision();
1387+
1388+ if (rev == OMAP4430_ES1_0)
1389+ {
1390+ /* Configurte the Control Module DDRIO device */
1391+ __raw_writel(0x1c1c1c1c, 0x4A100638);
1392+ __raw_writel(0x1c1c1c1c, 0x4A10063c);
1393+ __raw_writel(0x1c1c1c1c, 0x4A100640);
1394+ __raw_writel(0x1c1c1c1c, 0x4A100648);
1395+ __raw_writel(0x1c1c1c1c, 0x4A10064c);
1396+ __raw_writel(0x1c1c1c1c, 0x4A100650);
1397+ } else if (rev == OMAP4430_ES2_0) {
1398+ __raw_writel(0x9e9e9e9e, 0x4A100638);
1399+ __raw_writel(0x9e9e9e9e, 0x4A10063c);
1400+ __raw_writel(0x9e9e9e9e, 0x4A100640);
1401+ __raw_writel(0x9e9e9e9e, 0x4A100648);
1402+ __raw_writel(0x9e9e9e9e, 0x4A10064c);
1403+ __raw_writel(0x9e9e9e9e, 0x4A100650);
1404+ }
1405 /* LPDDR2IO set to NMOS PTV */
1406 __raw_writel(0x00ffc000, 0x4A100704);
1407
1408+
1409+ /*
1410+ * DMM Configuration
1411+ */
1412+
1413+ /* Both EMIFs 128 byte interleaved*/
1414+ if (rev == OMAP4430_ES1_0)
1415+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
1416+ else if (rev == OMAP4430_ES2_0)
1417+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300;
1418+
1419+ /* EMIF2 only at 0x90000000 */
1420+ //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
1421+
1422+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
1423+ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
1424+
1425 /* DDR needs to be initialised @ 19.2 MHz
1426 * So put core DPLL in bypass mode
1427 * Configure the Core DPLL but don't lock it
1428@@ -466,7 +415,6 @@
1429 /* Configure EMIF24D */
1430 base_addr = EMIF2_BASE;
1431 emif_config(base_addr);
1432-#ifdef FREQ_UPDATE_EMIF
1433 /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
1434 lock_core_dpll_shadow();
1435 /* TODO: SDC needs few hacks to get DDR freq update working */
1436@@ -483,34 +431,10 @@
1437 /* Reprogram the DDR PYHY Control register */
1438 /* PHY control values */
1439
1440-#else
1441- /* Lock Core dpll
1442- * FREQ update method is not working
1443- * so use generic approach
1444- */
1445- lock_core_dpll();
1446-
1447- /* Reconfigure EMIF14D */
1448- base_addr = EMIF1_BASE;
1449- emif_reconfig(base_addr);
1450-
1451- /* Configure EMIF24D */
1452- base_addr = EMIF2_BASE;
1453- emif_reconfig(base_addr);
1454-
1455- /* Set DLL_OVERRIDE = 0 */
1456- *(volatile int*)CM_DLL_CTRL = 0x0;
1457-
1458- /* Check for DDR PHY ready for EMIF1 & EMIF2 */
1459- while((((*(volatile int*)EMIF1_BASE + EMIF_STATUS)&(0x04)) != 0x04) \
1460- || (((*(volatile int*)EMIF2_BASE + EMIF_STATUS)&(0x04)) != 0x04));
1461-
1462-#endif /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); */ /* SDC BUG */
1463 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
1464 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
1465
1466 /* Put the Core Subsystem PD to ON State */
1467- sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x30E03);
1468
1469 /* No IDLE: BUG in SDC */
1470 //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
1471@@ -542,16 +466,12 @@
1472 * [9:8] SDRC_MAP 0x3
1473 * [7:0] SDRC_ADDR 0X0
1474 */
1475- /* 256 MB configeration */
1476- /*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80400200; */
1477- /* 512MB configeration */
1478- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
1479- /* TODO: Settings can be locked but kept open for TILER */
1480- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x00000000;
1481- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
1482- /* Invalid address TRAP */
1483- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
1484+ reset_phy(EMIF1_BASE);
1485+ reset_phy(EMIF2_BASE);
1486
1487+ *((volatile int *)0x80000000) = 0;
1488+ *((volatile int *)0x80000080) = 0;
1489+ //*((volatile int *)0x90000000) = 0;
1490 }
1491 /*****************************************
1492 * Routine: board_init
1493@@ -615,6 +535,7 @@
1494 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
1495 static scale_vcores(void)
1496 {
1497+ unsigned int rev = omap_revision();
1498 /* For VC bypass only VCOREx_CGF_FORCE is necessary and
1499 * VCOREx_CFG_VOLTAGE changes can be discarded
1500 */
1501@@ -625,7 +546,10 @@
1502
1503 /* set VCORE1 force VSEL */
1504 /* PRM_VC_VAL_BYPASS) */
1505- *(volatile int*)(0x4A307BA0) = 0x3B5512;
1506+ if(rev == OMAP4430_ES1_0)
1507+ *(volatile int*)(0x4A307BA0) = 0x3B5512;
1508+ else
1509+ *(volatile int*)(0x4A307BA0) = 0x3A5512;
1510 *(volatile int*)(0x4A307BA0) |= 0x1000000;
1511 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
1512
1513@@ -635,7 +559,10 @@
1514
1515 /* FIXME: set VCORE2 force VSEL, Check the reset value */
1516 /* PRM_VC_VAL_BYPASS) */
1517- *(volatile int*)(0x4A307BA0) = 0x315B12;
1518+ if(rev == OMAP4430_ES1_0)
1519+ *(volatile int*)(0x4A307BA0) = 0x315B12;
1520+ else
1521+ *(volatile int*)(0x4A307BA0) = 0x295B12;
1522 *(volatile int*)(0x4A307BA0) |= 0x1000000;
1523 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
1524
1525@@ -644,7 +571,10 @@
1526
1527 /*/set VCORE3 force VSEL */
1528 /* PRM_VC_VAL_BYPASS */
1529- *(volatile int*)(0x4A307BA0) = 0x316112;
1530+ if(rev == OMAP4430_ES1_0)
1531+ *(volatile int*)(0x4A307BA0) = 0x316112;
1532+ else
1533+ *(volatile int*)(0x4A307BA0) = 0x296112;
1534 *(volatile int*)(0x4A307BA0) |= 0x1000000;
1535 while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
1536
1537@@ -821,14 +751,14 @@
1538 MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
1539 MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
1540 MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
1541- MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
1542- MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
1543- MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
1544- MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
1545- MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
1546- MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
1547- MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
1548- MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
1549+ MV(CP(USBB1_ULPITLL_CLK) , ( IEN | OFF_EN | OFF_IN | M1)) /* hsi1_cawake */ \
1550+ MV(CP(USBB1_ULPITLL_STP) , ( IEN | OFF_EN | OFF_IN | M1)) /* hsi1_cadata */ \
1551+ MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_IN | M1)) /* hsi1_caflag */ \
1552+ MV(CP(USBB1_ULPITLL_NXT) , ( OFF_EN | M1)) /* hsi1_acready */ \
1553+ MV(CP(USBB1_ULPITLL_DAT0) , ( OFF_EN | M1)) /* hsi1_acwake */ \
1554+ MV(CP(USBB1_ULPITLL_DAT1) , ( OFF_EN | M1)) /* hsi1_acdata */ \
1555+ MV(CP(USBB1_ULPITLL_DAT2) , ( OFF_EN | M1)) /* hsi1_acflag */ \
1556+ MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_IN | M1)) /* hsi1_caready */ \
1557 MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
1558 MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
1559 MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
1560@@ -900,7 +830,7 @@
1561 MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
1562 MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \
1563 MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \
1564- MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \
1565+ MV(CP(USBB2_ULPITLL_CLK) , ( PTD | IEN | M3)) /* gpio_157 */ \
1566 MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \
1567 MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \
1568 MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \
1569@@ -936,7 +866,7 @@
1570 MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
1571 MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
1572 MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
1573- MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \
1574+ MV(CP(SYS_BOOT3) , ( PTD | IEN | M3)) /* gpio_187 */ \
1575 MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \
1576 MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \
1577 MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \
1578@@ -981,6 +911,9 @@
1579 MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \
1580 MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \
1581 MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \
1582+ MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \
1583+ MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \
1584+ MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */
1585 // MV1(WK(PAD0_JTAG_NTRST) , ( IEN | M0)) /* jtag_ntrst */ \
1586 MV1(WK(PAD1_JTAG_TCK) , ( IEN | M0)) /* jtag_tck */ \
1587 MV1(WK(PAD0_JTAG_RTCK) , ( M0)) /* jtag_rtck */ \
1588@@ -1133,7 +1066,7 @@
1589 MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
1590 MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \
1591 MV(CP(UART4_TX), (M0)) /* uart4_tx */ \
1592- MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \
1593+ MV(CP(USBB2_ULPITLL_CLK), (PTD | IEN | M3)) /* gpio_157 */ \
1594 MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \
1595 MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \
1596 MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \
1597@@ -1169,7 +1102,7 @@
1598 MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \
1599 MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \
1600 MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \
1601- MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \
1602+ MV(CP(SYS_BOOT3), (PTD | IEN | M3_SAFE)) /* gpio_187 */ \
1603 MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \
1604 MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \
1605 MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \
1606@@ -1255,3 +1188,7 @@
1607 {
1608 return 1;
1609 }
1610+void reset_phy(unsigned int base)
1611+{
1612+ *(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
1613+}
1614
1615=== modified file 'cpu/omap4/cpu.c'
1616--- cpu/omap4/cpu.c 2010-05-28 09:51:26 +0000
1617+++ cpu/omap4/cpu.c 2010-09-04 03:39:41 +0000
1618@@ -49,3 +49,27 @@
1619 return 0;
1620 }
1621
1622+unsigned int cortex_a9_rev(void)
1623+{
1624+
1625+ unsigned int i;
1626+
1627+ /* turn off I/D-cache */
1628+ asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (i));
1629+
1630+ return i;
1631+}
1632+
1633+unsigned int omap_revision(void)
1634+{
1635+ unsigned int rev = cortex_a9_rev();
1636+
1637+ switch(rev) {
1638+ case 0x410FC091:
1639+ return OMAP4430_ES1_0;
1640+ case 0x411FC092:
1641+ return OMAP4430_ES2_0;
1642+ default:
1643+ return OMAP4430_SILICON_ID_INVALID;
1644+ }
1645+}
1646
1647=== modified file 'debian/changelog'
1648--- debian/changelog 2010-06-24 15:15:33 +0000
1649+++ debian/changelog 2010-09-04 03:39:41 +0000
1650@@ -1,3 +1,14 @@
1651+x-loader-omap4 (L24.9git20100901-0ubuntu1) maverick; urgency=low
1652+
1653+ * new upstream release
1654+ - adds Omap 4 ES2 6 layer and 8 layer support (LP: #624652)
1655+ - uses branch omap4_panda_L24.9 from http://gitorious.org/pandaboard/x-loader
1656+ - es2 compatible only
1657+ * adding 02-panda-fix-ddr-timings.patch and 03-panda-x-loader-emif-1gb-support.patch
1658+ to have 1gb support
1659+
1660+ -- Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Fri, 03 Sep 2010 01:48:30 -0300
1661+
1662 x-loader-omap4 (L24.7git20100624-0ubuntu1) maverick; urgency=low
1663
1664 * new upstream release
1665
1666=== added file 'debian/patches/02-panda-fix-ddr-timings.patch'
1667--- debian/patches/02-panda-fix-ddr-timings.patch 1970-01-01 00:00:00 +0000
1668+++ debian/patches/02-panda-fix-ddr-timings.patch 2010-09-04 03:39:41 +0000
1669@@ -0,0 +1,299 @@
1670+From f3f113b81687d4034697645ebbc322b2973911c1 Mon Sep 17 00:00:00 2001
1671+From: Rob Clark <rob@ti.com>
1672+Date: Tue, 10 Aug 2010 14:36:42 -0500
1673+Subject: [PATCH 1/2] Panda: Post ES2.0, we were setting the same DDR timings for ES1.0 and ES2.0.
1674+
1675+Although this is safe on both, this was not optimal for both:
1676+ Refresh rate was not optimal for ES1.0.
1677+ Other timings were not optimal for ES2.0
1678+
1679+Correcting this by doing run-time check and applying different timings
1680+for ES1.0 and ES2.0
1681+
1682+a port of a patch by aneesh@ti.com
1683+---
1684+ board/omap4430panda/omap4430panda.c | 181 +++++++++++++----------------------
1685+ 1 files changed, 68 insertions(+), 113 deletions(-)
1686+
1687+diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
1688+index be9f268..d34768c 100644
1689+--- a/board/omap4430panda/omap4430panda.c
1690++++ b/board/omap4430panda/omap4430panda.c
1691+@@ -129,27 +129,56 @@
1692+ * should be programmed for new OPP.
1693+ */
1694+ /* Elpida 2x2Gbit */
1695+-#define SDRAM_REF_CTRL 0x0000004A
1696+-#define SDRAM_REF_CTRL_OPP100 0x0000030c
1697+-#define SDRAM_TIM_1 0x04442049
1698+-#define SDRAM_TIM_1_OPP100 0x10eb066A
1699+-#define SDRAM_TIM_2 0x1002008A
1700+-#define SDRAM_TIM_2_OPP100 0x20370dd2
1701+-#define SDRAM_TIM_3 0x0040802F
1702+-#define SDRAM_TIM_3_OPP100 0x00b1c33f
1703+ #define SDRAM_CONFIG_INIT 0x80800EB1
1704+-#define SDRAM_CONFIG_FINAL 0x98801ab1
1705+ #define DDR_PHY_CTRL_1_INIT 0x849FFFF5
1706+-#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8
1707+-#define DDR_PHY_CTRL_1_OPP100 0x849FF408
1708+-#define DDR_PHY_CTRL_2 0x00000000
1709+-#define READ_IDLE_CTRL 0x00050139
1710+-#define READ_IDLE_CTRL_OPP100 0x00050139
1711++#define READ_IDLE_CTRL 0x000501FF
1712+ #define PWR_MGMT_CTRL 0x4000000f
1713+ #define PWR_MGMT_CTRL_OPP100 0x4000000f
1714+-#define ZQ_CONFIG 0x50073214
1715+-
1716+-
1717++#define ZQ_CONFIG 0x500b3215
1718++
1719++struct ddr_regs{
1720++ u32 tim1;
1721++ u32 tim2;
1722++ u32 tim3;
1723++ u32 phy_ctrl_1;
1724++ u32 ref_ctrl;
1725++ u32 config;
1726++ u8 mr1;
1727++ u8 mr2;
1728++};
1729++
1730++const struct ddr_regs ddr_regs_400_mhz = {
1731++ .tim1 = 0x10eb065a,
1732++ .tim2 = 0x20370dd2,
1733++ .tim3 = 0x00b1c33f,
1734++ .phy_ctrl_1 = 0x849FF408,
1735++ .ref_ctrl = 0x00000618,
1736++ .config = 0x80001ab1,
1737++ .mr1 = 0x83,
1738++ .mr2 = 0x4
1739++};
1740++
1741++const struct ddr_regs ddr_regs_380_mhz = {
1742++ .tim1 = 0x10cb061a,
1743++ .tim2 = 0x20350d52,
1744++ .tim3 = 0x00b1431f,
1745++ .phy_ctrl_1 = 0x849FF408,
1746++ .ref_ctrl = 0x000005ca,
1747++ .config = 0x80001ab1,
1748++ .mr1 = 0x83,
1749++ .mr2 = 0x4
1750++};
1751++
1752++const struct ddr_regs ddr_regs_200_mhz = {
1753++ .tim1 = 0x08648309,
1754++ .tim2 = 0x101b06ca,
1755++ .tim3 = 0x0048a19f,
1756++ .phy_ctrl_1 = 0x849FF405,
1757++ .ref_ctrl = 0x0000030c,
1758++ .config = 0x80000eb1,
1759++ .mr1 = 0x23,
1760++ .mr2 = 0x1
1761++};
1762+ /*******************************************************
1763+ * Routine: delay
1764+ * Description: spinning delay to use before udelay works
1765+@@ -174,8 +203,14 @@ void big_delay(unsigned int count)
1766+ */
1767+ static int emif_config(unsigned int base)
1768+ {
1769+- unsigned int reg_value;
1770++ unsigned int reg_value, rev;
1771++ struct ddr_regs *ddr_regs;
1772++ rev = omap_revision();
1773+
1774++ if(rev == OMAP4430_ES1_0)
1775++ ddr_regs = &ddr_regs_380_mhz;
1776++ else if(rev == OMAP4430_ES2_0)
1777++ ddr_regs = &ddr_regs_200_mhz;
1778+ /*
1779+ * set SDRAM CONFIG register
1780+ * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
1781+@@ -190,33 +225,31 @@ static int emif_config(unsigned int base)
1782+
1783+ /* PHY control values */
1784+ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT;
1785+- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= \
1786+- DDR_PHY_CTRL_1_OPP100;
1787+- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
1788++ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1;
1789+
1790+ /*
1791+ * EMIF_READ_IDLE_CTRL
1792+ */
1793+ *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL;
1794+- *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL_OPP100;
1795++ *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL;
1796+
1797+ /*
1798+ * EMIF_SDRAM_TIM_1
1799+ */
1800+- *(volatile int*)(base + EMIF_SDRAM_TIM_1) = SDRAM_TIM_1;
1801+- *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = SDRAM_TIM_1_OPP100;
1802++ *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1;
1803++ *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1;
1804+
1805+ /*
1806+ * EMIF_SDRAM_TIM_2
1807+ */
1808+- *(volatile int*)(base + EMIF_SDRAM_TIM_2) = SDRAM_TIM_2;
1809+- *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = SDRAM_TIM_2_OPP100;
1810++ *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2;
1811++ *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2;
1812+
1813+ /*
1814+ * EMIF_SDRAM_TIM_3
1815+ */
1816+- *(volatile int*)(base + EMIF_SDRAM_TIM_3) = SDRAM_TIM_3;
1817+- *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = SDRAM_TIM_3_OPP100;
1818++ *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3;
1819++ *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3;
1820+
1821+ *(volatile int*)(base + EMIF_ZQ_CONFIG) = ZQ_CONFIG;
1822+ /*
1823+@@ -230,14 +263,12 @@ static int emif_config(unsigned int base)
1824+ * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
1825+ * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
1826+ */
1827+- big_delay(1000);
1828+-#if 0
1829++
1830+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR;
1831+ do
1832+ {
1833+ reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
1834+ } while((reg_value & 0x1) != 0);
1835+-#endif
1836+
1837+ /* set MR10 register */
1838+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR;
1839+@@ -247,24 +278,23 @@ static int emif_config(unsigned int base)
1840+
1841+ /* set MR1 register */
1842+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR;
1843+- *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR1_VALUE;
1844++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
1845+
1846+ /* set MR2 register RL=6 for OPP100 */
1847+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR;
1848+- *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR2_RL6_WL3;
1849++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
1850+
1851+ /* Set SDRAM CONFIG register again here with final RL-WL value */
1852+- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_FINAL;
1853+- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_FINAL;
1854++ *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config;
1855++ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1;
1856+
1857+ /*
1858+ * EMIF_SDRAM_REF_CTRL
1859+ * refresh rate = DDR_CLK / reg_refresh_rate
1860+ * 3.9 uS = (400MHz) / reg_refresh_rate
1861+ */
1862+- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = SDRAM_REF_CTRL;
1863+- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = \
1864+- SDRAM_REF_CTRL_OPP100;
1865++ *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl;
1866++ *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl;
1867+
1868+ /* set MR16 register */
1869+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN;
1870+@@ -272,57 +302,6 @@ static int emif_config(unsigned int base)
1871+ /* LPDDR2 init complete */
1872+
1873+ }
1874+-/* FREQ update method is not working so use Normal Reconfigure method
1875+- * Shadow registers are programmed for completeness already in emif_config
1876+- * fucntion @ 100 OPP
1877+- * This fucntion popullated the 100% OPP values
1878+- */
1879+-static int emif_reconfig(unsigned int base)
1880+-{
1881+- unsigned int reg_value;
1882+-
1883+- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_FINAL;
1884+-
1885+- /* PHY control values */
1886+- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) \
1887+- = DDR_PHY_CTRL_1_OPP100;
1888+- *(volatile int*)(base + EMIF_DDR_PHY_CTRL_2) = DDR_PHY_CTRL_2;
1889+-
1890+- /*
1891+- * EMIF_READ_IDLE_CTRL
1892+- */
1893+- *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL_OPP100;
1894+-
1895+- /*
1896+- * EMIF_SDRAM_TIM_1
1897+- */
1898+- *(volatile int*)(base + EMIF_SDRAM_TIM_1) = SDRAM_TIM_1_OPP100;
1899+-
1900+- /*
1901+- * EMIF_SDRAM_TIM_2
1902+- */
1903+- *(volatile int*)(base + EMIF_SDRAM_TIM_2) = SDRAM_TIM_2_OPP100;
1904+-
1905+- /*
1906+- * EMIF_SDRAM_TIM_3
1907+- */
1908+- *(volatile int*)(base + EMIF_SDRAM_TIM_3) = SDRAM_TIM_3_OPP100;
1909+-
1910+- /*
1911+- * EMIF_PWR_MGMT_CTRL
1912+- */
1913+- *(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL_OPP100;
1914+-
1915+- /*
1916+- * EMIF_SDRAM_REF_CTRL
1917+- * refresh rate = DDR_CLK / reg_refresh_rate
1918+- * 3.9 uS = (400MHz) / reg_refresh_rate
1919+- */
1920+- *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = SDRAM_REF_CTRL_OPP100;
1921+-
1922+- /* LPDDR2 init complete at 100 OPP*/
1923+-
1924+-}
1925+ /*****************************************
1926+ * Routine: ddr_init
1927+ * Description: Configure DDR
1928+@@ -389,7 +368,6 @@ static void ddr_init(void)
1929+ /* Configure EMIF24D */
1930+ base_addr = EMIF2_BASE;
1931+ emif_config(base_addr);
1932+-#ifdef FREQ_UPDATE_EMIF
1933+ /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
1934+ lock_core_dpll_shadow();
1935+ /* TODO: SDC needs few hacks to get DDR freq update working */
1936+@@ -406,29 +384,6 @@ static void ddr_init(void)
1937+ /* Reprogram the DDR PYHY Control register */
1938+ /* PHY control values */
1939+
1940+-#else
1941+- /* Lock Core dpll
1942+- * FREQ update method is not working
1943+- * so use generic approach
1944+- */
1945+- lock_core_dpll();
1946+-
1947+- /* Reconfigure EMIF14D */
1948+- base_addr = EMIF1_BASE;
1949+- emif_reconfig(base_addr);
1950+-
1951+- /* Configure EMIF24D */
1952+- base_addr = EMIF2_BASE;
1953+- emif_reconfig(base_addr);
1954+-
1955+- /* Set DLL_OVERRIDE = 0 */
1956+- *(volatile int*)CM_DLL_CTRL = 0x0;
1957+-
1958+- /* Check for DDR PHY ready for EMIF1 & EMIF2 */
1959+- while((((*(volatile int*)EMIF1_BASE + EMIF_STATUS)&(0x04)) != 0x04) \
1960+- || (((*(volatile int*)EMIF2_BASE + EMIF_STATUS)&(0x04)) != 0x04));
1961+-
1962+-#endif /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); */ /* SDC BUG */
1963+ sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
1964+ sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
1965+
1966+--
1967+1.7.1
1968+
1969
1970=== added file 'debian/patches/03-panda-x-loader-emif-1gb-support.patch'
1971--- debian/patches/03-panda-x-loader-emif-1gb-support.patch 1970-01-01 00:00:00 +0000
1972+++ debian/patches/03-panda-x-loader-emif-1gb-support.patch 2010-09-04 03:39:41 +0000
1973@@ -0,0 +1,247 @@
1974+From 8a77d574033340217bd734ecb4140a7f241fa434 Mon Sep 17 00:00:00 2001
1975+From: Rob Clark <rob@ti.com>
1976+Date: Tue, 10 Aug 2010 14:41:03 -0500
1977+Subject: [PATCH 2/2] Panda: x-loader: emif: 1GB support
1978+
1979+Add 1GB support
1980+
1981+a port of a patch by aneesh@ti.com
1982+---
1983+ board/omap4430panda/omap4430panda.c | 113 ++++++++++++++++++++++++-----------
1984+ 1 files changed, 79 insertions(+), 34 deletions(-)
1985+
1986+diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
1987+index d34768c..48fe831 100644
1988+--- a/board/omap4430panda/omap4430panda.c
1989++++ b/board/omap4430panda/omap4430panda.c
1990+@@ -136,49 +136,77 @@
1991+ #define PWR_MGMT_CTRL_OPP100 0x4000000f
1992+ #define ZQ_CONFIG 0x500b3215
1993+
1994++#define CS1_MR(mr) ((mr) | 0x80000000)
1995+ struct ddr_regs{
1996+ u32 tim1;
1997+ u32 tim2;
1998+ u32 tim3;
1999+ u32 phy_ctrl_1;
2000+ u32 ref_ctrl;
2001+- u32 config;
2002++ u32 config_init;
2003++ u32 config_final;
2004++ u32 zq_config;
2005+ u8 mr1;
2006+ u8 mr2;
2007+ };
2008++const struct ddr_regs ddr_regs_380_mhz = {
2009++ .tim1 = 0x10cb061a,
2010++ .tim2 = 0x20350d52,
2011++ .tim3 = 0x00b1431f,
2012++ .phy_ctrl_1 = 0x849FF408,
2013++ .ref_ctrl = 0x000005ca,
2014++ .config_init = 0x80000eb1,
2015++ .config_final = 0x80001ab1,
2016++ .zq_config = 0x500b3215,
2017++ .mr1 = 0x83,
2018++ .mr2 = 0x4
2019++};
2020+
2021++/*
2022++ * Unused timings - but we may need them later
2023++ * Keep them commented
2024++ */
2025++#if 0
2026+ const struct ddr_regs ddr_regs_400_mhz = {
2027+ .tim1 = 0x10eb065a,
2028+ .tim2 = 0x20370dd2,
2029+ .tim3 = 0x00b1c33f,
2030+ .phy_ctrl_1 = 0x849FF408,
2031+ .ref_ctrl = 0x00000618,
2032+- .config = 0x80001ab1,
2033++ .config_init = 0x80000eb1,
2034++ .config_final = 0x80001ab1,
2035++ .zq_config = 0x500b3215,
2036+ .mr1 = 0x83,
2037+ .mr2 = 0x4
2038+ };
2039+
2040+-const struct ddr_regs ddr_regs_380_mhz = {
2041+- .tim1 = 0x10cb061a,
2042+- .tim2 = 0x20350d52,
2043+- .tim3 = 0x00b1431f,
2044+- .phy_ctrl_1 = 0x849FF408,
2045+- .ref_ctrl = 0x000005ca,
2046+- .config = 0x80001ab1,
2047+- .mr1 = 0x83,
2048+- .mr2 = 0x4
2049++const struct ddr_regs ddr_regs_200_mhz = {
2050++ .tim1 = 0x08648309,
2051++ .tim2 = 0x101b06ca,
2052++ .tim3 = 0x0048a19f,
2053++ .phy_ctrl_1 = 0x849FF405,
2054++ .ref_ctrl = 0x0000030c,
2055++ .config_init = 0x80000eb1,
2056++ .config_final = 0x80000eb1,
2057++ .zq_config = 0x500b3215,
2058++ .mr1 = 0x23,
2059++ .mr2 = 0x1
2060+ };
2061++#endif
2062+
2063+-const struct ddr_regs ddr_regs_200_mhz = {
2064++const struct ddr_regs ddr_regs_200_mhz_2cs = {
2065+ .tim1 = 0x08648309,
2066+ .tim2 = 0x101b06ca,
2067+ .tim3 = 0x0048a19f,
2068+ .phy_ctrl_1 = 0x849FF405,
2069+ .ref_ctrl = 0x0000030c,
2070+- .config = 0x80000eb1,
2071++ .config_init = 0x80000eb9,
2072++ .config_final = 0x80000eb9,
2073++ .zq_config = 0xD00b3215,
2074+ .mr1 = 0x23,
2075+ .mr2 = 0x1
2076+ };
2077++
2078+ /*******************************************************
2079+ * Routine: delay
2080+ * Description: spinning delay to use before udelay works
2081+@@ -204,13 +232,13 @@ void big_delay(unsigned int count)
2082+ static int emif_config(unsigned int base)
2083+ {
2084+ unsigned int reg_value, rev;
2085+- struct ddr_regs *ddr_regs;
2086++ const struct ddr_regs *ddr_regs;
2087+ rev = omap_revision();
2088+
2089+ if(rev == OMAP4430_ES1_0)
2090+ ddr_regs = &ddr_regs_380_mhz;
2091+- else if(rev == OMAP4430_ES2_0)
2092+- ddr_regs = &ddr_regs_200_mhz;
2093++ else if (rev == OMAP4430_ES2_0)
2094++ ddr_regs = &ddr_regs_200_mhz_2cs;
2095+ /*
2096+ * set SDRAM CONFIG register
2097+ * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
2098+@@ -221,7 +249,8 @@ static int emif_config(unsigned int base)
2099+ * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
2100+ * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
2101+ */
2102+- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = SDRAM_CONFIG_INIT;
2103++ *(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF;
2104++ *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_init;
2105+
2106+ /* PHY control values */
2107+ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT;
2108+@@ -251,7 +280,7 @@ static int emif_config(unsigned int base)
2109+ *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3;
2110+ *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3;
2111+
2112+- *(volatile int*)(base + EMIF_ZQ_CONFIG) = ZQ_CONFIG;
2113++ *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config;
2114+ /*
2115+ * EMIF_PWR_MGMT_CTRL
2116+ */
2117+@@ -265,27 +294,40 @@ static int emif_config(unsigned int base)
2118+ */
2119+
2120+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR;
2121+- do
2122+- {
2123++ do {
2124+ reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
2125+- } while((reg_value & 0x1) != 0);
2126++ } while ((reg_value & 0x1) != 0);
2127++
2128++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR);
2129++ do {
2130++ reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
2131++ } while ((reg_value & 0x1) != 0);
2132++
2133+
2134+ /* set MR10 register */
2135+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR;
2136+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
2137++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR);
2138++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
2139++
2140+ /* wait for tZQINIT=1us */
2141+ delay(10);
2142+
2143+ /* set MR1 register */
2144+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR;
2145+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
2146++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR);
2147++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
2148++
2149+
2150+ /* set MR2 register RL=6 for OPP100 */
2151+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR;
2152+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
2153++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR);
2154++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
2155+
2156+ /* Set SDRAM CONFIG register again here with final RL-WL value */
2157+- *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config;
2158++ *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final;
2159+ *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1;
2160+
2161+ /*
2162+@@ -299,6 +341,9 @@ static int emif_config(unsigned int base)
2163+ /* set MR16 register */
2164+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN;
2165+ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
2166++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) =
2167++ CS1_MR(MR16_ADDR | REF_EN);
2168++ *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
2169+ /* LPDDR2 init complete */
2170+
2171+ }
2172+@@ -313,16 +358,7 @@ static void ddr_init(void)
2173+ unsigned int base_addr, rev;
2174+ rev = omap_revision();
2175+
2176+- if(rev == OMAP4430_ES2_0)
2177+- {
2178+- __raw_writel(0x9e9e9e9e, 0x4A100638);
2179+- __raw_writel(0x9e9e9e9e, 0x4A10063c);
2180+- __raw_writel(0x9e9e9e9e, 0x4A100640);
2181+- __raw_writel(0x9e9e9e9e, 0x4A100648);
2182+- __raw_writel(0x9e9e9e9e, 0x4A10064c);
2183+- __raw_writel(0x9e9e9e9e, 0x4A100650);
2184+- }
2185+- else if(rev == OMAP4430_ES1_0)
2186++ if (rev == OMAP4430_ES1_0)
2187+ {
2188+ /* Configurte the Control Module DDRIO device */
2189+ __raw_writel(0x1c1c1c1c, 0x4A100638);
2190+@@ -331,8 +367,14 @@ static void ddr_init(void)
2191+ __raw_writel(0x1c1c1c1c, 0x4A100648);
2192+ __raw_writel(0x1c1c1c1c, 0x4A10064c);
2193+ __raw_writel(0x1c1c1c1c, 0x4A100650);
2194++ } else if (rev == OMAP4430_ES2_0) {
2195++ __raw_writel(0x9e9e9e9e, 0x4A100638);
2196++ __raw_writel(0x9e9e9e9e, 0x4A10063c);
2197++ __raw_writel(0x9e9e9e9e, 0x4A100640);
2198++ __raw_writel(0x9e9e9e9e, 0x4A100648);
2199++ __raw_writel(0x9e9e9e9e, 0x4A10064c);
2200++ __raw_writel(0x9e9e9e9e, 0x4A100650);
2201+ }
2202+-
2203+ /* LPDDR2IO set to NMOS PTV */
2204+ __raw_writel(0x00ffc000, 0x4A100704);
2205+
2206+@@ -342,7 +384,10 @@ static void ddr_init(void)
2207+ */
2208+
2209+ /* Both EMIFs 128 byte interleaved*/
2210+- *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
2211++ if (rev == OMAP4430_ES1_0)
2212++ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
2213++ else if (rev == OMAP4430_ES2_0)
2214++ *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300;
2215+
2216+ /* EMIF2 only at 0x90000000 */
2217+ //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
2218+--
2219+1.7.1
2220+
2221
2222=== modified file 'debian/patches/series'
2223--- debian/patches/series 2010-05-28 09:51:26 +0000
2224+++ debian/patches/series 2010-09-04 03:39:41 +0000
2225@@ -1,1 +1,3 @@
2226 01-add-missing-uboot-headers.patch
2227+02-panda-fix-ddr-timings.patch
2228+03-panda-x-loader-emif-1gb-support.patch
2229
2230=== modified file 'include/asm/arch-omap4/cpu.h'
2231--- include/asm/arch-omap4/cpu.h 2010-05-28 09:51:26 +0000
2232+++ include/asm/arch-omap4/cpu.h 2010-09-04 03:39:41 +0000
2233@@ -447,4 +447,17 @@
2234 extern void lcd_panel_disable(void);
2235 #endif
2236
2237+/* Silicon revisions */
2238+#define OMAP4430_SILICON_ID_INVALID 0
2239+#define OMAP4430_ES1_0 1
2240+#define OMAP4430_ES2_0 2
2241+
2242+#ifndef __ASSEMBLY__
2243+/*Functions for silicon revision */
2244+unsigned int omap_revision(void);
2245+unsigned int cortex_a9_rev(void);
2246+
2247+void big_delay(unsigned int count);
2248+#endif
2249+
2250 #endif
2251
2252=== modified file 'include/configs/omap4430panda.h'
2253--- include/configs/omap4430panda.h 2010-06-24 15:15:33 +0000
2254+++ include/configs/omap4430panda.h 2010-09-04 03:39:41 +0000
2255@@ -40,18 +40,13 @@
2256 #define CONFIG_OMAP4430 1 /* which is in a 3430 */
2257 #define CONFIG_4430PANDA 1 /* working with SDP */
2258
2259-/* Keep Default @ 33MHz at boot loader level
2260- * On Phoenix board vlotage needs to be bumped up
2261- * before scaling the MPU up
2262- */
2263-#define CONFIG_MPU_600 1
2264 #define CORE_190MHZ 1
2265 /* Enable the below macro if MMC boot support is required */
2266 #define CONFIG_MMC 1
2267 #if defined(CONFIG_MMC)
2268- /* To Enable MMC boot for OMAP4430 Panda */
2269+ /* To Enable MMC boot for OMAP4430 SDP */
2270 //#define CONFIG_MMC1 1
2271- /* To Enable EMMC boot for OMAP4430 Panda */
2272+ /* To Enable EMMC boot for OMAP4430 SDP */
2273 #define CONFIG_MMC2 1
2274 #define CFG_CMD_MMC 1
2275 #define CFG_CMD_FAT 1
2276
2277=== modified file 'scripts/signGP.c'
2278--- scripts/signGP.c 2010-05-28 09:51:26 +0000
2279+++ scripts/signGP.c 2010-09-04 03:39:41 +0000
2280@@ -12,6 +12,212 @@
2281 #include <sys/stat.h>
2282 #include <string.h>
2283 #include <malloc.h>
2284+#include <linux/types.h>
2285+
2286+#undef CH_WITH_CHRAM
2287+struct chsettings {
2288+ __u32 section_key;
2289+ __u8 valid;
2290+ __u8 version;
2291+ __u16 reserved;
2292+ __u32 flags;
2293+} __attribute__ ((__packed__));
2294+
2295+/* __u32 cm_clksel_core;
2296+ __u32 reserved1;
2297+ __u32 cm_autoidle_dpll_mpu;
2298+ __u32 cm_clksel_dpll_mpu;
2299+ __u32 cm_div_m2_dpll_mpu;
2300+ __u32 cm_autoidle_dpll_core;
2301+ __u32 cm_clksel_dpll_core;
2302+ __u32 cm_div_m2_dpll_core;
2303+ __u32 cm_div_m3_dpll_core;
2304+ __u32 cm_div_m4_dpll_core;
2305+ __u32 cm_div_m5_dpll_core;
2306+ __u32 cm_div_m6_dpll_core;
2307+ __u32 cm_div_m7_dpll_core;
2308+ __u32 cm_autoidle_dpll_per;
2309+ __u32 cm_clksel_dpll_per;
2310+ __u32 cm_div_m2_dpll_per;
2311+ __u32 cm_div_m3_dpll_per;
2312+ __u32 cm_div_m4_dpll_per;
2313+ __u32 cm_div_m5_dpll_per;
2314+ __u32 cm_div_m6_dpll_per;
2315+ __u32 cm_div_m7_dpll_per;
2316+ __u32 cm_autoidle_dpll_usb;
2317+ __u32 cm_clksel_dpll_usb;
2318+ __u32 cm_div_m2_dpll_usb;
2319+}*/
2320+
2321+struct gp_header {
2322+ __u32 size;
2323+ __u32 load_addr;
2324+} __attribute__ ((__packed__));
2325+
2326+struct ch_toc {
2327+ __u32 section_offset;
2328+ __u32 section_size;
2329+ __u8 unused[12];
2330+ __u8 section_name[12];
2331+} __attribute__ ((__packed__));
2332+
2333+struct chram {
2334+ /*CHRAM */
2335+ __u32 section_key_chr;
2336+ __u8 section_disable_chr;
2337+ __u8 pad_chr[3];
2338+ /*EMIF1 */
2339+ __u32 config_emif1;
2340+ __u32 refresh_emif1;
2341+ __u32 tim1_emif1;
2342+ __u32 tim2_emif1;
2343+ __u32 tim3_emif1;
2344+ __u32 pwrControl_emif1;
2345+ __u32 phy_cntr1_emif1;
2346+ __u32 phy_cntr2_emif1;
2347+ __u8 modereg1_emif1;
2348+ __u8 modereg2_emif1;
2349+ __u8 modereg3_emif1;
2350+ __u8 pad_emif1;
2351+ /*EMIF2 */
2352+ __u32 config_emif2;
2353+ __u32 refresh_emif2;
2354+ __u32 tim1_emif2;
2355+ __u32 tim2_emif2;
2356+ __u32 tim3_emif2;
2357+ __u32 pwrControl_emif2;
2358+ __u32 phy_cntr1_emif2;
2359+ __u32 phy_cntr2_emif2;
2360+ __u8 modereg1_emif2;
2361+ __u8 modereg2_emif2;
2362+ __u8 modereg3_emif2;
2363+ __u8 pad_emif2;
2364+
2365+ __u32 dmm_lisa_map;
2366+ __u8 flags;
2367+ __u8 pad[3];
2368+} __attribute__ ((__packed__));
2369+
2370+
2371+struct ch_chsettings_chram {
2372+ struct ch_toc toc_chsettings;
2373+ struct ch_toc toc_chram;
2374+ struct ch_toc toc_terminator;
2375+ struct chsettings section_chsettings;
2376+ struct chram section_chram;
2377+ __u8 padding1[512 -
2378+ (sizeof(struct ch_toc) * 3 +
2379+ sizeof(struct chsettings) + sizeof(struct chram))];
2380+ //struct gp_header gpheader;
2381+} __attribute__ ((__packed__));
2382+
2383+struct ch_chsettings_nochram {
2384+ struct ch_toc toc_chsettings;
2385+ struct ch_toc toc_terminator;
2386+ struct chsettings section_chsettings;
2387+ __u8 padding1[512 -
2388+ (sizeof(struct ch_toc) * 2 +
2389+ sizeof(struct chsettings))];
2390+ //struct gp_header gpheader;
2391+} __attribute__ ((__packed__));
2392+
2393+
2394+#ifdef CH_WITH_CHRAM
2395+const struct ch_chsettings_chram config_header = {
2396+ //CHSETTINGS TOC
2397+ {sizeof(struct ch_toc) * 4,
2398+ sizeof(struct chsettings),
2399+ "",
2400+ {"CHSETTINGS"}
2401+ },
2402+ //CHRAM TOC
2403+ {sizeof(struct ch_toc) * 4 + sizeof(struct chsettings),
2404+ sizeof(struct chram),
2405+ "",
2406+ {"CHRAM"}
2407+ },
2408+ // toc terminator
2409+ {0xFFFFFFFF,
2410+ 0xFFFFFFFF,
2411+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2412+ 0xFF},
2413+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2414+ 0xFF}
2415+ },
2416+ //CHSETTINGS section
2417+ {
2418+ 0xC0C0C0C1,
2419+ 0,
2420+ 1,
2421+ 0,
2422+ 0},
2423+ //CHRAM section
2424+ {
2425+ 0xc0c0c0c2,
2426+ 0x01,
2427+ {0x00, 0x00, 0x00},
2428+
2429+ /*EMIF1 */
2430+ 0x80800eb2,
2431+ 0x00000010,
2432+ 0x110d1624,
2433+ 0x3058161b,
2434+ 0x030060b2,
2435+ 0x00000200,
2436+ 0x901ff416,
2437+ 0x00000000,
2438+ 0x23,
2439+ 0x01,
2440+ 0x02,
2441+ 0x00,
2442+
2443+ /*EMIF2 */
2444+ 0x80800eb2,
2445+ 0x000002ba,
2446+ 0x110d1624,
2447+ 0x3058161b,
2448+ 0x03006542,
2449+ 0x00000200,
2450+ 0x901ff416,
2451+ 0x00000000,
2452+ 0x23,
2453+ 0x01,
2454+ 0x02,
2455+ 0x00,
2456+
2457+ /* LISA map */
2458+ 0x80700100,
2459+ 0x05,
2460+ {0x00, 0x00, 0x00},
2461+ },
2462+ ""
2463+};
2464+#else
2465+struct ch_chsettings_nochram config_header __attribute__((section(".config_header"))) = {
2466+ //CHSETTINGS TOC
2467+ {(sizeof(struct ch_toc)) * 2,
2468+ sizeof(struct chsettings),
2469+ "",
2470+ {"CHSETTINGS"}
2471+ },
2472+ // toc terminator
2473+ {0xFFFFFFFF,
2474+ 0xFFFFFFFF,
2475+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2476+ 0xFF},
2477+ {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2478+ 0xFF}
2479+ },
2480+ //CHSETTINGS section
2481+ {
2482+ 0xC0C0C0C1,
2483+ 0,
2484+ 1,
2485+ 0,
2486+ 0},
2487+ ""
2488+};
2489+#endif
2490
2491
2492 main(int argc, char *argv[])
2493@@ -31,7 +237,7 @@
2494 strcpy(ifname, argv[1]);
2495
2496 if (argc == 3)
2497- loadaddr = strtol(argv[2], NULL, 16);
2498+ loadaddr = strtoul(argv[2], NULL, 16);
2499
2500 // Form the output file name.
2501 strcpy(ofname, ifname);
2502@@ -61,6 +267,7 @@
2503 //for (i=0; i<0x200; i++)
2504 // fwrite(&ch, 1, 1, ofile);
2505
2506+ fwrite(&config_header, 1, 512, ofile);
2507 fwrite(&len, 1, 4, ofile);
2508 fwrite(&loadaddr, 1, 4, ofile);
2509 for (i=0; i<len; i++) {

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