0d6695b...
by
Stanislav Lisovskiy <email address hidden>
drm/i915/adl_p: Same slices mask is not same Dbuf state
We currently treat same slice mask as a same DBuf state and skip
updating the Dbuf slices, if we detect that.
This is wrong as if we have a multi to single pipe change or
vice versa, that would be treated as a same Dbuf state and thus
no changes required, so we don't get Mbus updated, causing issues.
Solution: check also mbus_join, in addition to slices mask.
Cc: Ville Syrjälä <email address hidden>
Reviewed-by: Uma Shankar <email address hidden>
Signed-off-by: Stanislav Lisovskiy <email address hidden>
Signed-off-by: Jani Nikula <email address hidden>
Link: https://patchwork.freedesktop<email address hidden>
d62686b...
by
Stanislav Lisovskiy <email address hidden>
drm/i915/adl_p: CDCLK crawl support for ADL
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
v2: - Added has_cdclk_crawl as a feature flag to
intel_device_info(Matt Roper)
- s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
(Matt Roper)
Cc: Mika Kahola <email address hidden>
Reviewed-by: Mika Kahola <email address hidden>
Signed-off-by: Stanislav Lisovskiy <email address hidden>
Signed-off-by: Gwan-gyeong Mun <email address hidden>
Signed-off-by: Jani Nikula <email address hidden>
Link: https://patchwork.freedesktop<email address hidden>
5131743...
by
Vandita Kulkarni <email address hidden>
drm/i915/dsc: Fix bigjoiner check in dsc_disable
This change takes care of resetting the dss_ctl registers
in case of dsc_disable, bigjoiner disable and also
uncompressed joiner disable.
17c1a4b...
by
=?utf-8?b?VmlsbGUgU3lyasOkbMOk?= <email address hidden>
drm/i915: Disable PSR around cdclk changes
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola <email address hidden>
Signed-off-by: Ville Syrjälä <email address hidden>
Signed-off-by: Gwan-gyeong Mun <email address hidden>
Reviewed-by: Mika Kahola <email address hidden>
Signed-off-by: José Roberto de Souza <email address hidden>
Link: https://patchwork.freedesktop<email address hidden>
234b402...
by
Gwan-gyeong Mun <email address hidden>
drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
v3: Address Jose's review comment.
- Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
- Move WA_1408330847 to intel_psr_disable_locked()
- If the PSR is paused by an explicit intel_psr_paused() call, make the
intel_psr_flush() not to activate PSR.
v4: Address Jose's review comment.
- In order to avoid the scenario of PSR is not active but there is a
scheduled psr->work, it changes the check routine of intel_psr_pause()
for PSR's enablement from "psr->active" to "psr->enable".
Cc: José Roberto de Souza <email address hidden>
Cc: Stanislav Lisovskiy <email address hidden>
Cc: Ville Syrjälä <email address hidden>
Signed-off-by: Gwan-gyeong Mun <email address hidden>
Signed-off-by: Matt Roper <email address hidden>
Reviewed-by: José Roberto de Souza <email address hidden>
Signed-off-by: José Roberto de Souza <email address hidden>
Link: https://patchwork.freedesktop<email address hidden>
31b77c7...
by
Tejas Upadhyay <email address hidden>
x86/gpu: add JasperLake to gen11 early quirks
Let's reserve JSL stolen memory for graphics.
JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.
This was missed in commit 24ea098b7c0d ("drm/i915/jsl: Split
EHL/JSL platform info and PCI ids")
V2:
- Added maintainer list in cc
- Added patch ref in commit message
V1:
- Added Cc: <email address hidden>
3f409e4...
by
=?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= <email address hidden>
drm/i915/display: Drop FIXME about turn off infoframes
intel_dp_set_infoframes() call in intel_ddi_post_disable_dp() will
take care to disable all enabled infoframes.
Cc: Ville Syrjälä <email address hidden>
Signed-off-by: José Roberto de Souza <email address hidden>
Reviewed-by: Radhakrishna Sripada <email address hidden>
Link: https://patchwork<email address hidden>
6d7a793...
by
=?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= <email address hidden>
drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled
When PSR is enabled it handles DP_SDP_VSC, changing revision and all
the other fields as necessary.
It can also enabled and disable this SDP as needed without a full
modeset.
So here masking DP_SDP_VSC bit when previous and future state PSR
enabled, it will still be checked when comparing the asked state
to what was programmed to hardware.
Cc: Gwan-gyeong Mun <email address hidden>
Cc: Radhakrishna Sripada <email address hidden>
Reported-by: Ville Syrjälä <email address hidden>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
Signed-off-by: José Roberto de Souza <email address hidden>
Reviewed-by: Gwan-gyeong Mun <email address hidden>
Link: https://patchwork<email address hidden>
9b2e49a...
by
=?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= <email address hidden>
drm/i915/display: Fix fastsets involving PSR
Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware
configuration read out") is not allowing fastsets to happen when PSR
states changes but PSR is a feature that can be enabled and disabled
during fastsets.
So here moving the PSR pipe conf checks to a block that is only
executed when checking if HW state matches with requested state, not
during the phase where it checks if fastset is possible or not.
There still a state mismatch not allowing fastsets between states
turning off or on PSR because of crtc_state->infoframes.enable
BIT(DP_SDP_VSC) but at least for now it will allow a fastset between
PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not
work with PSR2, but the remaning issue will be fixed in a future patch.
Cc: Gwan-gyeong Mun <email address hidden>
Cc: Radhakrishna Sripada <email address hidden>
Reported-by: Ville Syrjälä <email address hidden>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
Signed-off-by: José Roberto de Souza <email address hidden>
Reviewed-by: Gwan-gyeong Mun <email address hidden>
Link: https://patchwork<email address hidden>
