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1c046bc... by Jeff McGee <email address hidden> on 2015-04-04

drm/i915/bxt: Support BXT in SSEU device status dump

Modify the Gen9 SSEU device status logic to support Broxton.
Broxton reuses the Skylake power gate acknowledgment registers but
has at most 1 slice and 3 subslices. Broxton supports subslice
power gating within its single slice.

Signed-off-by: Jeff McGee <email address hidden>
Reviewed-by: Imre Deak <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

5d39525... by Jeff McGee <email address hidden> on 2015-04-04

drm/i915: Split-up SSEU device status by platform

Signed-off-by: Jeff McGee <email address hidden>
Reviewed-by: Imre Deak <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

dead16e... by Jeff McGee <email address hidden> on 2015-04-04

drm/i915/bxt: Determine BXT slice/subslice/EU info

Modify the Gen9 SSEU info initialization logic to support
Broxton. Broxton reuses the SKL fuse registers but has at most
1 slice and 6 EU per subslice.

Signed-off-by: Jeff McGee <email address hidden>
Reviewed-by: Imre Deak <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

9705ad8... by Jeff McGee <email address hidden> on 2015-04-04

drm/i915: Split SSEU init into functions by platform

Signed-off-by: Jeff McGee <email address hidden>
Reviewed-by: Imre Deak <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

3449ca8... by Vandana Kannan <email address hidden> on 2015-03-27

drm/i915/bxt: Increase DDI buf idle timeout

For BXT, DDI buf idle timeout delay needs to be increased to 16us.

Since this is a timeout value and we return as soon as the condition is
realized, no penalty incurred for other platforms.

v2:
- remove TIMEOUT macro used only at a single place (Daniel)

Suggested-by: Satheeshakrishna M <email address hidden>
Cc: Satheeshakrishna M <email address hidden>
Cc: Damien Lespiau <email address hidden>
Signed-off-by: Vandana Kannan <email address hidden>
Signed-off-by: Damien Lespiau <email address hidden> (v1)
Reviewed-by: Jani Nikula <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

6c74c87... by Nick Hoath <email address hidden> on 2015-03-20

drm/i915/bxt: Add Broxton steppings

Signed-off-by: Nick Hoath <email address hidden>
Reviewed-by: Imre Deak <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

cae0437... by Nick Hoath <email address hidden> on 2015-03-17

drm/i915/bxt: HardWare WorkAround ring initialisation for Broxton

Adds framework for Broxton HW WAs

Signed-off-by: Nick Hoath <email address hidden>
Signed-off-by: Imre Deak <email address hidden>
Reviewed-by: Nick Hoath <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

2a073f8... by Imre Deak <email address hidden> on 2015-03-27

drm/i915/bxt: map GTT as uncached

On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.

v2:
- add comment explaining how the problem with WC mapping manifests
  (Daniel)

Signed-off-by: Imre Deak <email address hidden>
Reviewed-by: Antti Koskipää <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

8232edb... by Damien Lespiau on 2015-03-17

drm/i915/bxt: Broxton raises the maximum number of planes to 4

Pipe A and b have 4 planes.

Signed-off-by: Damien Lespiau <email address hidden>
Reviewed-by: Antti Koskipää <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>

43d735a... by Damien Lespiau on 2015-03-17

drm/i915/bxt: Broxton DDB is 512 blocks

Signed-off-by: Damien Lespiau <email address hidden>
Reviewed-by: Antti Koskipää <email address hidden>
Signed-off-by: Daniel Vetter <email address hidden>