Initially, Intel mGbE was only able to configure the overclocking of 2.5
times clock rate to enable 2.5Gbps in the BIOS during boot time. Kernel
driver had no access to modify the clock rate for 1G/2.5G mode at runtime.
Now, this patch enables the runtime 1G/2.5G auto-negotiation support to
gets rid of the dependency on BIOS to change the 1G/2.5G clock rate.
This patch adds several new functions below:-
- intel_check_TSN_interface(): This new function reads FIA lane ownership
registers and common lane registers through IPC1 commands to know which
lane the mGbE port is assigned to.
- stmmac_mac_prepare(): To obtain the latest PHY interface from phylink
during initialization and call intel_config_serdes() to proceed with
SERDES configuration.
- intel_config_serdes(): To configure the SERDES based on the assigned
lane and latest PHY interface, it sends IPC1 command to the PMC through
PMC driver/API. The PMC acts as a proxy for R/W on behalf of the driver.
Signed-off-by: Tan, Tee Min <email address hidden>
Add cur_link_an_mode into phy_device struct for PHY drivers to
communicate the in-band AN mode setting with phylink framework.
As there is a mechanism in PHY drivers to switch the PHY interface
between SGMII and 2500BaseX according to link speed. In this case,
the in-band AN mode should be switching based on the PHY interface
as well, if the PHY interface has been changed/updated by PHY driver.
For e.g., disable in-band AN in 2500BaseX mode, or enable in-band AN
back for SGMII mode (10/100/1000Mbps).
Signed-off-by: Tan, Tee Min <email address hidden>
This commit introduces xpcs_sgmii_2500basex_features[] that combine
xpcs_sgmii_features[] and xpcs_2500basex_features[] for Intel mGbE
controller that desire to interchange the speed mode of
10/100/1000/2500Mbps at runtime.
Also, we introduce xpcs_config_aneg_c37_sgmii_2500basex() function
which is called by the xpcs_do_config() with the new AN mode:
DW_SGMII_2500BASEX, and this new function will proceed next-level
calling to perform C37 SGMII AN/2500BASEX configuration based on
the PHY interface updated by PHY driver.
Signed-off-by: Tan, Tee Min <email address hidden>
Add support to use IPC1 command allows host to access SoC registers
through PMC firmware that are otherwise inaccessible to the host due to
security policies.
Moved const struct char pmc_lpm_modes[] to core.c to solve
multiple definition.
Signed-off-by: Tan, Tee Min <email address hidden>
There is a possibility that the context descriptor still owned by the DMA
even the previous normal descriptor own bit is already cleared. Checking
the context descriptor readiness without delay might be not enough time
for the DMA to update the descriptor field, which causing failure in
getting HW Rx timestamp.
This patch introduces a 1us fsleep() in HW Rx timestamp checking loop
to give time for DMA to update/complete the context descriptor.
ptp4l Timestamp log without this patch:
-----------------------------------------------------------
$ echo 10000 > /sys/class/net/enp0s30f4/gro_flush_timeout
$ echo 10000 > /sys/class/net/enp0s30f4/napi_defer_hard_irqs
$ ptp4l -P2Hi enp0s30f4 --step_threshold=1 -m
ptp4l: selected /dev/ptp2 as PTP clock
ptp4l: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l: selected local clock 901210.fffe.b57df7 as best master
ptp4l: port 1: new foreign master 22bb22.fffe.bb22bb-1
ptp4l: selected best master clock 22bb22.fffe.bb22bb
ptp4l: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l: port 1: received SYNC without timestamp
ptp4l: rms 49 max 63 freq -9573 +/- 34 delay 71 +/- 1
ptp4l: rms 15 max 25 freq -9553 +/- 20 delay 72 +/- 0
ptp4l: port 1: received SYNC without timestamp
ptp4l: rms 9 max 18 freq -9540 +/- 11 delay 70 +/- 0
ptp4l: port 1: received PDELAY_REQ without timestamp
ptp4l: rms 16 max 29 freq -9519 +/- 12 delay 72 +/- 0
ptp4l: port 1: received PDELAY_REQ without timestamp
ptp4l: rms 9 max 18 freq -9527 +/- 12 delay 72 +/- 0
ptp4l: rms 5 max 9 freq -9530 +/- 7 delay 70 +/- 0
ptp4l: rms 11 max 20 freq -9530 +/- 16 delay 72 +/- 0
ptp4l: rms 5 max 11 freq -9530 +/- 7 delay 74 +/- 0
ptp4l: rms 6 max 9 freq -9522 +/- 7 delay 72 +/- 0
ptp4l: port 1: received PDELAY_REQ without timestamp
-----------------------------------------------------------
ptp4l Timestamp log with this patch:
-----------------------------------------------------------
$ echo 10000 > /sys/class/net/enp0s30f4/gro_flush_timeout
$ echo 10000 > /sys/class/net/enp0s30f4/napi_defer_hard_irqs
$ ptp4l -P2Hi enp0s30f4 --step_threshold=1 -m
ptp4l: selected /dev/ptp2 as PTP clock
ptp4l: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l: selected local clock 901210.fffe.b57df7 as best master
ptp4l: port 1: new foreign master 22bb22.fffe.bb22bb-1
ptp4l: selected best master clock 22bb22.fffe.bb22bb
ptp4l: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l: rms 30 max 45 freq -9400 +/- 23 delay 72 +/- 0
ptp4l: rms 7 max 16 freq -9414 +/- 10 delay 70 +/- 0
ptp4l: rms 6 max 9 freq -9422 +/- 6 delay 72 +/- 0
ptp4l: rms 13 max 20 freq -9436 +/- 13 delay 74 +/- 0
ptp4l: rms 12 max 27 freq -9446 +/- 11 delay 72 +/- 0
ptp4l: rms 9 max 12 freq -9453 +/- 6 delay 74 +/- 0
ptp4l: rms 9 max 15 freq -9438 +/- 11 delay 74 +/- 0
ptp4l: rms 10 max 16 freq -9435 +/- 12 delay 74 +/- 0
ptp4l: rms 8 max 18 freq -9428 +/- 8 delay 72 +/- 0
ptp4l: rms 8 max 18 freq -9423 +/- 8 delay 72 +/- 0
ptp4l: rms 9 max 16 freq -9431 +/- 12 delay 70 +/- 0
ptp4l: rms 9 max 18 freq -9441 +/- 9 delay 72 +/- 0
-----------------------------------------------------------
Fixes: ba1ffd74df74 ("stmmac: fix PTP support for GMAC4")
Cc: <email address hidden> # 5.4.x
Signed-off-by: Song Yoong Siang <email address hidden>
Signed-off-by: Tan Tee Min <email address hidden>
This reverts commit d4aeaed80b0ebb020fadf2073b23462928dbdc17.
This patch causes a regression issue on Elkhart Lake and Tiger Lake
when MaxLinear GPY115/211 PHYs are connected.
Issue is not seen when external PHYs from other vendors are used.
Until we have a root-cause from MaxLinear, temporary reverting this
patch to unblock EHL MR3 and ADL-S MR1.
Tested-by: Ling, Pei Lee <email address hidden>
Signed-off-by: Wong Vee Khee <email address hidden>
Disable is done in stmmac_init_eee() on the event of MAC link down.
Since setting enable/disable EEE via ethtool will eventually trigger
a MAC down, removing this redunctant call in stmmac_ethtool.c to avoid
calling xpcs_config_eee() twice.
Fixes: d4aeaed80b0e ("net: stmmac: trigger PCS to turn off on link down")
Signed-off-by: Wong Vee Khee <email address hidden>
When the PHY wakes up from suspend through WOL event, there is a need to
reconfigure the WOL if the WOL option still enabled. The main operation
is to clear the WOL event status. So that, subsequent WOL event can be
triggered properly.
This fix is needed especially for the PHY that operates in PHY_POLL mode
where there is no handler (such as interrupt handler) available to clear
the WOL event status.
Fixes: 611d779af7ca ("net: phy: fix MDIO bus PM PHY resuming")
Signed-off-by: Mohammad Athari Bin Ismail <email address hidden>
Signed-off-by: Ling Pei Lee <email address hidden>
