Merge ~paelzer/ubuntu/+source/qemu:fix-1832622-ppc-spectre-disco into ubuntu/+source/qemu:ubuntu/disco-devel

Proposed by Christian Ehrhardt  on 2019-06-13
Status: Merged
Approved by: Christian Ehrhardt  on 2019-06-26
Approved revision: f5ccfa81ec89a89e7f7f3f7d5fe41a4f02b32c38
Merge reported by: Christian Ehrhardt 
Merged at revision: fac417ed7d848ba91926c7421c8c4621c32fccab
Proposed branch: ~paelzer/ubuntu/+source/qemu:fix-1832622-ppc-spectre-disco
Merge into: ubuntu/+source/qemu:ubuntu/disco-devel
Diff against target: 412 lines (+384/-0)
4 files modified
debian/changelog (+7/-0)
debian/patches/series (+2/-0)
debian/patches/ubuntu/lp-1832622-0002-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch (+159/-0)
debian/patches/ubuntu/lp-1832622-0004-target-ppc-spapr-Add-SPAPR_CAP_CCF_ASSIST.patch (+216/-0)
Reviewer Review Type Date Requested Status
Rafael David Tinoco 2019-06-13 Approve on 2019-06-26
Canonical Server packageset reviewers 2019-06-13 Pending
Ubuntu Server Dev import team 2019-06-13 Pending
Review via email: mp+368749@code.launchpad.net
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Christian Ehrhardt  (paelzer) wrote :

Related test PPA at [1].
This started with the provided backports for 2.11 and then one by one taking away changes no more needed on the backports. The commits that "undo some backports" are intentionally not squashed so one can see what changes in between the versions and what is the same.

[1]: https://launchpad.net/~paelzer/+archive/ubuntu/bug-1832622-qemu-spectre-ppc

Paride Legovini (legovini) wrote :

Looks good from a formal point view; the packages in the PPA seem to be working as expected, however I don't think I can test the specific fix.

Rafael David Tinoco (rafaeldtinoco) wrote :

I did a full bionic review into eoan merge request:

https://code.launchpad.net/~paelzer/ubuntu/+source/qemu/+git/qemu/+merge/368748/comments/964720

All others are a subset of that, I did a quick look and compilation tests only.

+1 from me.

review: Approve
Christian Ehrhardt  (paelzer) wrote :

This migrated, closing forgotten MP

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1diff --git a/debian/changelog b/debian/changelog
2index bb2e787..4006062 100644
3--- a/debian/changelog
4+++ b/debian/changelog
5@@ -1,3 +1,10 @@
6+qemu (1:3.1+dfsg-2ubuntu3.4) disco; urgency=medium
7+
8+ * d/p/ubuntu/lp-1832622-*: count cache flush Spectre v2 mitigation for ppc64
9+ (LP: #1832622)
10+
11+ -- Christian Ehrhardt <christian.ehrhardt@canonical.com> Thu, 13 Jun 2019 08:40:55 +0200
12+
13 qemu (1:3.1+dfsg-2ubuntu3.3) disco; urgency=medium
14
15 [ Christian Ehrhardt ]
16diff --git a/debian/patches/series b/debian/patches/series
17index f8a7ef6..bbbd749 100644
18--- a/debian/patches/series
19+++ b/debian/patches/series
20@@ -31,3 +31,5 @@ ubuntu/lp1828495-0012-arch-capabilities-migratable.patch
21 ubuntu/lp1828495-0014-remove-cpuid-pconfig.patch
22 ubuntu/lp1828495-0015-remove-cpuid-intel_pt.patch
23 ubuntu/lp1828495-0016-no-ospke-on-some.patch
24+ubuntu/lp-1832622-0002-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch
25+ubuntu/lp-1832622-0004-target-ppc-spapr-Add-SPAPR_CAP_CCF_ASSIST.patch
26diff --git a/debian/patches/ubuntu/lp-1832622-0002-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch b/debian/patches/ubuntu/lp-1832622-0002-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch
27new file mode 100644
28index 0000000..58b3e88
29--- /dev/null
30+++ b/debian/patches/ubuntu/lp-1832622-0002-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch
31@@ -0,0 +1,159 @@
32+From 399b2896d4948a1ec0278d896ea3a561df768d64 Mon Sep 17 00:00:00 2001
33+From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
34+Date: Fri, 1 Mar 2019 14:19:11 +1100
35+Subject: [PATCH 1/2] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS
36+
37+The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
38+for mitigations for indirect branch speculation. Currently the available
39+values are broken (default), fixed-ibs (fixed by serialising indirect
40+branches) and fixed-ccd (fixed by diabling the count cache).
41+
42+Introduce a new value for this capability denoted workaround, meaning that
43+software can work around the issue by flushing the count cache on
44+context switch. This option is available if the hypervisor sets the
45+H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from
46+the KVM_PPC_GET_CPU_CHAR ioctl.
47+
48+Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
49+Message-Id: <20190301031912.28809-1-sjitindarsingh@gmail.com>
50+Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
51+
52+Origin: upstream, https://git.qemu.org/?p=qemu.git;a=commit;h=399b2896d4948a1ec0278d896ea3a561df768d64
53+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1832622
54+Last-Update: 2019-06-13
55+
56+---
57+ hw/ppc/spapr_caps.c | 21 ++++++++++-----------
58+ hw/ppc/spapr_hcall.c | 5 +++++
59+ include/hw/ppc/spapr.h | 7 +++++++
60+ target/ppc/kvm.c | 8 +++++++-
61+ 4 files changed, 29 insertions(+), 12 deletions(-)
62+
63+diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
64+index faab472d06..ca35b5153d 100644
65+--- a/hw/ppc/spapr_caps.c
66++++ b/hw/ppc/spapr_caps.c
67+@@ -276,11 +276,13 @@ static void cap_safe_bounds_check_apply(sPAPRMachineState *spapr, uint8_t val,
68+ }
69+
70+ sPAPRCapPossible cap_ibs_possible = {
71+- .num = 4,
72++ .num = 5,
73+ /* Note workaround only maintained for compatibility */
74+- .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd"},
75+- .help = "broken - no protection, fixed-ibs - indirect branch serialisation,"
76+- " fixed-ccd - cache count disabled",
77++ .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"},
78++ .help = "broken - no protection, workaround - count cache flush"
79++ ", fixed-ibs - indirect branch serialisation,"
80++ " fixed-ccd - cache count disabled,"
81++ " fixed-na - fixed in hardware (no longer applicable)",
82+ };
83+
84+ static void cap_safe_indirect_branch_apply(sPAPRMachineState *spapr,
85+@@ -288,15 +290,11 @@ static void cap_safe_indirect_branch_apply(sPAPRMachineState *spapr,
86+ {
87+ uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
88+
89+- if (val == SPAPR_CAP_WORKAROUND) { /* Can only be Broken or Fixed */
90+- error_setg(errp,
91+-"Requested safe indirect branch capability level \"workaround\" not valid, try cap-ibs=%s",
92+- cap_ibs_possible.vals[kvm_val]);
93+- } else if (tcg_enabled() && val) {
94++ if (tcg_enabled() && val) {
95+ /* TODO - for now only allow broken for TCG */
96+ error_setg(errp,
97+ "Requested safe indirect branch capability level not supported by tcg, try a different value for cap-ibs");
98+- } else if (kvm_enabled() && val && (val != kvm_val)) {
99++ } else if (kvm_enabled() && (val > kvm_val)) {
100+ error_setg(errp,
101+ "Requested safe indirect branch capability level not supported by kvm, try cap-ibs=%s",
102+ cap_ibs_possible.vals[kvm_val]);
103+@@ -494,7 +492,8 @@ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
104+ [SPAPR_CAP_IBS] = {
105+ .name = "ibs",
106+ .description =
107+- "Indirect Branch Speculation (broken, fixed-ibs, fixed-ccd)",
108++ "Indirect Branch Speculation (broken, workaround, fixed-ibs,"
109++ "fixed-ccd, fixed-na)",
110+ .index = SPAPR_CAP_IBS,
111+ .get = spapr_cap_get_string,
112+ .set = spapr_cap_set_string,
113+diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
114+index 476bad6271..4aa8036fc0 100644
115+--- a/hw/ppc/spapr_hcall.c
116++++ b/hw/ppc/spapr_hcall.c
117+@@ -1723,12 +1723,17 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
118+ }
119+
120+ switch (safe_indirect_branch) {
121++ case SPAPR_CAP_FIXED_NA:
122++ break;
123+ case SPAPR_CAP_FIXED_CCD:
124+ characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
125+ break;
126+ case SPAPR_CAP_FIXED_IBS:
127+ characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
128+ break;
129++ case SPAPR_CAP_WORKAROUND:
130++ behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
131++ break;
132+ default: /* broken */
133+ assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
134+ break;
135+diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
136+index 8efc5e0779..a7f3b1bfdd 100644
137+--- a/include/hw/ppc/spapr.h
138++++ b/include/hw/ppc/spapr.h
139+@@ -85,12 +85,17 @@ typedef enum {
140+ /* Bool Caps */
141+ #define SPAPR_CAP_OFF 0x00
142+ #define SPAPR_CAP_ON 0x01
143++
144+ /* Custom Caps */
145++
146++/* Generic */
147+ #define SPAPR_CAP_BROKEN 0x00
148+ #define SPAPR_CAP_WORKAROUND 0x01
149+ #define SPAPR_CAP_FIXED 0x02
150++/* SPAPR_CAP_IBS (cap-ibs) */
151+ #define SPAPR_CAP_FIXED_IBS 0x02
152+ #define SPAPR_CAP_FIXED_CCD 0x03
153++#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
154+
155+ typedef struct sPAPRCapabilities sPAPRCapabilities;
156+ struct sPAPRCapabilities {
157+@@ -339,9 +344,11 @@ struct sPAPRMachineState {
158+ #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
159+ #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
160+ #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
161++#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
162+ #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
163+ #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
164+ #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
165++#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
166+
167+ /* Each control block has to be on a 4K boundary */
168+ #define H_CB_ALIGNMENT 4096
169+diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
170+index f0f5bf9391..4d46314276 100644
171+--- a/target/ppc/kvm.c
172++++ b/target/ppc/kvm.c
173+@@ -2392,7 +2392,13 @@ static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
174+
175+ static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
176+ {
177+- if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
178++ if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
179++ (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
180++ (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
181++ return SPAPR_CAP_FIXED_NA;
182++ } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
183++ return SPAPR_CAP_WORKAROUND;
184++ } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
185+ return SPAPR_CAP_FIXED_CCD;
186+ } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
187+ return SPAPR_CAP_FIXED_IBS;
188+--
189+2.21.0
190+
191diff --git a/debian/patches/ubuntu/lp-1832622-0004-target-ppc-spapr-Add-SPAPR_CAP_CCF_ASSIST.patch b/debian/patches/ubuntu/lp-1832622-0004-target-ppc-spapr-Add-SPAPR_CAP_CCF_ASSIST.patch
192new file mode 100644
193index 0000000..3bc9541
194--- /dev/null
195+++ b/debian/patches/ubuntu/lp-1832622-0004-target-ppc-spapr-Add-SPAPR_CAP_CCF_ASSIST.patch
196@@ -0,0 +1,216 @@
197+From 77012c6029ae15328f04ddcb713f459cdacffef9 Mon Sep 17 00:00:00 2001
198+From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
199+Date: Fri, 1 Mar 2019 14:19:12 +1100
200+Subject: [PATCH] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST
201+
202+Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
203+the requirement for a hw-assisted version of the count cache flush
204+workaround.
205+
206+The count cache flush workaround is a software workaround which can be
207+used to flush the count cache on context switch. Some revisions of
208+hardware may have a hardware accelerated flush, in which case the
209+software flush can be shortened. This cap is used to set the
210+availability of such hardware acceleration for the count cache flush
211+routine.
212+
213+The availability of such hardware acceleration is indicated by the
214+H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics
215+returned from the KVM_PPC_GET_CPU_CHAR ioctl.
216+
217+Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
218+Message-Id: <20190301031912.28809-2-sjitindarsingh@gmail.com>
219+[dwg: Small style fixes]
220+
221+Origin: backport, https://git.qemu.org/?p=qemu.git;a=commit;h=8ff43ee404d3e295839d1fd4e9e6571ca7a62a66
222+Author: Christian Ehrhardt <christian.ehrhardt@canonical.com>
223+Original-Author: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
224+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1832622
225+Last-Update: 2019-06-13
226+
227+---
228+ hw/ppc/spapr.c | 2 ++
229+ hw/ppc/spapr_caps.c | 25 +++++++++++++++++++++++++
230+ hw/ppc/spapr_hcall.c | 5 +++++
231+ include/hw/ppc/spapr.h | 5 ++++-
232+ target/ppc/kvm.c | 16 ++++++++++++++++
233+ target/ppc/kvm_ppc.h | 6 ++++++
234+ 6 files changed, 58 insertions(+), 1 deletion(-)
235+
236+--- a/hw/ppc/spapr.c
237++++ b/hw/ppc/spapr.c
238+@@ -1939,6 +1939,7 @@ static const VMStateDescription vmstate_
239+ &vmstate_spapr_cap_ibs,
240+ &vmstate_spapr_irq_map,
241+ &vmstate_spapr_cap_nested_kvm_hv,
242++ &vmstate_spapr_cap_ccf_assist,
243+ NULL
244+ }
245+ };
246+@@ -3904,6 +3905,7 @@ static void spapr_machine_class_init(Obj
247+ smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
248+ smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
249+ smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
250++ smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
251+ spapr_caps_add_properties(smc, &error_abort);
252+ smc->irq = &spapr_irq_xics;
253+ }
254+--- a/hw/ppc/spapr_caps.c
255++++ b/hw/ppc/spapr_caps.c
256+@@ -388,6 +388,21 @@ static void cap_nested_kvm_hv_apply(sPAP
257+ }
258+ }
259+
260++static void cap_ccf_assist_apply(sPAPRMachineState *spapr, uint8_t val,
261++ Error **errp)
262++{
263++ uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
264++
265++ if (tcg_enabled() && val) {
266++ /* TODO - for now only allow broken for TCG */
267++ error_setg(errp,
268++"Requested count cache flush assist capability level not supported by tcg, try cap-ccf-assist=off");
269++ } else if (kvm_enabled() && (val > kvm_val)) {
270++ error_setg(errp,
271++"Requested count cache flush assist capability level not supported by kvm, try cap-ccf-assist=off");
272++ }
273++}
274++
275+ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
276+ [SPAPR_CAP_HTM] = {
277+ .name = "htm",
278+@@ -467,6 +482,15 @@ sPAPRCapabilityInfo capability_table[SPA
279+ .type = "bool",
280+ .apply = cap_nested_kvm_hv_apply,
281+ },
282++ [SPAPR_CAP_CCF_ASSIST] = {
283++ .name = "ccf-assist",
284++ .description = "Count Cache Flush Assist via HW Instruction",
285++ .index = SPAPR_CAP_CCF_ASSIST,
286++ .get = spapr_cap_get_bool,
287++ .set = spapr_cap_set_bool,
288++ .type = "bool",
289++ .apply = cap_ccf_assist_apply,
290++ },
291+ };
292+
293+ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
294+@@ -595,6 +619,7 @@ SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC
295+ SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
296+ SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
297+ SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
298++SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
299+
300+ void spapr_caps_init(sPAPRMachineState *spapr)
301+ {
302+--- a/hw/ppc/spapr_hcall.c
303++++ b/hw/ppc/spapr_hcall.c
304+@@ -1674,6 +1674,8 @@ static target_ulong h_get_cpu_characteri
305+ uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
306+ uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
307+ uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
308++ uint8_t count_cache_flush_assist = spapr_get_cap(spapr,
309++ SPAPR_CAP_CCF_ASSIST);
310+
311+ switch (safe_cache) {
312+ case SPAPR_CAP_WORKAROUND:
313+@@ -1714,6 +1716,9 @@ static target_ulong h_get_cpu_characteri
314+ break;
315+ case SPAPR_CAP_WORKAROUND:
316+ behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
317++ if (count_cache_flush_assist) {
318++ characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
319++ }
320+ break;
321+ default: /* broken */
322+ assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
323+--- a/include/hw/ppc/spapr.h
324++++ b/include/hw/ppc/spapr.h
325+@@ -72,8 +72,10 @@ typedef enum {
326+ #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
327+ /* Nested KVM-HV */
328+ #define SPAPR_CAP_NESTED_KVM_HV 0x07
329++/* Count Cache Flush Assist HW Instruction */
330++#define SPAPR_CAP_CCF_ASSIST 0x08
331+ /* Num Caps */
332+-#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1)
333++#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1)
334+
335+ /*
336+ * Capability Values
337+@@ -801,6 +803,7 @@ extern const VMStateDescription vmstate_
338+ extern const VMStateDescription vmstate_spapr_cap_sbbc;
339+ extern const VMStateDescription vmstate_spapr_cap_ibs;
340+ extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
341++extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
342+
343+ static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
344+ {
345+--- a/target/ppc/kvm.c
346++++ b/target/ppc/kvm.c
347+@@ -91,6 +91,7 @@ static int cap_ppc_pvr_compat;
348+ static int cap_ppc_safe_cache;
349+ static int cap_ppc_safe_bounds_check;
350+ static int cap_ppc_safe_indirect_branch;
351++static int cap_ppc_count_cache_flush_assist;
352+ static int cap_ppc_nested_kvm_hv;
353+
354+ static uint32_t debug_inst_opcode;
355+@@ -2391,6 +2392,14 @@ static int parse_cap_ppc_safe_indirect_b
356+ return 0;
357+ }
358+
359++static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
360++{
361++ if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
362++ return 1;
363++ }
364++ return 0;
365++}
366++
367+ static void kvmppc_get_cpu_characteristics(KVMState *s)
368+ {
369+ struct kvm_ppc_cpu_char c;
370+@@ -2413,6 +2422,8 @@ static void kvmppc_get_cpu_characteristi
371+ cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
372+ cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
373+ cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
374++ cap_ppc_count_cache_flush_assist =
375++ parse_cap_ppc_count_cache_flush_assist(c);
376+ }
377+
378+ int kvmppc_get_cap_safe_cache(void)
379+@@ -2430,6 +2441,11 @@ int kvmppc_get_cap_safe_indirect_branch(
380+ return cap_ppc_safe_indirect_branch;
381+ }
382+
383++int kvmppc_get_cap_count_cache_flush_assist(void)
384++{
385++ return cap_ppc_count_cache_flush_assist;
386++}
387++
388+ bool kvmppc_has_cap_nested_kvm_hv(void)
389+ {
390+ return !!cap_ppc_nested_kvm_hv;
391+--- a/target/ppc/kvm_ppc.h
392++++ b/target/ppc/kvm_ppc.h
393+@@ -62,6 +62,7 @@ bool kvmppc_has_cap_mmu_hash_v3(void);
394+ int kvmppc_get_cap_safe_cache(void);
395+ int kvmppc_get_cap_safe_bounds_check(void);
396+ int kvmppc_get_cap_safe_indirect_branch(void);
397++int kvmppc_get_cap_count_cache_flush_assist(void);
398+ bool kvmppc_has_cap_nested_kvm_hv(void);
399+ int kvmppc_set_cap_nested_kvm_hv(int enable);
400+ int kvmppc_enable_hwrng(void);
401+@@ -321,6 +322,11 @@ static inline int kvmppc_get_cap_safe_in
402+ {
403+ return 0;
404+ }
405++
406++static inline int kvmppc_get_cap_count_cache_flush_assist(void)
407++{
408++ return 0;
409++}
410+
411+ static inline bool kvmppc_has_cap_nested_kvm_hv(void)
412+ {

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