Linaro GCC

Merge lp:~michaelh1/gcc-linaro/vdup-immediates into lp:gcc-linaro/4.7

  1. vdup-immediates
  2. Merge into 4.7
Proposed by Michael Hope
Status: Merged
Approved by: Ulrich Weigand
Approved revision: no longer in the source branch.
Merge reported by: Michael Hope
Merged at revision: not available
Proposed branch: lp:~michaelh1/gcc-linaro/vdup-immediates
Merge into: lp:gcc-linaro/4.7
To merge this branch: bzr merge lp:~michaelh1/gcc-linaro/vdup-immediates
Reviewer Review Type Date Requested Status
Linaro Toolchain Developers Pending
Review via email: mp+115641@code.launchpad.net

Description of the change

Backport Julian's vdup builtin improvements. Causes the immediate version to be used instead of an immediate load/register vdup.

  2012-05-04 Michael Hope <email address hidden>

        Backport from mainline r189611:

        gcc/
        2012-07-18 Jie Zhang <email address hidden>
            Julian Brown <email address hidden>

        * config/arm/arm.c (arm_rtx_costs_1): Adjust cost for
        CONST_VECTOR.
        (arm_size_rtx_costs): Likewise.
        (neon_valid_immediate): Add a case for double 0.0.

        gcc/testsuite/
        2012-07-18 Jie Zhang <email address hidden>
            Julian Brown <email address hidden>

        * gcc.target/arm/neon-vdup-1.c: New test case.
        * gcc.target/arm/neon-vdup-2.c: New test case.
        * gcc.target/arm/neon-vdup-3.c: New test case.
        * gcc.target/arm/neon-vdup-4.c: New test case.
        * gcc.target/arm/neon-vdup-5.c: New test case.
        * gcc.target/arm/neon-vdup-6.c: New test case.
        * gcc.target/arm/neon-vdup-7.c: New test case.
        * gcc.target/arm/neon-vdup-8.c: New test case.
        * gcc.target/arm/neon-vdup-9.c: New test case.
        * gcc.target/arm/neon-vdup-10.c: New test case.
        * gcc.target/arm/neon-vdup-11.c: New test case.
        * gcc.target/arm/neon-vdup-12.c: New test case.
        * gcc.target/arm/neon-vdup-13.c: New test case.
        * gcc.target/arm/neon-vdup-14.c: New test case.
        * gcc.target/arm/neon-vdup-15.c: New test case.
        * gcc.target/arm/neon-vdup-16.c: New test case.
        * gcc.target/arm/neon-vdup-17.c: New test case.
        * gcc.target/arm/neon-vdup-18.c: New test case.
        * gcc.target/arm/neon-vdup-19.c: New test case.
        * gcc.target/arm/neon-combine-sub-abs-into-vabd.c: Make intrinsic
        arguments non-constant.

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Revision history for this message
Michael Hope (michaelh1) wrote :

cbuild has taken a snapshot of this branch at r115005 and queued it for build.

The diff against the ancestor r115004 is available at:
 http://builds.linaro.org/toolchain/snapshots/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates.diff

and will be built on the following builders:
 a9-builder a9hf-builder armv5-builder i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates
cbuild-ancestor: lp:gcc-linaro+bzr115004
cbuild-state: check

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on x86_64-precise-cbuild348-oort1-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/x86_64-precise-cbuild348-oort1-x86_64r1

The testsuite results are the same as the branch point lp:gcc-linaro+bzr115004

The full diff is at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/x86_64-precise-cbuild348-oort1-x86_64r1/testsuite-diff.txt

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/x86_64-precise-cbuild348-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-precise-cbuild348-oort1-x86_64r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :

cbuild successfully built this on i686-precise-cbuild348-oort6-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/i686-precise-cbuild348-oort6-i686r1

The testsuite results are the same as the branch point lp:gcc-linaro+bzr115004

The full diff is at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/i686-precise-cbuild348-oort6-i686r1/testsuite-diff.txt

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/i686-precise-cbuild348-oort6-i686r1/gcc-testsuite.txt

cbuild-checked: i686-precise-cbuild348-oort6-i686r1

Revision history for this message
Linaro Toolchain Builder (cbuild) wrote :
Download full text (3.9 KiB)

cbuild successfully built this on armv7l-precise-cbuild348-ursa2-cortexa9hfr1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/armv7l-precise-cbuild348-ursa2-cortexa9hfr1

+PASS: gcc.target/arm/neon-vdup-1.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-1.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #0.0([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-10.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-10.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #3992977407([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-11.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-11.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-12.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-12.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-13.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-13.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #65517([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-14.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-14.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #60927([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-15.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-15.c scan-assembler vmov.i8[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-16.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-16.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4863([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-17.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-17.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1245183([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-18.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-18.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4294962432([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-19.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-19.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4293722112([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-2.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-2.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #1.25e-1([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-3.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-3.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-4.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-4.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-5.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-5.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1179648([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-6.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-6.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #301989888([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-7.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-7.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4294967277([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/ar...

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Linaro Toolchain Builder (cbuild) wrote :
Download full text (3.9 KiB)

cbuild successfully built this on armv7l-natty-cbuild348-tcpanda06-armv5r2.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/armv7l-natty-cbuild348-tcpanda06-armv5r2

+PASS: gcc.target/arm/neon-vdup-1.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-1.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #0.0([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-10.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-10.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #3992977407([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-11.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-11.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-12.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-12.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-13.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-13.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #65517([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-14.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-14.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #60927([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-15.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-15.c scan-assembler vmov.i8[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-16.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-16.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4863([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-17.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-17.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1245183([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-18.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-18.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4294962432([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-19.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-19.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4293722112([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-2.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-2.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #1.25e-1([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-3.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-3.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-4.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-4.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-5.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-5.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1179648([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-6.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-6.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #301989888([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-7.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-7.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4294967277([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon...

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Linaro Toolchain Builder (cbuild) wrote :
Download full text (4.1 KiB)

cbuild successfully built this on armv7l-natty-cbuild348-tcpanda03-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115005~michaelh1~vdup-immediates/logs/armv7l-natty-cbuild348-tcpanda03-cortexa9r1

-FAIL: g++.dg/cdce3.C -std=gnu++11 execution test
+PASS: g++.dg/cdce3.C -std=gnu++11 execution test
-FAIL: g++.dg/cdce3.C -std=gnu++98 execution test
+PASS: g++.dg/cdce3.C -std=gnu++98 execution test
+PASS: gcc.target/arm/neon-vdup-1.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-1.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #0.0([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-10.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-10.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #3992977407([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-11.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-11.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-12.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-12.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-13.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-13.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #65517([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-14.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-14.c scan-assembler vmov.i16[ \t]+[qQ][0-9]+, #60927([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-15.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-15.c scan-assembler vmov.i8[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-16.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-16.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4863([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-17.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-17.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1245183([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-18.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-18.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4294962432([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-19.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-19.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4293722112([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-2.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-2.c scan-assembler vmov.f32[ \t]+[qQ][0-9]+, #1.25e-1([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-3.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-3.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #18([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-4.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-4.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #4608([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-5.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-5.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #1179648([ ]+@[a-zA-Z0-9 ]+)?\n
+PASS: gcc.target/arm/neon-vdup-6.c (test for excess errors)
+PASS: gcc.target/arm/neon-vdup-6.c scan-assembler vmov.i32[ \t]+[qQ][0-9]+, #301989888([ ]+@[a-zA-Z0-9...

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Ulrich Weigand (uweigand) wrote :

This is OK.

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