/** @file
*  Header defining Versatile Express constants (Base addresses, sizes, flags)
*
*  Copyright (c) 2012, ARM Limited. All rights reserved.
*
*  This program and the accompanying materials
*  are licensed and made available under the terms and conditions of the BSD License
*  which accompanies this distribution.  The full text of the license may be found at
*  http://opensource.org/licenses/bsd-license.php
*
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/

#ifndef __ARM_VEXPRESS_H__
#define __ARM_VEXPRESS_H__

#include <VExpressMotherBoard.h>

/***********************************************************************************
// Platform Memory Map
************************************************************************************/

// Motherboard Peripheral and On-chip peripheral
#define ARM_VE_BOARD_PERIPH_BASE              0x1C010000

// Secure NOR Flash
#define ARM_VE_SEC_NOR0_BASE                  0x00000000
#define ARM_VE_SEC_NOR0_SZ                    SIZE_64MB

// Secure RAM
#define ARM_VE_SEC_RAM0_BASE                  0x04000000
#define ARM_VE_SEC_RAM0_SZ                    SIZE_64MB

// NOR Flash 0
#define ARM_VE_SMB_NOR0_BASE                  0x08000000
#define ARM_VE_SMB_NOR0_SZ                    SIZE_64MB
// NOR Flash 1
#define ARM_VE_SMB_NOR1_BASE                  0x0C000000
#define ARM_VE_SMB_NOR1_SZ                    SIZE_64MB

// SRAM
#define ARM_VE_SMB_SRAM_BASE                  0x14000000
#define ARM_VE_SMB_SRAM_SZ                    SIZE_32MB

// USB, Ethernet, VRAM
#define ARM_VE_SMB_PERIPH_BASE                0x18000000
#define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_32MB + SIZE_16MB)
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE      ARM_VE_SMB_PERIPH_BASE

// On-Chip non-secure ROM
#define ARM_VE_TC2_NON_SECURE_ROM_BASE        0x1F000000
#define ARM_VE_TC2_NON_SECURE_ROM_SZ          SIZE_16MB

// On-Chip Peripherals
#define ARM_VE_ONCHIP_PERIPH_BASE             0x20000000
#define ARM_VE_ONCHIP_PERIPH_SZ               0x10000000

// On-Chip non-secure SRAM
#define ARM_VE_TC2_NON_SECURE_SRAM_BASE       0x2E000000
#define ARM_VE_TC2_NON_SECURE_SRAM_SZ         SIZE_64KB

// Allocate a section for the VRAM (Video RAM)
// If 0 then allow random memory allocation
#define LCD_VRAM_CORE_TILE_BASE               0

// Define SEC phase sync point
#define ARM_SEC_EVENT_BOOT_IMAGE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)

/***********************************************************************************
   Core Tile memory-mapped Peripherals
************************************************************************************/

// PL354 Static Memory Controller Base
#define ARM_VE_SMC_CTRL_BASE                    0x7FFD0000

#endif
