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Last commit made on 2024-06-10
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d0fbf9e...

Ensure 'make check' works after message added by abd4c49ee665.

3632c95...

Fix gcc warnings.

934ab54...

Add additional examples of Verilog co-simulation and share the Verilog
source and large parts of the example circuits between Verilator and
Icarus Verilog. Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.

75b33e4...

Add a utility function to the d_cosim code model to open dynamic
libraries. It automatically tries adding standard file extensions,
so that model lines for d_cosim can be the same for all OSs.

33b46b1...

Add support for including Verilog simulation within an instance
of the d_cosim codemodel, using libvvp, the simulation runtime of
Icarus Verilog. This complements the existing method using Verilator.
The new source code is built into two binary shared libraries,
ivlng.so (or .DLL) and ivlng.vpi that are loaded during simulation.

c1effdb...

Add support for Verilator's --timing option, allowing use of delays
in Verilog source code. Also add two parameters to d_cosim:
sim_args is used to pass string arguments to a Verilator simulation;
and lib_args is for future use. In vlnggen, also check for two causes
of failure: a verilator error may lead to creation of interfering header
files; and misleading instances of verilated_shim.cpp can cause an obscure
failure (reported by Diarmuid Collins).
Use a generic name for the generated DLL in MSVC.CMD.

2b1955d...

Allow trailing null connections to be omitted from XSPICE device
lines. Also tidy some code,

6bb1e86...

Changes to d_cosim to work with initial support for Icarus Verilog.
Fully resolve symbols on loading and tolerate attempts to set
output in the past.

059e2b2... by Holger Vogt

Add function check_for_nodes to
check if there are enough tokens in an instance line.

9774a64... by Holger Vogt

Bail out when the instance line is not complete.
Moving on does typically not make any sense.