The Cannon Lake Windows GPIO driver always exposes 32 pins per "bank"
regardless of whether the hardware actually has that many pins in a pad
group. This means that there are gaps in the GPIO number space even if
such gaps do not exist in the real hardware. To make things worse the
BIOS is also using the same scheme, so for example on Cannon Lake-LP
vGPIO 39 (vSD3_CD_B) the ACPI GpioInt resource has number 231 instead of
the expected 180 (which would be the hardware number).
To make SD card detection and other GPIOs working properly in Linux we
align the pinctrl-cannonlake GPIO numbering to follow the Windows GPIO
driver numbering taking advantage of the gpio_base field introduced in
the previous patch.
Signed-off-by: Mika Westerberg <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Signed-off-by: Linus Walleij <email address hidden>
(cherry picked from commit cb5fda413e1d4a857bf4fd0bc92e9de0f1ff9e9d)
Signed-off-by: Seth Forshee <email address hidden>
3b59d70...
by
Mika Westerberg <email address hidden>
pinctrl: intel: Allow custom GPIO base for pad groups
Currently we always have direct mapping between GPIO numbers and the
hardware pin numbers. However, there are cases where that's not the case
anymore (more about this in the next patch). Instead we need to be able
to specify custom GPIO base for certain pad groups.
To support this, add a new field (gpio_base) to the pad group structure
and update the core Intel pinctrl driver to handle this accordingly.
Passing 0 as gpio_base will use direct mapping so the existing drivers
do not need to be modified. Passing -1 excludes the whole pad group from
having GPIO mapping.
Signed-off-by: Mika Westerberg <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Signed-off-by: Linus Walleij <email address hidden>
(cherry picked from commit a60eac3239f01838bdd34eaac8c486c4c6e84551)
Signed-off-by: Seth Forshee <email address hidden>
85ef722...
by
Mika Westerberg <email address hidden>
gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation
We added acpi_gpiochip_pin_to_gpio_offset() because there was a need to
translate from ACPI GpioIo/GpioInt number to Linux GPIO number in the
Cherryview pinctrl driver. This translation is necessary because
Cherryview has gaps in the pin list and the driver used continuous GPIO
number space in Linux side as follows:
created GPIO range 0->7 ==> INT33FF:03 PIN 0->7
created GPIO range 8->19 ==> INT33FF:03 PIN 15->26
created GPIO range 20->25 ==> INT33FF:03 PIN 30->35
created GPIO range 26->33 ==> INT33FF:03 PIN 45->52
created GPIO range 34->43 ==> INT33FF:03 PIN 60->69
created GPIO range 44->54 ==> INT33FF:03 PIN 75->85
For example when ACPI GpioInt resource refers to GPIO 81 (SDMMC3_CD_B)
we translate from pin 81 to the corresponding Linux GPIO number, which
is 50. This number is then used when the GPIO is accessed through gpiolib.
It turns out, this is not necessary at all. We can just pass 1:1 mapping
between Linux GPIO numbers and pin numbers (including gaps) and the
pinctrl core handles all the details automatically:
created GPIO range 0->7 ==> INT33FF:03 PIN 0->7
created GPIO range 15->26 ==> INT33FF:03 PIN 15->26
created GPIO range 30->35 ==> INT33FF:03 PIN 30->35
created GPIO range 45->52 ==> INT33FF:03 PIN 45->52
created GPIO range 60->69 ==> INT33FF:03 PIN 60->69
created GPIO range 75->85 ==> INT33FF:03 PIN 75->85
Here GPIO 81 is exactly same than the hardware pin 81 (SDMMC3_CD_B).
As an added bonus this simplifies both the ACPI GPIO core code and the
Cherryview pinctrl driver.
Signed-off-by: Mika Westerberg <email address hidden>
Acked-by: Rafael J. Wysocki <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Signed-off-by: Linus Walleij <email address hidden>
(cherry picked from commit 03c4749dd6c7ff948a0ce59a44a1b97c015353c2)
Signed-off-by: Seth Forshee <email address hidden>
xHCI compatible USB host controllers(i.e. super-speed USB3 controllers)
can be implemented with the Debug Capability(DbC). It presents a debug
device which is fully compliant with the USB framework and provides the
equivalent of a very high performance full-duplex serial link. The debug
capability operation model and registers interface are defined in 7.6.8
of the xHCI specification, revision 1.1.
The DbC debug device shares a root port with the xHCI host. By default,
the debug capability is disabled and the root port is assigned to xHCI.
When the DbC is enabled, the root port will be assigned to the DbC debug
device, and the xHCI sees nothing on this port. This implementation uses
a sysfs node named <dbc> under the xHCI device to manage the enabling
and disabling of the debug capability.
When the debug capability is enabled, it will present a debug device
through the debug port. This debug device is fully compliant with the
USB3 framework, and it can be enumerated by a debug host on the other
end of the USB link. As soon as the debug device is configured, a TTY
serial device named /dev/ttyDBC0 will be created.
Signed-off-by: Lu Baolu <email address hidden>
Signed-off-by: Mathias Nyman <email address hidden>
Signed-off-by: Greg Kroah-Hartman <email address hidden>
(back ported from commit dfba2174dc421ecad8dc50741054a305cd3ba681)
Signed-off-by: Joseph Salisbury <email address hidden>
Signed-off-by: Thadeu Lima de Souza Cascardo <email address hidden>
