~kamalmostafa/ubuntu/+source/linux/+git/bionic:lp1730770

Branch merges

Related source package recipes

No recipes using this branch. (?)

Create packaging recipe

Related snap packages

Related charm recipes

9825d4e... by Rajneesh Bhardwaj <email address hidden> on 2018-02-02

platform/x86: intel_pmc_core: Special case for Coffeelake

BugLink: http://bugs.launchpad.net/bugs/1730770

Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in
this case PMC register details from Cannonlake PCH must be used.

In order to identify whether the given platform is Coffeelake, scan for the
Sunrisepoint PMC PCI Id.

  KBL CPUID SPT PCIID
------------------------------------
KBL | Y | Y |
------------------------------------
CFL | Y | N |
------------------------------------

Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 661405bd817b209ac9bd4812c63d90873a7f2993)
Signed-off-by: Kamal Mostafa <email address hidden>

497a9b1... by Rajneesh Bhardwaj <email address hidden> on 2018-02-02

platform/x86: intel_pmc_core: Add CannonLake PCH support

BugLink: http://bugs.launchpad.net/bugs/1730770

This adds support for Cannonlake PCH which is used by Cannonlake and
Coffeelake SoCs.

Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 291101f6a73566f5d1ab597784288c5bc85906fd)
Signed-off-by: Kamal Mostafa <email address hidden>

dcfa052... by Rajneesh Bhardwaj <email address hidden> on 2018-02-02

x86/cpu: Add Cannonlake to Intel family

BugLink: http://bugs.launchpad.net/bugs/1730770

Add CPUID of Cannonlake (CNL) processors to Intel family list.

Cc: Dave Hansen <email address hidden>
Cc: Thomas Gleixner <email address hidden>
cc: Ingo Molnar <email address hidden>
Cc: "H. Peter Anvin" <email address hidden>
Cc: <email address hidden>

Reviewed-by: Thomas Gleixner <email address hidden>
Suggested-by: Tony Luck <email address hidden>
Signed-off-by: Megha Dey <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 850eb9fba3711e98bafebde26675d9c082c0ff48)
Signed-off-by: Kamal Mostafa <email address hidden>

3ee10b0... by Srinivas Pandruvada on 2018-02-02

platform/x86: intel_pmc_core: Read base address from LPIT

BugLink: http://bugs.launchpad.net/bugs/1730770

Read SLP_S0 address from ACPI LPIT table when present and use PMC
specific SLP_S0 offset to get the base address of PMC MMIO.

Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 745698c37c08f48fb5ad3c0cb7ee955bd5701d4a)
Signed-off-by: Kamal Mostafa <email address hidden>

d11955b... by Srinivas Pandruvada on 2018-02-02

ACPI / LPIT: Export lpit_read_residency_count_address()

BugLink: http://bugs.launchpad.net/bugs/1730770

Export lpit_read_residency_count_address(), so that it can be used from
drivers built as module. With the recent changes, the builtin_pci
functionality of the intel_pmc_core driver is removed and now it can be
built as a module to read this exported interface to calculate the PMC base
address.

Cc: Rafael J. Wysocki <email address hidden>
Cc: Len Brown <email address hidden>
Cc: <email address hidden>

Acked-by: Rafael J. Wysocki <email address hidden>
Tested-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 9383bbadfe29fe8319e2245b75a508db9abd7b87)
Signed-off-by: Kamal Mostafa <email address hidden>

dbf21dc... by Rajneesh Bhardwaj <email address hidden> on 2018-01-31

platform/x86: intel_pmc_core: Remove unused header file

BugLink: http://bugs.launchpad.net/bugs/1730770

Recently sent patch 'platform/x86: intel_pmc_core: Remove unused EXPORTED
API' missed to remove the header file 'arch/x86/include/asm/pmc_core.h'
which was solely used to declare the EXPORTED API
'intel_pmc_slp_s0_counter_read'. This patch provides the errata fix for the
same.

Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 941691ef2197944a202d7870dcd7da3fb0391c65)
Signed-off-by: Kamal Mostafa <email address hidden>

003a1ba... by Rajneesh Bhardwaj <email address hidden> on 2018-01-19

platform/x86: intel_pmc_core: Convert to ICPU macro

BugLink: http://bugs.launchpad.net/bugs/1730770

Use ICPU macro to refactor code related to x86_cpu_id for better
readability.

Suggested-by: Andy Shevchenko <email address hidden>
Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 00f8b2fce4da2296bafc1de6a46510a13ef60938)
Signed-off-by: Kamal Mostafa <email address hidden>

3e99f60... by Srinivas Pandruvada on 2018-01-19

platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration

BugLink: http://bugs.launchpad.net/bugs/1730770

The Only use of PCI device enumeration here is to get the PMC base address
which is a fixed value i.e. 0xFE000000. On some platforms this can be read
through a non standard PCI BAR. But after Kabylake, PMC is not exposed as a
PCI device anymore. There are other non standard methods like ACPI LPIT
which can also be used for obtaining this value.

For simplicity, this value can be hardcoded as it won't change.

Since we don't have a PMC PCI device on any platform after Kabylake, this
creates a foundation for future SoC support.

Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 21ae43570940f8393a80369f62a3880bd64daad8)
Signed-off-by: Kamal Mostafa <email address hidden>

ee24337... by Rajneesh Bhardwaj <email address hidden> on 2018-01-19

platform/x86: intel_pmc_core: Refactor debugfs entries

BugLink: http://bugs.launchpad.net/bugs/1730770

When on a platform if we can't show MPHY and PLL status, don't even bother
to create a debugfs entry as it will fail anyway. In fact unless OEM builds
a special BIOS for test, it will fail on every production system.

This will help to add future platform support where we can't support these
entries.

Suggested-by: Andy Shevchenko <email address hidden>
Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 750e0f570b7145870d40f07337f3356c18e0abd4)
Signed-off-by: Kamal Mostafa <email address hidden>

dd19563... by Rajneesh Bhardwaj <email address hidden> on 2018-01-11

platform/x86: intel_pmc_core: Fix file permission warnings

BugLink: http://bugs.launchpad.net/bugs/1730770

Symbolic permissions 'S_IRUGO' are not preferred. This patch changes the
debugfs files to use octal permissions '0644' or '0444' as needed by the
attribute.

Signed-off-by: Srinivas Pandruvada <email address hidden>
Signed-off-by: Rajneesh Bhardwaj <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 1f644da7e920cb83403818efa88ebfb6d1528264)
Signed-off-by: Kamal Mostafa <email address hidden>