~kamalmostafa/ubuntu/+source/linux-aws/+git/disco:arm-update

Last commit made on 2019-10-30
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9ab6496... by Kamal Mostafa

UBUNTU: [Config] updateconfigs for arm64 errata

BugLink: https://bugs.launchpad.net/bugs/1850675

Signed-off-by: Kamal Mostafa <email address hidden>

ef09b9a... by James Morse <email address hidden>

UBUNTU: SAUCE: arm64: ftrace: Ensure synchronisation in PLT setup for Neoverse-N1 #1542419

BugLink: https://bugs.launchpad.net/bugs/1850675

CPUs affected by Neoverse-N1 #1542419 may execute a stale instruction if
it was recently modified. The affected sequence requires freshly written
instructions to be executable before a branch to them is updated.

There are very few places in the kernel that modify executable text,
all but one come with sufficient synchronisation:
 * The module loader's flush_module_icache() calls flush_icache_range(),
   which does a kick_all_cpus_sync()
 * bpf_int_jit_compile() calls flush_icache_range().
 * Kprobes calls aarch64_insn_patch_text(), which does its work in
   stop_machine().
 * static keys and ftrace both patch between nops and branches to
   existing kernel code (not generated code).

The affected sequence is the interaction between ftrace and modules.
The module PLT is cleaned using __flush_icache_range() as the trampoline
shouldn't be executable until we update the branch to it.

Drop the double-underscore so that this path runs kick_all_cpus_sync()
too.

Signed-off-by: James Morse <email address hidden>
Reference: https://lore<email address hidden>/
Signed-off-by: Kamal Mostafa <email address hidden>

6e0f6ce... by James Morse <email address hidden>

UBUNTU: SAUCE: arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space

BugLink: https://bugs.launchpad.net/bugs/1850675

Compat user-space is unable to perform ICIMVAU instructions from
user-space. Instead it uses a compat-syscall. Add the workaround for
Neoverse-N1 #1542419 to this code path.

Signed-off-by: James Morse <email address hidden>
Reference: https://lore<email address hidden>/
Signed-off-by: Kamal Mostafa <email address hidden>

112479d... by James Morse <email address hidden>

UBUNTU: SAUCE: arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419

BugLink: https://bugs.launchpad.net/bugs/1850675

Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
perform icache maintenance once new instructions are cleaned to the PoU.
For the errata workaround, the kernel hides DIC from user-space, so that
the unnecessary cache maintenance can be trapped by firmware.

To reduce the number of traps, produce a fake IminLine value based on
PAGE_SIZE.

Signed-off-by: James Morse <email address hidden>
Reference: https://lore<email address hidden>/
Signed-off-by: Kamal Mostafa <email address hidden>

9f0d93c... by James Morse <email address hidden>

UBUNTU: SAUCE: arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419

BugLink: https://bugs.launchpad.net/bugs/1850675

Cores affected by Neoverse-N1 #1542419 could execute a stale instruction
when a branch is updated to point to freshly generated instructions.

To workaround this issue we need user-space to issue unnecessary
icache maintenance that we can trap. Start by hiding CTR_EL0.DIC.

Signed-off-by: James Morse <email address hidden>
Reference: https://lore<email address hidden>/
Signed-off-by: Kamal Mostafa <email address hidden>

10a464d... by James Morse <email address hidden>

arm64: Update silicon-errata.txt for Neoverse-N1 #1349291

BugLink: https://bugs.launchpad.net/bugs/1850675

Neoverse-N1 affected by #1349291 may report an Uncontained RAS Error
as Unrecoverable. The kernel's architecture code already considers
Unrecoverable errors as fatal as without kernel-first support no
further error-handling is possible.

Now that KVM attributes SError to the host/guest more precisely
the host's architecture code will always handle host errors that
become pending during world-switch.
Errors misclassified by this errata that affected the guest will be
re-injected to the guest as an implementation-defined SError, which can
be uncontained.

Until kernel-first support is implemented, no workaround is needed
for this issue.

Signed-off-by: James Morse <email address hidden>
Signed-off-by: Marc Zyngier <email address hidden>
(cherry picked from commit 3276cc2489641f7f37e9558f5fe9d6ae17a25528)
Signed-off-by: Kamal Mostafa <email address hidden>

3955d25... by Marc Zyngier

arm64: Handle erratum 1418040 as a superset of erratum 1188873

BugLink: https://bugs.launchpad.net/bugs/1850675

We already mitigate erratum 1188873 affecting Cortex-A76 and
Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to
r3p1 of the same cores are affected by erratum 1418040, which
has the same workaround as 1188873.

Let's expand the range of affected revisions to match 1418040,
and repaint all occurences of 1188873 to 1418040. Whilst we're
there, do a bit of reformating in silicon-errata.txt and drop
a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND.

Signed-off-by: Marc Zyngier <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(backported from commit a5325089bd05a7b0259cc4038479d36308edbda2)
Signed-off-by: Kamal Mostafa <email address hidden>

2266d4b... by Marc Zyngier

arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1

BugLink: https://bugs.launchpad.net/bugs/1850675

Neoverse-N1 is also affected by ARM64_ERRATUM_1188873, so let's
add it to the list of affected CPUs.

Signed-off-by: Marc Zyngier <email address hidden>
[will: Update silicon-errata.txt]
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit 6989303a3b2d864fd8e17d3fa3365d3e9649a598)
Signed-off-by: Kamal Mostafa <email address hidden>

f7e55a4... by Marc Zyngier

arm64: Add part number for Neoverse N1

BugLink: https://bugs.launchpad.net/bugs/1850675

New CPU, new part number. You know the drill.

Signed-off-by: Marc Zyngier <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit 0cf57b86859c49381addb3ce47be70aadf5fd2c0)
Signed-off-by: Kamal Mostafa <email address hidden>

47d6cd2... by Marc Zyngier

arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT

BugLink: https://bugs.launchpad.net/bugs/1850675

Since ARM64_ERRATUM_1188873 only affects AArch32 EL0, it makes some
sense that it should depend on COMPAT.

Signed-off-by: Marc Zyngier <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(cherry picked from commit c2b5bba3967a000764e9148e6f020d776b7ecd82)
Signed-off-by: Kamal Mostafa <email address hidden>