Compat user-space is unable to perform ICIMVAU instructions from
user-space. Instead it uses a compat-syscall. Add the workaround for
Neoverse-N1 #1542419 to this code path.
Signed-off-by: James Morse <email address hidden>
Signed-off-by: Catalin Marinas <email address hidden>
(cherry picked from commit 222fc0c8503d98cec3cb2bac2780cdd21a6e31c0)
Signed-off-by: Kamal Mostafa <email address hidden>
Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
perform icache maintenance once new instructions are cleaned to the PoU.
For the errata workaround, the kernel hides DIC from user-space, so that
the unnecessary cache maintenance can be trapped by firmware.
To reduce the number of traps, produce a fake IminLine value based on
PAGE_SIZE.
Signed-off-by: James Morse <email address hidden>
Reviewed-by: Suzuki K Poulose <email address hidden>
Signed-off-by: Catalin Marinas <email address hidden>
(cherry picked from commit ee9d90be9ddace01b7fb126567e4b539fbe1f82f)
Signed-off-by: Kamal Mostafa <email address hidden>
When there is a mismatch in the CTR_EL0 field, we trap
access to CTR from EL0 on all CPUs to expose the safe
value. However, we could skip trapping on a CPU which
matches the safe value.
Cc: Mark Rutland <email address hidden>
Cc: Will Deacon <email address hidden>
Signed-off-by: Suzuki K Poulose <email address hidden>
Signed-off-by: Catalin Marinas <email address hidden>
(cherry picked from commit 4afe8e79da920bdf6698b01bc668fffc6758f37b)
Signed-off-by: Kamal Mostafa <email address hidden>
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
The following two control bits DIC and IDC were defined for this
purpose. No need to perform point of unification cache maintenance
operations from software on systems where CPU caches are transparent.
This patch optimize the three functions __flush_cache_user_range(),
clean_dcache_area_pou() and invalidate_icache_range() if the hardware
reports CTR_EL0.IDC and/or CTR_EL0.IDC. Basically it skips the two
instructions 'DC CVAU' and 'IC IVAU', and the associated loop logic
in order to avoid the unnecessary overhead.
CTR_EL0.DIC: Instruction cache invalidation requirements for
instruction to data coherence. The meaning of this bit[29].
0: Instruction cache invalidation to the point of unification
is required for instruction to data coherence.
1: Instruction cache cleaning to the point of unification is
not required for instruction to data coherence.
CTR_EL0.IDC: Data cache clean requirements for instruction to data
coherence. The meaning of this bit[28].
0: Data cache clean to the point of unification is required for
instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Co-authored-by: Philip Elcan <email address hidden>
Reviewed-by: Mark Rutland <email address hidden>
Signed-off-by: Shanker Donthineni <email address hidden>
Signed-off-by: Will Deacon <email address hidden>
(backported from commit 6ae4b6e0578886eb36cedbf99f04031d93f9e315)
Signed-off-by: Kamal Mostafa <email address hidden>
