Unfortunately, the architecture provides no means to determine the bit
width of the system counter. However, we do know the following from the
specification:
- the system counter is at least 56 bits wide
- Roll-over time of not less than 40 years
To date, the arch timer driver has depended on the first property,
assuming any system counter to be 56 bits wide and masking off the rest.
However, combining a narrow clocksource mask with a high frequency
counter could result in prematurely wrapping the system counter by a
significant margin. For example, a 56 bit wide, 1GHz system counter
would wrap in a mere 2.28 years!
This is a problem for two reasons: v8.6+ implementations are required to
provide a 64 bit, 1GHz system counter. Furthermore, before v8.6,
implementers may select a counter frequency of their choosing.
Fix the issue by deriving a valid clock mask based on the second
property from above. Set the floor at 56 bits, since we know no system
counter is narrower than that.
[maz: fixed width computation not to lose the last bit, added
max delta generation for the timer]
Suggested-by: Marc Zyngier <email address hidden>
Signed-off-by: Oliver Upton <email address hidden>
Reviewed-by: Linus Walleij <email address hidden>
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit c1153d52c4140424a5e31a5916fca3edd91fe13a)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.
This reduces the number of ISBs from 3 to 2 when programming
the timer.
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit ec8f7f3342c88780d682cc2464daf0fe43259c4f)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
The Applied Micro XGene-1 SoC has a busted implementation of the
CVAL register: it looks like it is based on TVAL instead of the
other way around. The net effect of this implementation blunder
is that the maximum deadline you can program in the timer is
32bit wide.
Use a MIDR check to notice the broken CPU, and reduce the width
of the timer to 32bit.
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit 012f188504528b8cb32f441ac3bd9ea2eba39c9e)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
Similarily to the sysreg-based timer, move the MMIO over to using
the CVAL registers instead of TVAL. Note that there is no warranty
that the 64bit MMIO access will be atomic, but the timer is always
disabled at the point where we program CVAL.
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit 8b82c4f883a7b22660464c0232fbdb7a6deb3061)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
The MMIO timer base address gets published after we have registered
the callbacks and the interrupt handler, which is... a bit dangerous.
Fix this by moving the base address publication to the point where
we register the timer, and expose a pointer to the timer structure
itself rather than a naked value.
Reviewed-by: Oliver Upton <email address hidden>
Reviewed-by: Mark Rutland <email address hidden>
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit 72f47a3f0ea4cda4ca5d90c0d6043f697b9b0647)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
In order to cope better with high frequency counters, move the
programming of the timers from the countdown timer (TVAL) over
to the comparator (CVAL).
The programming model is slightly different, as we now need to
read the current counter value to have an absolute deadline
instead of a relative one.
There is a small overhead to this change, which we will address
in the following patches.
Reviewed-by: Oliver Upton <email address hidden>
Reviewed-by: Mark Rutland <email address hidden>
Tested-by: Mark Rutland <email address hidden>
Signed-off-by: Marc Zyngier <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Daniel Lezcano <email address hidden>
(cherry picked from commit a38b71b0833eb2fabd2b1fa37d665c0a88b8b7e4)
Signed-off-by: John Cabaj <email address hidden>
Acked-by: Tim Gardner <email address hidden>
Acked-by: Manuel Diewald <email address hidden>
Signed-off-by: John Cabaj <email address hidden>
