x86/virt/tdx: Explicitly save/restore RBP for seamcall_saved_ret()
The currently available version of TDX module that support NO_RBP_MOD
doesn't work with TDH.VP.ENTER(). As workaround, don't set NO_RBP_MOD
and make __seamcall_saved_ret() explicitly save/restore RBP.
TODO: Once the new version of the TDX module, or the corrected behavior of
TDH.VP.ENTER(), is available, drop this patch.
The TDX module doesn't allow VMM to disable CPUID.MTRR
(CPUID[EAX=1].EDX[12]) bit. It forcibly sets the bit to 1(MTRR available)
unconditionally and VMM can't change it. The v6.5 guest kernel doesn't
disable MTRR explicitly. It uses CPUID.MTRR and results in a kernel panic
when setting CR4.CD=1 to disable cache during programming MTRRs.
The guest kernel has Xen MTRR disablement.
Commit f9626104a5b6 ("x86/mm/mtrr: Generalize runtime disabling of MTRRs")
When MTRR is available and MTRRdefType.enable = 0 as BIOS hand-off state,
the kernel pretends as MTRR isn't available. That is a deviation from SDM
because MTRRdefType.enable = 0 means all memory access is UC according to
the SDM.
Mimic the Xen guest MTRR disablement for the TD guest kernel to boot.
Other workaround is to pass "clearcpuid=mtrr" to the guest kernel command
line.
KVM: X86: Add a capability to configure bus frequency for APIC timer
Add KVM_CAP_X86_BUS_FREQUENCY_CONTROL capability to configure the core
crystal clock (or processor's bus clock) for APIC timer emulation. Allow
KVM_ENABLE_CAPABILITY(KVM_CAP_X86_BUS_FREQUENCY_CONTROL) to set the
frequency. When using this capability, the user space VMM may configure
CPUID[0x15] to advertise the frequency. The guest determine the frequency
based on CPUID[0x15] or other known clock.
TDX virtualizes CPUID[0x15] for the core crystal clock to be 25MHz. The
x86 KVM hardcodes its frequency for APIC timer to be 1GHz. This mismatch
causes the vAPIC timer to fire earlier than the guest expects. [1] The KVM
APIC timer emulation uses hrtimer, whose unit is nanosecond. Make the
parameter configurable for conversion from the TMICT value to nanosecond.
This patch doesn't affect the TSC deadline timer emulation. The TSC
deadline emulation path records its expiring TSC value and calculates the
expiring time in nanoseconds. The APIC timer emulation path calculates the
TSC value from the TMICT register value and uses the TSC deadline timer
path. This patch touches the APIC timer-specific code but doesn't touch
common logic.
