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4400. By Colin Ian King on 2019-08-19

fwtstest: syntaxcheck-0001: update to keep in sync with ACPICA features

We now have Legacy Processor() keyword detection, so add this
to the output from the syntaxcheck test.

Signed-off-by: Colin Ian King <email address hidden>
Acked-by: Alex Hung <email address hidden>
Acked-by: Ivan Hu <email address hidden>

4399. By Colin Ian King on 2019-08-19

ACPICA: Update to version 20190816

Changes in this release of ACPICA are detailed at the following
link on the ACPICA developer mailing list:

https://lists.acpica.org/pipermail/devel/2019-August/001949.html

Also changed the fwtsiasl makefile to build new dtcompilerparser

Signed-off-by: Colin Ian King <email address hidden>
Acked-by: Alex Hung <email address hidden>
Acked-by: Ivan Hu <email address hidden>

4398. By Colin Ian King on 2019-08-07

efi_runtime: enable KBUILD_MODPOST_WARN=y to workaround build failures

With newer kernels > 5.0, undefined variables now throw an error
rather than a warning. Force the older warning behaviour so that
dkms builds can pass ADT build testing.

Signed-off-by: Colin Ian King <email address hidden>
Acked-by: Ivan Hu <email address hidden>
Acked-by: Alex Hung <email address hidden>

4397. By nbhat on 2019-08-05

README: Add package dependency notes for ARM64

Add package dependency notes for Ubuntu on ARM64

Signed-off-by: Naresh Bhat <email address hidden>
Acked-by: Colin Ian King <email address hidden>
Acked-by: Alex Hung <email address hidden>

4396. By Alex Hung on 2019-07-25

lib: fwts_version.h - update to V19.07.00

Signed-off-by: Alex Hung <email address hidden>

4395. By Alex Hung on 2019-07-25

debian: update changelog

Signed-off-by: Alex Hung <email address hidden>

4394. By Alex Hung on 2019-07-25

cpu/msr: update MISC_ENABLE to IA32_silvermont_MSRs

MISC_ENABLE in silvermont has one more feature than the one defined in
architectural MSRs (IA32_MSRs): BIT38 - Turbo Mode Disable (R/W).

Signed-off-by: Alex Hung <email address hidden>
Acked-by: Colin Ian King <email address hidden>
Acked-by: Ivan Hu <email address hidden>

4393. By Alex Hung on 2019-07-25

cpu/msr: update THERM_INTERRUPT MSR masks

BIT definition is as below:

0 High-Temperature Interrupt Enable
1 Low-Temperature Interrupt Enable
2 PROCHOT# Interrupt Enable
3 FORCEPR# Interrupt Enable
4 Critical Temperature Interrupt Enable
7:5 Reserved
14:8 Threshold #1 Value
15 Threshold #1 Interrupt Enable
22:16 Threshold #2 Value
23 Threshold #2 Interrupt Enable
24 Power Limit Notification Enable
63:25 Reserved

Signed-off-by: Alex Hung <email address hidden>
Acked-by: Colin Ian King <email address hidden>
Acked-by: Ivan Hu <email address hidden>

4392. By Alex Hung on 2019-07-25

cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs

BIT definition is as below:

0 L2 Hardware Enabled (RO)
7:1 Reserved
8 L2 Enabled (R/W)
22:9 Reserved
23 L2 Not Present (RO)
63:24 Reserved

Signed-off-by: Alex Hung <email address hidden>
Acked-by: Ivan Hu <email address hidden>
Acked-by: Colin Ian King <email address hidden>

4391. By Alex Hung on 2019-07-25

cpu/msr: add MSR_TEMPERATURE_TARGET to IA32_silvermont_MSRs

BIT definition is as below:

15:0 Reserved
23:16 Temperature Target (R)
29:24 Target Offset (R/W)

Signed-off-by: Alex Hung <email address hidden>
Acked-by: Ivan Hu <email address hidden>
Acked-by: Colin Ian King <email address hidden>