lp:~danilovesky/workcraft/trank-bug-1455185

Created by Danil Sokolov and last modified
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Owner:
Danil Sokolov
Project:
Workcraft
Status:
Merged

Recent revisions

622. By Danil Sokolov

Correction for trace processing for hierarchical circuits.

621. By Danil Sokolov

Fix for preserving node names inside pages on copy-pase.

620. By Danil Sokolov

Handling the drivers of the output ports that are inside pages.

619. By Danil Sokolov

Better validation of connections in Circuits plugin.

618. By Danil Sokolov

Dealing wiht forks on primariry outputs.

617. By Danil Sokolov

Improvements to Connection tools od circuit and STG.

616. By Danil Sokolov

Fix for highlighting of the nodes excited by the current trace event.

615. By Danil Sokolov

Translation of the STG trace to circuit trace.

614. By Danil Sokolov

Initial attempt to simulate composed STG trace in a circuit.

613. By Danil Sokolov

Fixed a bug in Circuit STG simplification algorithm.

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Branch format 6
Repository format:
Bazaar pack repository format 1 with rich root (needs bzr 1.0)
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